Description:
Write a small RV32I assembly program that generates the “F1 light” pattern using the CPU’s memory-mapped output port.
The program should repeatedly write a shifting bit-pattern (e.g., 0b0001 → 0010 → 0100 → 1000 → 0001) to the device address specified in the project brief (e.g., 0xFFFF0000 or your team’s chosen MMIO base address).
Add a simple delay loop between updates to make the pattern visible in simulation.
Output binary and hex versions (.bin and .hex) for loading into instruction memory during cpu_top verification.
Acceptance Criteria:
Pure RV32I assembly (no pseudo-instructions).
Verified on Ripes / Venus / Spike before integration.
Produces correct memory-mapped writes visible in Verilator testbench.
Integrated into programs/ folder with a Makefile or script to assemble to .hex.
Description:
Write a small RV32I assembly program that generates the “F1 light” pattern using the CPU’s memory-mapped output port.
The program should repeatedly write a shifting bit-pattern (e.g., 0b0001 → 0010 → 0100 → 1000 → 0001) to the device address specified in the project brief (e.g., 0xFFFF0000 or your team’s chosen MMIO base address).
Add a simple delay loop between updates to make the pattern visible in simulation.
Output binary and hex versions (.bin and .hex) for loading into instruction memory during cpu_top verification.
Acceptance Criteria:
Pure RV32I assembly (no pseudo-instructions).
Verified on Ripes / Venus / Spike before integration.
Produces correct memory-mapped writes visible in Verilator testbench.
Integrated into programs/ folder with a Makefile or script to assemble to .hex.