Create a Verilator integration testbench for cpu_top.sv.
Load a small RV32I program into instruction memory (addi/add/lw/sw/branch/jump) and simulate multiple cycles.
Check: correct PC progression, register file updates, ALU results, memory accesses, branch decisions, and final architectural state.
Testbench should step the clock, monitor internal signals, and assert expected results at key cycles.
Goal: verify that the entire single-cycle CPU executes short instruction sequences correctly end-to-end.
Create a Verilator integration testbench for cpu_top.sv.
Load a small RV32I program into instruction memory (addi/add/lw/sw/branch/jump) and simulate multiple cycles.
Check: correct PC progression, register file updates, ALU results, memory accesses, branch decisions, and final architectural state.
Testbench should step the clock, monitor internal signals, and assert expected results at key cycles.
Goal: verify that the entire single-cycle CPU executes short instruction sequences correctly end-to-end.