Implement cpu_top.sv that instantiates and connects all single-cycle components: PC, Instruction Memory, Controlpath, Datapath, Data Memory (and any small adders/muxes if not already inside datapath).
Clock/reset enter only at this level.
cpu_top should:
Wire PC ↔ InstrMem ↔ Datapath
Pass instruction fields to Controlpath
Pass control signals from Controlpath to Datapath
Connect Datapath to Data Memory and writeback path
Ready to be used as the DUT in full-CPU testbenches (no verification here,
Implement cpu_top.sv that instantiates and connects all single-cycle components: PC, Instruction Memory, Controlpath, Datapath, Data Memory (and any small adders/muxes if not already inside datapath).
Clock/reset enter only at this level.
cpu_top should:
Wire PC ↔ InstrMem ↔ Datapath
Pass instruction fields to Controlpath
Pass control signals from Controlpath to Datapath
Connect Datapath to Data Memory and writeback path
Ready to be used as the DUT in full-CPU testbenches (no verification here,