Description:
Create a unit-level Verilator testbench for the datapath module.
Test basic instruction flows (addi, add, lw, sw, branch).
Check correct PC updates, immediate generation, ALU operand routing, memory interface wiring, and writeback mux selection.
No control logic inside the DUT — all control signals driven manually by the testbench.
Description:
Create a unit-level Verilator testbench for the datapath module.
Test basic instruction flows (addi, add, lw, sw, branch).
Check correct PC updates, immediate generation, ALU operand routing, memory interface wiring, and writeback mux selection.
No control logic inside the DUT — all control signals driven manually by the testbench.