Description:
Implement the single-cycle datapath module. This is structural wiring only. Instantiate PC, Instruction Memory, Register File, Immediate Extend, ALU, Data Memory, PC+4 adder, branch/jump target adder, and the writeback mux. Connect them according to the Task 1 diagram.
Expose ports for control signals (alu_src, alu_op, reg_write, mem_read, mem_write, mem_to_reg, branch, jump).
No decoding logic here—only wires and module instances.
Description:
Implement the single-cycle datapath module. This is structural wiring only. Instantiate PC, Instruction Memory, Register File, Immediate Extend, ALU, Data Memory, PC+4 adder, branch/jump target adder, and the writeback mux. Connect them according to the Task 1 diagram.
Expose ports for control signals (alu_src, alu_op, reg_write, mem_read, mem_write, mem_to_reg, branch, jump).
No decoding logic here—only wires and module instances.