Create a set of tiny RISC-V programs to test core CPU features: Register writes ADD/SUB LW/SW BEQ loops PC branch behaviour A mini F1-like counter loop if needed Compile to .hex using riscv64-unknown-elf-as + objcopy.
Create a set of tiny RISC-V programs to test core CPU features:
Register writes
ADD/SUB
LW/SW
BEQ loops
PC branch behaviour
A mini F1-like counter loop if needed
Compile to .hex using riscv64-unknown-elf-as + objcopy.