led.sv

module led(
  input  logic         clk_i,
  input  logic         rst_i,

  input  logic [15:0]  sw_i,

  output logic         LED16_B,
  output logic         LED16_G,
  output logic         LED16_R,
  output logic [7:0]   an_o,
  output logic         ca_o,
  output logic         cb_o,
  output logic         cc_o,
  output logic         cd_o,
  output logic         ce_o,
  output logic         cf_o,
  output logic         cg_o
);

  logic  [5:0]   red;
  logic  [5:0]   blue;
  logic  [5:0]   green;
  logic          led_red_reg;
  logic          led_green_reg;
  logic          led_blue_reg;
  logic  [6:0]   seg;
  logic  [6:0]   seg_reg;
  logic  [7:0]   an_reg;
  logic  [7:0]   an_next;
  logic  [5:0]   cnt_my_ff;
  logic  [9:0]  clk_div_ff;
  logic  [2:0]   scan_cnt_ff;
  logic  [3:0]   dc_hex_data;
  logic  [7:0]   red_8;
  logic  [7:0]   green_8;
  logic  [7:0]   blue_8;
  logic  [23:0]  hex_RGB;

  assign red      =  {sw_i[15:11], sw_i[11]};
  assign green    =  sw_i[10:5];
  assign blue     =  {sw_i[4:0], sw_i[0]};
  assign red_8    =  {red, red[5:4]};
  assign green_8  =  {green, green[5:4]};
  assign blue_8   =  {blue, blue[5:4]};
  assign hex_RGB  =  {red_8, green_8, blue_8};

  always_ff @( posedge clk_i or negedge rst_i ) begin
    if ( !rst_i )
      cnt_my_ff <= 6'd0;
    else
      cnt_my_ff <= cnt_my_ff + 1'b1;
  end

  always_ff @( posedge clk_i or negedge rst_i) begin
    if ( !rst_i ) begin
      led_red_reg    <=  1'b0;
      led_green_reg  <=  1'b0;
      led_blue_reg   <=  1'b0;
    end else begin
      led_red_reg    <= ( cnt_my_ff < red );
      led_green_reg  <= ( cnt_my_ff < green );
      led_blue_reg   <= ( cnt_my_ff < blue );
    end
  end

  assign  LED16_R  =  led_red_reg;
  assign  LED16_G  =  led_green_reg;
  assign  LED16_B  =  led_blue_reg;

  always_ff @( posedge clk_i or negedge rst_i ) begin
    if ( !rst_i )
      clk_div_ff <= 10'd0;
    else
      clk_div_ff <= clk_div_ff + 1;
  end

  always_ff @( posedge clk_i or negedge rst_i ) begin
    if ( !rst_i )
      scan_cnt_ff <= 3'd0;
    else if( clk_div_ff == 0)
      scan_cnt_ff <= scan_cnt_ff + 1;
  end

  always_comb begin
    case ( scan_cnt_ff )
      3'b000: dc_hex_data = hex_RGB[3:0];
      3'b001: dc_hex_data = hex_RGB[7:4];
      3'b010: dc_hex_data = hex_RGB[11:8];
      3'b011: dc_hex_data = hex_RGB[15:12];
      3'b100: dc_hex_data = hex_RGB[19:16];
      3'b101: dc_hex_data = hex_RGB[23:20];
    endcase
  end

  always_comb begin
    case( dc_hex_data )
      4'h0:    seg = 7'b1000000;
      4'h1:    seg = 7'b1111001;
      4'h2:    seg = 7'b0100100;
      4'h3:    seg = 7'b0110000;
      4'h4:    seg = 7'b0011001;
      4'h5:    seg = 7'b0010010;
      4'h6:    seg = 7'b0000010;
      4'h7:    seg = 7'b1111000;
      4'h8:    seg = 7'b0000000;
      4'h9:    seg = 7'b0010000;
      4'ha:    seg = 7'b0001000;
      4'hb:    seg = 7'b0000011;
      4'hc:    seg = 7'b1000110;
      4'hd:    seg = 7'b0100001;
      4'he:    seg = 7'b0000110;
      4'hf:    seg = 7'b0001110;
      default: seg = 7'b1111111;
    endcase
  end

  always_ff @(posedge clk_i or negedge rst_i) begin
    if (!rst_i)
      seg_reg <= 7'b1111111;
    else
      seg_reg <= seg;
  end

  always_comb begin
    case ( scan_cnt_ff )
      3'b000:  an_next = 8'b11111110;
      3'b001:  an_next = 8'b11111101;
      3'b010:  an_next = 8'b11111011;
      3'b011:  an_next = 8'b11110111;
      3'b100:  an_next = 8'b11101111;
      3'b101:  an_next = 8'b11011111;
      default: an_next = 8'b11111111;
    endcase
  end

  always_ff @(posedge clk_i or negedge rst_i) begin
  if (!rst_i)
    an_reg <= 8'b11111111;
  else
    an_reg <= an_next;
  end

  assign an_o = an_reg;

  assign ca_o = seg_reg[0];
  assign cb_o = seg_reg[1];
  assign cc_o = seg_reg[2];
  assign cd_o = seg_reg[3];
  assign ce_o = seg_reg[4];
  assign cf_o = seg_reg[5];
  assign cg_o = seg_reg[6];

endmodule