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IFU-dev-20260706-v2.17
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Ifu dev 20260706 v2.17#660
AllenFarcas wants to merge 196 commits into
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IFU-dev-20260706-v2.17

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Description

Please include a brief summary of the changes, relevant motivation and context.

Fixes # (issue)

Type of change

  • Documentation change (change only to the documentation, either a fix or a new content)
  • Bug fix (non-breaking change which fixes an issue)
  • New feature (non-breaking change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to not work as expected)
  • Infra/Build change
  • Code refactoring

Changes

Please list the changes introduced in this PR:

  • Change A
  • Change B

Checklist:

  • I have read and followed the contributing guidelines
  • The functionality is complete
  • I have commented my code, particularly in hard-to-understand areas
  • I have made corresponding changes to the documentation
  • My changes generate no new warnings
  • I have added tests that prove my fix is effective or that my feature works
  • New and existing unit tests pass locally with my changes

ptrendx and others added 30 commits April 20, 2026 11:45
Signed-off-by: Przemek Tredak <[email protected]>
* Reduced padding kernel compilation time

Signed-off-by: Oleg Goncharov <[email protected]>

* Completely removed unroll for better performance

Signed-off-by: Oleg Goncharov <[email protected]>

---------

Signed-off-by: Oleg Goncharov <[email protected]>
…(#2905)

Zero out padded region when swizzling via group quantize

Signed-off-by: Kirthi Shankar Sivamani <[email protected]>
…2879)

* fix broken links in README

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* update README to modernize description and standardize terminology

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* Update README.rst

Co-authored-by: greptile-apps[bot] <165735046+greptile-apps[bot]@users.noreply.github.com>
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* Removed the duplicate line

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---------

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* initial implementation for mxfp8

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* semi-working FP8; broken F16

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* comment out F16 pass

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* pull in grouped_quantize for MXFP8

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* grouped tensor - pytorch

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* quantize mxfp8

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* fix unfused; clean up

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…929)

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Comment thread build_tools/jax.py
Comment thread ci/pytorch.sh
Comment thread tests/cpp/operator/test_cast_mxfp4_transpose.cu
Comment thread tests/pytorch/distributed/fsdp2_tests/run_fsdp2_fused_adam.py Outdated
Comment thread tests/pytorch/distributed/fsdp2_tests/run_fsdp2_mem_leak.py Outdated
Comment thread transformer_engine/common/cast/nvfp4/rowwise_amax_nvfp4.cuh
if is_hip_extension():
# Fully-masked striped steps must contribute nothing; the CK kernel can
# emit non-finite output/LSE for them, so neutralize to avoid 0 * NaN.
softmax_aux_per_step = jnp.where(

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I think this issue is worth a new git ticket for fully understanding.

If it's a CK issue in gfx942, we may need to report to CK team.

Comment thread transformer_engine/jax/csrc/extensions/topk.cpp Outdated
Comment thread transformer_engine/pytorch/tensor/storage/nvfp4_tensor_storage.py
Comment thread transformer_engine/pytorch/triton_kernels/cast.py
AllenFarcas and others added 4 commits July 22, 2026 12:28
Use pathlib.Path(sys.executable) / pathlib.Path(__file__).resolve() like
upstream and test_cast_master_weights_to_fp8; drop the stale TODO. Verified
test_distributed_fuser_ops passes on ROCm (world_size 1 and 2).

Co-Authored-By: Claude Opus 4.8 (1M context) <[email protected]>
NVFP4 on gfx942 was simulation-only and required fnuz-specific workarounds
that were only needed because the fnuz e4m3 block scale (max 240) differs
from OCP (448). Restrict NVFP4 to gfx950 (gfx1250 remains behind the
existing TODO) and revert the fnuz workarounds:

- quantization.py: NVFP4 arch gate ((9,4),(9,5)) -> ((9,5),); message updated.
  FP8 / block-scaling gates keep (9,4) (unaffected).
- dequantize_nvfp4.cuh: drop the arch-aware factor_inv branch; use the
  upstream 1/(6*E4M3_MAX) form (no-op on gfx950/OCP).
- quantization_ref_nvfp4.py: simplify all is_fp8_fnuz() branches to 448 and
  drop the now-unused import (no-op on gfx950).

On gfx942 NVFP4 now reports unavailable, so all pytorch NVFP4 tests skip via
the centralized _compute_nvfp4_support gate; gfx950 behavior is unchanged.

Co-Authored-By: Claude Opus 4.8 (1M context) <[email protected]>
Follow-up to bffa8f0, trimmed to the necessary changes:
- quantization_ref_nvfp4.py: keep only the be3feea revert (global scale);
  restore the incidental is_fp8_fnuz cleanup (no-op on gfx950, unreached on
  gfx942) to keep the diff minimal.
- test_dequantize_nvfp4.cu: skip on gfx942 (te_fp8_fnuz) — the dequant kernel
  now uses OCP 448 while its reference is fnuz-240, so it fails there.
- test_nvfp4_rht_quantize_exact.py: gate the ROCm-only test_hadamard_transform_amax
  on recipe_available (was IS_HIP_EXTENSION-only; uses the reverted reference).

Drops the unnecessary cast/grouped-gemm cpp skips (those tests pass on gfx942).

Co-Authored-By: Claude Opus 4.8 (1M context) <[email protected]>
68bc6e0 added the te_fp8_fnuz() skip to the CUDA-branch dequant bodies
(#else of __HIP_PLATFORM_AMD__), which don't run on ROCm — so gfx942 still
failed — and would break the CUDA build (te_fp8_fnuz is ROCm-only). Move the
skip to the ROCm-branch DequantizeNVFP4 test body (the one that actually runs
on gfx942) and drop it from the CUDA bodies.

Co-Authored-By: Claude Opus 4.8 (1M context) <[email protected]>
@AllenFarcas

AllenFarcas commented Jul 22, 2026

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@ipanfilo @wangye805 related to your comment on tests/pytorch/distributed/test_fusible_ops.py line 1049 "TODO probably is not applicable - we know why the code is different. So it should rather be other comment, similar to test_cast_master_weights_to_fp8() which later solved the same problem"

I cannot comment there but ill add here my reply: I replaced the TODO with an explanatory comment in the # ROCm: style used in test_cast_master_weights_to_fp8.py: # ROCm: fnuz FP8 (gfx942) caps E4M3 at 240; OCP (gfx950+/CUDA) caps at 448., so the reference max must branch on is_fp8_fnuz(). Also removed an unused transformer_engine_torch import left behind.

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Number of files have AMD copyright header incorrect format

Comment thread ci/pytorch.sh
Comment thread tests/pytorch/attention/test_attention_with_cp.py
Comment thread tests/pytorch/distributed/test_fusible_ops.py
Comment thread tests/pytorch/test_grouped_linear.py
Comment thread tests/pytorch/test_grouped_linear.py
Comment thread transformer_engine/common/cast/nvfp4/rowwise_amax_nvfp4.cuh
import transformer_engine_torch as tex

from transformer_engine.common.recipe import Recipe
from transformer_engine.pytorch.tensor._quantization_helpers import (

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So on ROCm _quantized_helpers import quntized_tensor? Why?

Comment thread transformer_engine/pytorch/quantization.py
@AllenFarcas

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@ipanfilo In response to your question about _quantized_helpers: the import was removed because it was the load-time dependency creating the quantized_tensor -> tensor/init -> quantized_tensor cycle on ROCm.

The cycle is ROCm-specific because init_mxfp4_extension() (guarded by #ifdef USE_ROCM in pybind) imports mxfp4_tensor -> triton_kernels.cast -> quantized_tensor at extension load, entering it before the tensor package; on CUDA that block is compiled out.

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@ipanfilo I fixed all remaining AMD copyright and added any missing ones.

@AllenFarcas
AllenFarcas requested review from ipanfilo July 23, 2026 16:13
@AllenFarcas
AllenFarcas marked this pull request as ready for review July 23, 2026 16:13
@AllenFarcas AllenFarcas added ci-level 1 CI test level 1 and removed ci-level 1 CI test level 1 labels Jul 23, 2026
AllenFarcas and others added 3 commits July 23, 2026 20:31
new_empty([]) crashed staging a rank-0 NVFP4 placeholder; shape it like
the source instead. The per-tensor amax rides fsdp_pre_all_gather metadata,
which async DCP bf16-casts, so async cannot be bit-exact -- use the documented
loose tolerance (as with Float8CurrentScaling). Sync stays bit-exact.

Co-Authored-By: Claude Opus 4.8 (1M context) <[email protected]>
TE caches the FP8 weight columnwise transpose during forward instead of
recreating it in backward, accumulating ~0.68 MiB/layer under FSDP2. The
modules already skip caching when use_fsdp2 is set, which the test never did;
enable use_fsdp2 on submodules in _shard_model after sharding.

Also trims the verbose new_empty comment added in the prior NVFP4 async-DCP fix.

Co-Authored-By: Claude Opus 4.8 (1M context) <[email protected]>
# Conflicts:
#	transformer_engine/common/fused_attn_rocm/fused_attn.cpp
@AllenFarcas AllenFarcas added the ci-level 3 CI test level 3 label Jul 23, 2026
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@ipanfilo I fixed all remaining AMD copyright and added any missing ones.
It doesn't seem so. There are still files with wrong copyright header format

__device__ __forceinline__ float compute_global_encode_scaling_factor_FP4(const float global_amax) {
using namespace detail;
constexpr float fp8_max = TypeExtrema<fp8e4m3>::max; // 448.0f;
static_assert(E4M3_MAX == 448 || E4M3_MAX == 256, "Unsupported NVFP4 E4M3 max.");
constexpr float fp8_max = static_cast<float>(E4M3_MAX);

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Are any of those changes ROCm specific or all come from upstream?

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