[PyTorchSim] Add sin,cos instruction

Author: YWHyuk

src/arch/riscv/isa/decoder.isa

@@ -4859,12 +4859,12 @@ decode QUADRANT default Unknown::unknown() {
             0xb: decode VM {
                 0x0: VectorNonSplitFormat::vexp_v({{
                     Vd_vu[0] = Vs2_vu[0];
-                }}, OPFVV, CustomMatMulvexpOp);
+                }}, OPFVV, CustomVexpOp);
             }
             0x8: decode VM {
                 0x0: VectorNonSplitFormat::verf_v({{
                     Vd_vu[0] = Vs2_vu[0];
-                }}, OPFVV, CustomMatMulverfOp);
+                }}, OPFVV, CustomVerfOp);
                 0x1: VectorNonSplitFormat::iVpush_v({{
                     auto v_temp = Vs2_vu;
                     v_temp[0] = 0;
@@ -4873,12 +4873,17 @@ decode QUADRANT default Unknown::unknown() {
             0x9: decode VM {
                 0x0: VectorNonSplitFormat::vtanh_v({{
                     Vd_vu[0] = Vs2_vu[0];
-                }}, OPFVV, CustomMatMulvtanhOp);
+                }}, OPFVV, CustomVtanhOp);
                 0x1: VectorNonSplitFormat::wVpush_v({{
                     auto v_temp = Vs2_vu;
                     v_temp[0] = 0;
                 }}, OPFVV, CustomMatMulwVpushOp);
             }
+            0x10: decode VM {
+                0x0: VectorNonSplitFormat::vsin_v({{
+                    Vd_vu[0] = Vs2_vu[0];
+                }}, OPFVV, CustomVsinOp);
+            }
         }
     }
 

src/arch/riscv/isa/formats/vector_arith.isa

@@ -1195,6 +1195,32 @@ def format VectorNonSplitFormat(code, category, *flags) {{
         decoder_output = VectorNonSplitConstructor.subst(iop)
         exec_output = VectorIntNonSplitExecute.subst(iop)
         decode_block = VectorIntNonSplitDecodeBlock.subst(iop)
+    elif inst_name == "vsin" :
+        iop = InstObjParams(name,
+            Name,
+            'VectorNonSplitInst',
+            {'code': code,
+             'vm_decl_rd': vm_decl_rd,
+             'set_vm_idx': set_vm_idx,
+             'declare_varith_template': declareVArithTemplate(Name)},
+            flags)
+        header_output = VectorNonSplitDeclare.subst(iop)
+        decoder_output = VectorNonSplitConstructor.subst(iop)
+        exec_output = VectorIntNonSplitExecute.subst(iop)
+        decode_block = VectorIntNonSplitDecodeBlock.subst(iop)
+    elif inst_name == "vcos" :
+        iop = InstObjParams(name,
+            Name,
+            'VectorNonSplitInst',
+            {'code': code,
+             'vm_decl_rd': vm_decl_rd,
+             'set_vm_idx': set_vm_idx,
+             'declare_varith_template': declareVArithTemplate(Name)},
+            flags)
+        header_output = VectorNonSplitDeclare.subst(iop)
+        decoder_output = VectorNonSplitConstructor.subst(iop)
+        exec_output = VectorIntNonSplitExecute.subst(iop)
+        decode_block = VectorIntNonSplitDecodeBlock.subst(iop)
     elif inst_name == "iVpush" :
         iop = InstObjParams(name,
             Name,

src/cpu/FuncUnit.py

@@ -120,9 +120,11 @@ class OpClass(Enum):
         "CustomMatMuliVpush",
         "CustomMatMulwVpush",
         "CustomMatMulvpop",
-        "CustomMatMulvexp",
-        "CustomMatMulverf",
-        "CustomMatMulvtanh",
+        "CustomVexp",
+        "CustomVerf",
+        "CustomVtanh",
+        "CustomVsin",
+        "CustomVcos",
         "CustomVlaneIdx",
     ]
 

src/cpu/minor/execute.cc

@@ -832,11 +832,11 @@ Execute::issue(ThreadID thread_id)
                                 *inst);
                             thread.inFUMemInsts->push(fu_inst);
                         }
-						if (inst->staticInst->opClass() >= gem5::enums::CustomMatMulvexp)
+						if (inst->staticInst->opClass() >= gem5::enums::CustomVexp)
 							DPRINTF(PyTorchSim, "%s Issue at %d\n", *inst, cpu.curCycle());
-                        if (inst->staticInst->opClass() >= gem5::enums::CustomMatMulverf)
+                        if (inst->staticInst->opClass() >= gem5::enums::CustomVerf)
 							DPRINTF(PyTorchSim, "%s Issue at %d\n", *inst, cpu.curCycle());
-                        if (inst->staticInst->opClass() >= gem5::enums::CustomMatMulvtanh)
+                        if (inst->staticInst->opClass() >= gem5::enums::CustomVtanh)
 							DPRINTF(PyTorchSim, "%s Issue at %d\n", *inst, cpu.curCycle());
 
 						if (is_systolicArray) {

src/cpu/op_class.hh

@@ -137,9 +137,11 @@ static const OpClass CustomMatMulOp = enums::CustomMatMul;
 static const OpClass CustomMatMuliVpushOp = enums::CustomMatMuliVpush;
 static const OpClass CustomMatMulwVpushOp = enums::CustomMatMulwVpush;
 static const OpClass CustomMatMulvpopOp = enums::CustomMatMulvpop;
-static const OpClass CustomMatMulvexpOp = enums::CustomMatMulvexp;
-static const OpClass CustomMatMulverfOp = enums::CustomMatMulverf;
-static const OpClass CustomMatMulvtanhOp = enums::CustomMatMulvtanh;
+static const OpClass CustomVexpOp = enums::CustomVexp;
+static const OpClass CustomVerfOp = enums::CustomVerf;
+static const OpClass CustomVtanhOp = enums::CustomVtanh;
+static const OpClass CustomVsinOp = enums::CustomVsin;
+static const OpClass CustomVcosOp = enums::CustomVcos;
 static const OpClass CustomVlaneIdxOp = enums::CustomVlaneIdx;
 
 static const OpClass Num_OpClasses = enums::Num_OpClass;