offload-test-suite/test/WaveOps/WaveActiveBitXor.convergence.test at 0af815dd27fad4f3492e63ea546c6bd54794cfcc · Icohedron/offload-test-suite · GitHub

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#--- source.hlsl
StructuredBuffer<uint> In : register(t0);

RWStructuredBuffer<uint> Out1 : register(u1); // branch A
RWStructuredBuffer<uint> Out2 : register(u2); // branch B
RWStructuredBuffer<uint> Out3 : register(u3); // reconverged
RWStructuredBuffer<uint> Out4 : register(u4); // loop
RWStructuredBuffer<uint> Out5 : register(u5); // divergent loop

[numthreads(4,1,1)]
void main(uint3 TID : SV_GroupThreadID) {
    uint V = In[TID.x];

    // divergent branch
    if (TID.x < 2)
        Out1[TID.x] = WaveActiveBitXor(V);
    else
        Out2[TID.x] = WaveActiveBitXor(V);

    // reconverged wave op
    Out3[TID.x] = WaveActiveBitXor(V);

    // loop case
    uint R = V;
    for (uint i = 0; i < 2; i++)
        R = WaveActiveBitXor(R);

    Out4[TID.x] = R;

    // divergent loop: each thread iterates TID.x times
    // thread 0: 0 iters, thread 1: 1 iter, thread 2: 2 iters, thread 3: 3 iters
    uint R2 = V;
    for (uint j = 0; j < TID.x; j++)
        R2 = WaveActiveBitXor(R2);

    Out5[TID.x] = R2;
}

#--- pipeline.yaml

---
Shaders:
  - Stage: Compute
    Entry: main
    DispatchSize: [1, 1, 1]

Buffers:

  - Name: In
    Format: UInt32
    Stride: 4
    Data: [ 0x11, 0x12, 0x14, 0x18 ]
  - Name: Out1
    Format: UInt32
    Stride: 4
    FillSize: 16
  - Name: Out2
    Format: UInt32
    Stride: 4
    FillSize: 16
  - Name: Out3
    Format: UInt32
    Stride: 4
    FillSize: 16
  - Name: Out4
    Format: UInt32
    Stride: 4
    FillSize: 16
  - Name: Out5
    Format: UInt32
    Stride: 4
    FillSize: 16
  - Name: ExpectedOut1
    Format: UInt32
    Stride: 4
    Data: [ 0x3, 0x3, 0x0, 0x0 ]
  - Name: ExpectedOut2
    Format: UInt32
    Stride: 4
    Data: [ 0x0, 0x0, 0xc, 0xc ]
  - Name: ExpectedOut3
    Format: UInt32
    Stride: 4
    Data: [ 0xf, 0xf, 0xf, 0xf ]
  - Name: ExpectedOut4
    Format: UInt32
    Stride: 4
    Data: [ 0x0, 0x0, 0x0, 0x0 ]
  - Name: ExpectedOut5
    Format: UInt32
    Stride: 4
    Data: [ 0x11, 0x1e, 0x0, 0x0 ]

Results:
  - Result: ExpectedOut1
    Rule: BufferExact
    Actual: Out1
    Expected: ExpectedOut1
  - Result: ExpectedOut2
    Rule: BufferExact
    Actual: Out2
    Expected: ExpectedOut2
  - Result: ExpectedOut3
    Rule: BufferExact
    Actual: Out3
    Expected: ExpectedOut3
  - Result: ExpectedOut4
    Rule: BufferExact
    Actual: Out4
    Expected: ExpectedOut4
  - Result: ExpectedOut5
    Rule: BufferExact
    Actual: Out5
    Expected: ExpectedOut5


DescriptorSets:
  - Resources:
    - Name: In
      Kind: StructuredBuffer
      DirectXBinding:
        Register: 0
        Space: 0
      VulkanBinding:
        Binding: 0
    - Name: Out1
      Kind: RWStructuredBuffer
      DirectXBinding:
        Register: 1
        Space: 0
      VulkanBinding:
        Binding: 1
    - Name: Out2
      Kind: RWStructuredBuffer
      DirectXBinding:
        Register: 2
        Space: 0
      VulkanBinding:
        Binding: 2
    - Name: Out3
      Kind: RWStructuredBuffer
      DirectXBinding:
        Register: 3
        Space: 0
      VulkanBinding:
        Binding: 3
    - Name: Out4
      Kind: RWStructuredBuffer
      DirectXBinding:
        Register: 4
        Space: 0
      VulkanBinding:
        Binding: 4
    - Name: Out5
      Kind: RWStructuredBuffer
      DirectXBinding:
        Register: 5
        Space: 0
      VulkanBinding:
        Binding: 5
...
#--- end

# Bug: https://github.com/llvm/llvm-project/issues/188323
# XFAIL: Vulkan && Clang

# RUN: split-file %s %t
# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl
# RUN: %offloader %t/pipeline.yaml %t.o