udc: aspeed: manage TX/RX DMA buffer cache coherency explicitly

RX buffers used NON_CACHED_BSS_ALIGN16 to avoid cache coherency
issues, but that non-cached memory region isn't available here
anymore. Switch to plain aligned buffers and manage coherency with
sys_cache_data_flush_range() before TX DMA and
sys_cache_data_invd_range() before reading RX data, in both the
legacy and next USB device stacks.

Signed-off-by: Joe Wang <[email protected]>
Change-Id: I09730e12b0a41e9bfa8cef45383ca669989e73e2

Author: joe-aspeed

drivers/usb/device/usb_dc_aspeed.c

@@ -195,7 +195,7 @@ struct usb_device_ep_data {
 	usb_dc_ep_callback cb_out;
 };
 
-uint8_t rx_dma[AST_UDC_MAX_NUM_EP][RX_DMA_BUFF_SIZE] NON_CACHED_BSS_ALIGN16;
+uint8_t rx_dma[AST_UDC_MAX_NUM_EP][RX_DMA_BUFF_SIZE] __aligned(16);
 /*
  * Endpoint mapping table:
  * Each bidirectional endpoint address (e.g., 0x00, 0x80, 0x01, 0x81, 0x02, 0x82, ...)
@@ -1328,6 +1328,7 @@ int usb_dc_ep_write(const uint8_t ep, const uint8_t *const data,
 		LOG_DBG("trigger ep0 tx len: [%d/%d]", tx_len, data_len);
 		dev_data.ep_data[0].tx_last = tx_len;
 
+		sys_cache_data_flush_range(dev_data.ep_data[0].tx_dma, tx_len);
 		sys_write32(TO_PHY_ADDR((uintptr_t)dev_data.ep_data[0].tx_dma),
 			    dev_data.base + ASPEED_USB_EP0_DATA_BUFF);
 		aspeed_udc_ep0_tx(tx_len);
@@ -1349,6 +1350,7 @@ int usb_dc_ep_write(const uint8_t ep, const uint8_t *const data,
 		if (ret_bytes)
 			*ret_bytes = tx_len;
 
+		sys_cache_data_flush_range((void *)data, tx_len);
 		sys_write32(TO_PHY_ADDR((uintptr_t)data), ep_reg + ASPEED_EP_DMA_BUFF);
 		sys_write32(EP_TX_LEN(tx_len), ep_reg + ASPEED_EP_DMA_STS);
 		sys_write32(EP_TX_LEN(tx_len) | 0x1,
@@ -1517,6 +1519,7 @@ int usb_dc_ep_read_wait(uint8_t ep, uint8_t *data, uint32_t max_data_len,
 			LOG_DBG("Copy data from rx_dma, %s:0x%x",
 				"data_len", data_len);
 
+			sys_cache_data_invd_range(dev_data.ep_data[0].rx_dma, data_len);
 			memcpy(data, dev_data.ep_data[0].rx_dma, data_len);
 			*read_bytes = data_len;
 
@@ -1539,6 +1542,8 @@ int usb_dc_ep_read_wait(uint8_t ep, uint8_t *data, uint32_t max_data_len,
 		}
 
 		if (byte_to_copy <= RX_DMA_BUFF_SIZE) {
+			sys_cache_data_invd_range(dev_data.ep_data[ep_num].rx_dma,
+				byte_to_copy);
 			memcpy(data, dev_data.ep_data[ep_num].rx_dma,
 				byte_to_copy);
 		} else {

drivers/usb/udc/udc_aspeed.c

@@ -251,6 +251,8 @@ static int aspeed_udc_start_in(const struct device *dev,
 	tx_len = MIN(buf->len, ep_data->mps);
 	ep_data->tx_last = tx_len;
 
+	sys_cache_data_flush_range(buf->data, tx_len);
+
 	if (ep_data->hw_ep == 0) {
 		sys_write32(TO_PHY_ADDR((uintptr_t)buf->data),
 			    aspeed_udc_base(dev) + ASPEED_USB_EP0_DATA_BUFF);
@@ -471,6 +473,7 @@ static int aspeed_udc_handle_out(const struct device *dev, uint8_t ep)
 	}
 
 	if (data_len != 0) {
+		sys_cache_data_invd_range(ep_data->rx_dma, data_len);
 		net_buf_add_mem(buf, ep_data->rx_dma, data_len);
 	}
 
@@ -1078,7 +1081,7 @@ static int aspeed_udc_preinit(const struct device *dev)
 	ASPEED_UDC_PINCTRL_DT_INST_DEFINE(n);				       \
 	static uint8_t aspeed_udc_rx_dma_##n			       \
 		[DT_INST_PROP(n, num_bidir_endpoints)][RX_DMA_BUFF_SIZE]       \
-		NON_CACHED_BSS_ALIGN16;					       \
+		__aligned(16);						       \
 	static struct aspeed_udc_ep_data aspeed_udc_ep_data_##n		       \
 		[DT_INST_PROP(n, num_bidir_endpoints)];			       \
 	static uint8_t aspeed_udc_ep_map_##n[32];			       \