diff --git a/neon_intrinsics/advsimd.md b/neon_intrinsics/advsimd.md
index 05bdec33..7af69ba7 100644
--- a/neon_intrinsics/advsimd.md
+++ b/neon_intrinsics/advsimd.md
@@ -129,6 +129,7 @@ for more information about Arm’s trademarks.
 | M     | 21 February 2025  | 2024Q4               |
 | N     | 06 June 2025      | 2025Q2               |
 | O     | 15 May 2026       | 2026Q1               |
+| P     | 07 July 2026      | 2026Q2               |
 
 ### Changes between 2021Q2 and 2021Q3
 
@@ -174,6 +175,7 @@ for more information about Arm’s trademarks.
 
 * Added support for FEAT_F16F32DOT
 * Added support for FEAT_F16F32MM and FEAT_F16MM
+* Added documentation for missing Neon intrinsics
 
 <!---
 **** Do not remove! ****
@@ -1591,6 +1593,8 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``.
 | <code>uint32x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u32" target="_blank">vtstq_u32</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; uint32x4_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; uint32x4_t b)</code> | `a -> Vn.4S`<br>`b -> Vm.4S`   | `CMTST Vd.4S,Vn.4S,Vm.4S`    | `Vd.4S -> result`  | `v7/A32/A64`              |
 | <code>uint8x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p8" target="_blank">vtst_p8</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; poly8x8_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; poly8x8_t b)</code>        | `a -> Vn.8B`<br>`b -> Vm.8B`   | `CMTST Vd.8B,Vn.8B,Vm.8B`    | `Vd.8B -> result`  | `v7/A32/A64`              |
 | <code>uint8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p8" target="_blank">vtstq_p8</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; poly8x16_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; poly8x16_t b)</code>   | `a -> Vn.16B`<br>`b -> Vm.16B` | `CMTST Vd.16B,Vn.16B,Vm.16B` | `Vd.16B -> result` | `v7/A32/A64`              |
+| <code>uint16x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p16" target="_blank">vtst_p16</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; poly16x4_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; poly16x4_t b)</code>   | `a -> Vn.4H`<br>`b -> Vm.4H`   | `CMTST Vd.4H,Vn.4H,Vm.4H`    | `Vd.4H -> result`  | `v7/A32/A64`              |
+| <code>uint16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p16" target="_blank">vtstq_p16</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; poly16x8_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; poly16x8_t b)</code> | `a -> Vn.8H`<br>`b -> Vm.8H`   | `CMTST Vd.8H,Vn.8H,Vm.8H`    | `Vd.8H -> result`  | `v7/A32/A64`              |
 | <code>uint64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s64" target="_blank">vtst_s64</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; int64x1_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; int64x1_t b)</code>     | `a -> Dn`<br>`b -> Dm`         | `CMTST Dd,Dn,Dm`             | `Dd -> result`     | `A64`                     |
 | <code>uint64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s64" target="_blank">vtstq_s64</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; int64x2_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; int64x2_t b)</code>   | `a -> Vn.2D`<br>`b -> Vm.2D`   | `CMTST Vd.2D,Vn.2D,Vm.2D`    | `Vd.2D -> result`  | `A64`                     |
 | <code>uint64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u64" target="_blank">vtst_u64</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; uint64x1_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; uint64x1_t b)</code>   | `a -> Dn`<br>`b -> Dm`         | `CMTST Dd,Dn,Dm`             | `Dd -> result`     | `A64`                     |
@@ -2286,6 +2290,7 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``.
 | <code>uint16x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8" target="_blank">vreinterpret_u16_p8</a>(poly8x8_t a)</code>         | `a -> Vd.8B`           | `NOP`                 | `Vd.4H -> result`  | `v7/A32/A64`              |
 | <code>uint32x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8" target="_blank">vreinterpret_u32_p8</a>(poly8x8_t a)</code>         | `a -> Vd.8B`           | `NOP`                 | `Vd.2S -> result`  | `v7/A32/A64`              |
 | <code>poly16x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8" target="_blank">vreinterpret_p16_p8</a>(poly8x8_t a)</code>         | `a -> Vd.8B`           | `NOP`                 | `Vd.4H -> result`  | `v7/A32/A64`              |
+| <code>mfloat8x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_mf8_p8" target="_blank">vreinterpret_mf8_p8</a>(poly8x8_t a)</code>        | `a -> Vd.8B`           | `NOP`                 | `Vd.8B -> result`  | `A64`                     |
 | <code>uint64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8" target="_blank">vreinterpret_u64_p8</a>(poly8x8_t a)</code>         | `a -> Vd.8B`           | `NOP`                 | `Vd.1D -> result`  | `v7/A32/A64`              |
 | <code>int64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8" target="_blank">vreinterpret_s64_p8</a>(poly8x8_t a)</code>          | `a -> Vd.8B`           | `NOP`                 | `Vd.1D -> result`  | `v7/A32/A64`              |
 | <code>float64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p8" target="_blank">vreinterpret_f64_p8</a>(poly8x8_t a)</code>        | `a -> Vd.8B`           | `NOP`                 | `Vd.1D -> result`  | `A64`                     |
@@ -2298,6 +2303,7 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``.
 | <code>uint8x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_mf8" target="_blank">vreinterpret_u8_mf8</a>(mfloat8x8_t a)</code>        | `a -> Vd.8B`           | `NOP`                 | `Vd.8B -> result`  | `A64`                     |
 | <code>uint16x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_mf8" target="_blank">vreinterpret_u16_mf8</a>(mfloat8x8_t a)</code>     | `a -> Vd.8B`           | `NOP`                 | `Vd.4H -> result`  | `A64`                     |
 | <code>uint32x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_mf8" target="_blank">vreinterpret_u32_mf8</a>(mfloat8x8_t a)</code>     | `a -> Vd.8B`           | `NOP`                 | `Vd.2S -> result`  | `A64`                     |
+| <code>poly8x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_mf8" target="_blank">vreinterpret_p8_mf8</a>(mfloat8x8_t a)</code>        | `a -> Vd.8B`           | `NOP`                 | `Vd.8B -> result`  | `A64`                     |
 | <code>poly16x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_mf8" target="_blank">vreinterpret_p16_mf8</a>(mfloat8x8_t a)</code>     | `a -> Vd.8B`           | `NOP`                 | `Vd.4H -> result`  | `A64`                     |
 | <code>uint64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_mf8" target="_blank">vreinterpret_u64_mf8</a>(mfloat8x8_t a)</code>     | `a -> Vd.8B`           | `NOP`                 | `Vd.1D -> result`  | `A64`                     |
 | <code>int64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_mf8" target="_blank">vreinterpret_s64_mf8</a>(mfloat8x8_t a)</code>      | `a -> Vd.8B`           | `NOP`                 | `Vd.1D -> result`  | `A64`                     |
@@ -2344,6 +2350,7 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``.
 | <code>mfloat8x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_mf8_s64" target="_blank">vreinterpret_mf8_s64</a>(int64x1_t a)</code>      | `a -> Vd.1D`           | `NOP`                 | `Vd.8B -> result`  | `A64`                     |
 | <code>uint64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s64" target="_blank">vreinterpret_u64_s64</a>(int64x1_t a)</code>       | `a -> Vd.1D`           | `NOP`                 | `Vd.1D -> result`  | `v7/A32/A64`              |
 | <code>float64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s64" target="_blank">vreinterpret_f64_s64</a>(int64x1_t a)</code>      | `a -> Vd.1D`           | `NOP`                 | `Vd.1D -> result`  | `A64`                     |
+| <code>poly64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s64" target="_blank">vreinterpret_p64_s64</a>(int64x1_t a)</code>       | `a -> Vd.1D`           | `NOP`                 | `Vd.1D -> result`  | `A32/A64`                 |
 | <code>uint64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p64" target="_blank">vreinterpret_u64_p64</a>(poly64x1_t a)</code>      | `a -> Vd.1D`           | `NOP`                 | `Vd.1D -> result`  | `A32/A64`                 |
 | <code>float16x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64" target="_blank">vreinterpret_f16_s64</a>(int64x1_t a)</code>      | `a -> Vd.1D`           | `NOP`                 | `Vd.4H -> result`  | `v7/A32/A64`              |
 | <code>int8x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16" target="_blank">vreinterpret_s8_f16</a>(float16x4_t a)</code>         | `a -> Vd.4H`           | `NOP`                 | `Vd.8B -> result`  | `v7/A32/A64`              |
@@ -2475,6 +2482,7 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``.
 | <code>uint16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8" target="_blank">vreinterpretq_u16_p8</a>(poly8x16_t a)</code>      | `a -> Vd.16B`          | `NOP`                 | `Vd.8H -> result`  | `v7/A32/A64`              |
 | <code>uint32x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8" target="_blank">vreinterpretq_u32_p8</a>(poly8x16_t a)</code>      | `a -> Vd.16B`          | `NOP`                 | `Vd.4S -> result`  | `v7/A32/A64`              |
 | <code>poly16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8" target="_blank">vreinterpretq_p16_p8</a>(poly8x16_t a)</code>      | `a -> Vd.16B`          | `NOP`                 | `Vd.8H -> result`  | `v7/A32/A64`              |
+| <code>mfloat8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_mf8_p8" target="_blank">vreinterpretq_mf8_p8</a>(poly8x16_t a)</code>    | `a -> Vd.16B`          | `NOP`                 | `Vd.16B -> result` | `A64`                     |
 | <code>uint64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8" target="_blank">vreinterpretq_u64_p8</a>(poly8x16_t a)</code>      | `a -> Vd.16B`          | `NOP`                 | `Vd.2D -> result`  | `v7/A32/A64`              |
 | <code>int64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8" target="_blank">vreinterpretq_s64_p8</a>(poly8x16_t a)</code>       | `a -> Vd.16B`          | `NOP`                 | `Vd.2D -> result`  | `v7/A32/A64`              |
 | <code>float64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p8" target="_blank">vreinterpretq_f64_p8</a>(poly8x16_t a)</code>     | `a -> Vd.16B`          | `NOP`                 | `Vd.2D -> result`  | `A64`                     |
@@ -2488,6 +2496,7 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``.
 | <code>uint8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_mf8" target="_blank">vreinterpretq_u8_mf8</a>(mfloat8x16_t a)</code>    | `a -> Vd.16B`          | `NOP`                 | `Vd.16B -> result` | `A64`                     |
 | <code>uint16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_mf8" target="_blank">vreinterpretq_u16_mf8</a>(mfloat8x16_t a)</code>  | `a -> Vd.16B`          | `NOP`                 | `Vd.8H -> result`  | `A64`                     |
 | <code>uint32x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_mf8" target="_blank">vreinterpretq_u32_mf8</a>(mfloat8x16_t a)</code>  | `a -> Vd.16B`          | `NOP`                 | `Vd.4S -> result`  | `A64`                     |
+| <code>poly8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_mf8" target="_blank">vreinterpretq_p8_mf8</a>(mfloat8x16_t a)</code>    | `a -> Vd.16B`          | `NOP`                 | `Vd.16B -> result` | `A64`                     |
 | <code>poly16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_mf8" target="_blank">vreinterpretq_p16_mf8</a>(mfloat8x16_t a)</code>  | `a -> Vd.16B`          | `NOP`                 | `Vd.8H -> result`  | `A64`                     |
 | <code>uint64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_mf8" target="_blank">vreinterpretq_u64_mf8</a>(mfloat8x16_t a)</code>  | `a -> Vd.16B`          | `NOP`                 | `Vd.2D -> result`  | `A64`                     |
 | <code>int64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_mf8" target="_blank">vreinterpretq_s64_mf8</a>(mfloat8x16_t a)</code>   | `a -> Vd.16B`          | `NOP`                 | `Vd.2D -> result`  | `A64`                     |
@@ -2585,6 +2594,7 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``.
 | <code>int8x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64" target="_blank">vreinterpret_s8_p64</a>(poly64x1_t a)</code>          | `a -> Vd.1D`           | `NOP`                 | `Vd.8B -> result`  | `A32/A64`                 |
 | <code>int16x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64" target="_blank">vreinterpret_s16_p64</a>(poly64x1_t a)</code>       | `a -> Vd.1D`           | `NOP`                 | `Vd.4H -> result`  | `A32/A64`                 |
 | <code>int32x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64" target="_blank">vreinterpret_s32_p64</a>(poly64x1_t a)</code>       | `a -> Vd.1D`           | `NOP`                 | `Vd.2S -> result`  | `A32/A64`                 |
+| <code>float32x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p64" target="_blank">vreinterpret_f32_p64</a>(poly64x1_t a)</code>     | `a -> Vd.1D`           | `NOP`                 | `Vd.2S -> result`  | `A32/A64`                 |
 | <code>uint8x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64" target="_blank">vreinterpret_u8_p64</a>(poly64x1_t a)</code>         | `a -> Vd.1D`           | `NOP`                 | `Vd.8B -> result`  | `A32/A64`                 |
 | <code>uint16x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64" target="_blank">vreinterpret_u16_p64</a>(poly64x1_t a)</code>      | `a -> Vd.1D`           | `NOP`                 | `Vd.4H -> result`  | `A32/A64`                 |
 | <code>uint32x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64" target="_blank">vreinterpret_u32_p64</a>(poly64x1_t a)</code>      | `a -> Vd.1D`           | `NOP`                 | `Vd.2S -> result`  | `A32/A64`                 |
@@ -2597,6 +2607,7 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``.
 | <code>int8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64" target="_blank">vreinterpretq_s8_p64</a>(poly64x2_t a)</code>       | `a -> Vd.2D`           | `NOP`                 | `Vd.16B -> result` | `A32/A64`                 |
 | <code>int16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64" target="_blank">vreinterpretq_s16_p64</a>(poly64x2_t a)</code>     | `a -> Vd.2D`           | `NOP`                 | `Vd.8H -> result`  | `A32/A64`                 |
 | <code>int32x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64" target="_blank">vreinterpretq_s32_p64</a>(poly64x2_t a)</code>     | `a -> Vd.2D`           | `NOP`                 | `Vd.4S -> result`  | `A32/A64`                 |
+| <code>float32x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p64" target="_blank">vreinterpretq_f32_p64</a>(poly64x2_t a)</code>   | `a -> Vd.2D`           | `NOP`                 | `Vd.4S -> result`  | `A32/A64`                 |
 | <code>uint8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64" target="_blank">vreinterpretq_u8_p64</a>(poly64x2_t a)</code>      | `a -> Vd.2D`           | `NOP`                 | `Vd.16B -> result` | `A32/A64`                 |
 | <code>uint16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64" target="_blank">vreinterpretq_u16_p64</a>(poly64x2_t a)</code>    | `a -> Vd.2D`           | `NOP`                 | `Vd.8H -> result`  | `A32/A64`                 |
 | <code>uint32x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64" target="_blank">vreinterpretq_u32_p64</a>(poly64x2_t a)</code>    | `a -> Vd.2D`           | `NOP`                 | `Vd.4S -> result`  | `A32/A64`                 |
@@ -2605,10 +2616,12 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``.
 | <code>mfloat8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_mf8_p64" target="_blank">vreinterpretq_mf8_p64</a>(poly64x2_t a)</code>  | `a -> Vd.2D`           | `NOP`                 | `Vd.16B -> result` | `A64`                     |
 | <code>int64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p64" target="_blank">vreinterpretq_s64_p64</a>(poly64x2_t a)</code>     | `a -> Vd.2D`           | `NOP`                 | `Vd.2D -> result`  | `A32/A64`                 |
 | <code>float64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p64" target="_blank">vreinterpretq_f64_p64</a>(poly64x2_t a)</code>   | `a -> Vd.2D`           | `NOP`                 | `Vd.2D -> result`  | `A64`                     |
+| <code>poly128_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64" target="_blank">vreinterpretq_p128_p64</a>(poly64x2_t a)</code>   | `a -> Vd.2D`           | `NOP`                 | `Vd.1Q -> result`  | `A32/A64`                 |
 | <code>float16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64" target="_blank">vreinterpretq_f16_p64</a>(poly64x2_t a)</code>   | `a -> Vd.2D`           | `NOP`                 | `Vd.8H -> result`  | `A32/A64`                 |
 | <code>int8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128" target="_blank">vreinterpretq_s8_p128</a>(poly128_t a)</code>      | `a -> Vd.1Q`           | `NOP`                 | `Vd.16B -> result` | `A32/A64`                 |
 | <code>int16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128" target="_blank">vreinterpretq_s16_p128</a>(poly128_t a)</code>    | `a -> Vd.1Q`           | `NOP`                 | `Vd.8H -> result`  | `A32/A64`                 |
 | <code>int32x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128" target="_blank">vreinterpretq_s32_p128</a>(poly128_t a)</code>    | `a -> Vd.1Q`           | `NOP`                 | `Vd.4S -> result`  | `A32/A64`                 |
+| <code>float32x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128" target="_blank">vreinterpretq_f32_p128</a>(poly128_t a)</code>  | `a -> Vd.1Q`           | `NOP`                 | `Vd.4S -> result`  | `A32/A64`                 |
 | <code>uint8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128" target="_blank">vreinterpretq_u8_p128</a>(poly128_t a)</code>     | `a -> Vd.1Q`           | `NOP`                 | `Vd.16B -> result` | `A32/A64`                 |
 | <code>uint16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128" target="_blank">vreinterpretq_u16_p128</a>(poly128_t a)</code>   | `a -> Vd.1Q`           | `NOP`                 | `Vd.8H -> result`  | `A32/A64`                 |
 | <code>uint32x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128" target="_blank">vreinterpretq_u32_p128</a>(poly128_t a)</code>   | `a -> Vd.1Q`           | `NOP`                 | `Vd.4S -> result`  | `A32/A64`                 |
@@ -2618,6 +2631,7 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``.
 | <code>uint64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128" target="_blank">vreinterpretq_u64_p128</a>(poly128_t a)</code>   | `a -> Vd.1Q`           | `NOP`                 | `Vd.2D -> result`  | `A32/A64`                 |
 | <code>int64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128" target="_blank">vreinterpretq_s64_p128</a>(poly128_t a)</code>    | `a -> Vd.1Q`           | `NOP`                 | `Vd.2D -> result`  | `A32/A64`                 |
 | <code>float64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p128" target="_blank">vreinterpretq_f64_p128</a>(poly128_t a)</code>  | `a -> Vd.1Q`           | `NOP`                 | `Vd.2D -> result`  | `A64`                     |
+| <code>poly64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128" target="_blank">vreinterpretq_p64_p128</a>(poly128_t a)</code>   | `a -> Vd.1Q`           | `NOP`                 | `Vd.2D -> result`  | `A32/A64`                 |
 | <code>float16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128" target="_blank">vreinterpretq_f16_p128</a>(poly128_t a)</code>  | `a -> Vd.1Q`           | `NOP`                 | `Vd.8H -> result`  | `A32/A64`                 |
 | <code>mfloat8x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_mf8_u8" target="_blank">vreinterpret_mf8_u8</a>(uint8x8_t a)</code>        | `a -> Vd.8B`           | `NOP`                 | `Vd.8B -> result`  | `A64`                     |
 | <code>mfloat8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_mf8_u8" target="_blank">vreinterpretq_mf8_u8</a>(uint8x16_t a)</code>    | `a -> Vd.16B`          | `NOP`                 | `Vd.16B -> result` | `A64`                     |
@@ -3293,6 +3307,8 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``.
 | <code>poly8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_p8" target="_blank">vmovq_n_p8</a>(poly8_t value)</code>                                                                                         | `value -> rn`                        | `DUP Vd.16B,rn`         | `Vd.16B -> result` | `v7/A32/A64`              |
 | <code>poly16x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_p16" target="_blank">vmov_n_p16</a>(poly16_t value)</code>                                                                                        | `value -> rn`                        | `DUP Vd.4H,rn`          | `Vd.4H -> result`  | `v7/A32/A64`              |
 | <code>poly16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_p16" target="_blank">vmovq_n_p16</a>(poly16_t value)</code>                                                                                      | `value -> rn`                        | `DUP Vd.8H,rn`          | `Vd.8H -> result`  | `v7/A32/A64`              |
+| <code>poly64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_p64" target="_blank">vmov_n_p64</a>(poly64_t value)</code>                                                                                        | `value -> rn`                        | `INS Dd.D[0],xn`        | `Vd.1D -> result`  | `A32/A64`                 |
+| <code>poly64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_p64" target="_blank">vmovq_n_p64</a>(poly64_t value)</code>                                                                                      | `value -> rn`                        | `DUP Vd.2D,rn`          | `Vd.2D -> result`  | `A32/A64`                 |
 | <code>float64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_f64" target="_blank">vmov_n_f64</a>(float64_t value)</code>                                                                                      | `value -> rn`                        | `DUP Vd.1D,rn`          | `Vd.1D -> result`  | `A64`                     |
 | <code>float64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_f64" target="_blank">vmovq_n_f64</a>(float64_t value)</code>                                                                                    | `value -> rn`                        | `DUP Vd.2D,rn`          | `Vd.2D -> result`  | `A64`                     |
 | <code>mfloat8x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_mf8" target="_blank">vmov_n_mf8</a>(mfloat8_t value)</code>                                                                                      | `value -> rn`                        | `DUP Vd.8B,rn`          | `Vd.8B -> result`  | `A64`                     |
@@ -6022,6 +6038,7 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``.
 | <code>bfloat16x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_bf16_s8" target="_blank">vreinterpret_bf16_s8</a>(int8x8_t a)</code>         | `a -> Vd.8B`           | `NOP`                 | `Vd.4H -> result`  | `A32/A64`                 |
 | <code>bfloat16x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_bf16_s16" target="_blank">vreinterpret_bf16_s16</a>(int16x4_t a)</code>      | `a -> Vd.4H`           | `NOP`                 | `Vd.4H -> result`  | `A32/A64`                 |
 | <code>bfloat16x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_bf16_s32" target="_blank">vreinterpret_bf16_s32</a>(int32x2_t a)</code>      | `a -> Vd.2S`           | `NOP`                 | `Vd.4H -> result`  | `A32/A64`                 |
+| <code>bfloat16x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_bf16_f16" target="_blank">vreinterpret_bf16_f16</a>(float16x4_t a)</code>    | `a -> Vd.4H`           | `NOP`                 | `Vd.4H -> result`  | `A32/A64`                 |
 | <code>bfloat16x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_bf16_f32" target="_blank">vreinterpret_bf16_f32</a>(float32x2_t a)</code>    | `a -> Vd.2S`           | `NOP`                 | `Vd.4H -> result`  | `A32/A64`                 |
 | <code>bfloat16x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_bf16_u8" target="_blank">vreinterpret_bf16_u8</a>(uint8x8_t a)</code>        | `a -> Vd.8B`           | `NOP`                 | `Vd.4H -> result`  | `A32/A64`                 |
 | <code>bfloat16x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_bf16_u16" target="_blank">vreinterpret_bf16_u16</a>(uint16x4_t a)</code>     | `a -> Vd.4H`           | `NOP`                 | `Vd.4H -> result`  | `A32/A64`                 |
@@ -6034,6 +6051,7 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``.
 | <code>bfloat16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_bf16_s8" target="_blank">vreinterpretq_bf16_s8</a>(int8x16_t a)</code>      | `a -> Vd.16B`          | `NOP`                 | `Vd.8H -> result`  | `A32/A64`                 |
 | <code>bfloat16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_bf16_s16" target="_blank">vreinterpretq_bf16_s16</a>(int16x8_t a)</code>    | `a -> Vd.8H`           | `NOP`                 | `Vd.8H -> result`  | `A32/A64`                 |
 | <code>bfloat16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_bf16_s32" target="_blank">vreinterpretq_bf16_s32</a>(int32x4_t a)</code>    | `a -> Vd.4S`           | `NOP`                 | `Vd.8H -> result`  | `A32/A64`                 |
+| <code>bfloat16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_bf16_f16" target="_blank">vreinterpretq_bf16_f16</a>(float16x8_t a)</code>  | `a -> Vd.8H`           | `NOP`                 | `Vd.8H -> result`  | `A32/A64`                 |
 | <code>bfloat16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_bf16_f32" target="_blank">vreinterpretq_bf16_f32</a>(float32x4_t a)</code>  | `a -> Vd.4S`           | `NOP`                 | `Vd.8H -> result`  | `A32/A64`                 |
 | <code>bfloat16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_bf16_u8" target="_blank">vreinterpretq_bf16_u8</a>(uint8x16_t a)</code>     | `a -> Vd.16B`          | `NOP`                 | `Vd.8H -> result`  | `A32/A64`                 |
 | <code>bfloat16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_bf16_u16" target="_blank">vreinterpretq_bf16_u16</a>(uint16x8_t a)</code>   | `a -> Vd.8H`           | `NOP`                 | `Vd.8H -> result`  | `A32/A64`                 |
@@ -6051,6 +6069,7 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``.
 | <code>int8x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_bf16" target="_blank">vreinterpret_s8_bf16</a>(bfloat16x4_t a)</code>         | `a -> Vd.4H`           | `NOP`                 | `Vd.8B -> result`  | `A32/A64`                 |
 | <code>int16x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_bf16" target="_blank">vreinterpret_s16_bf16</a>(bfloat16x4_t a)</code>      | `a -> Vd.4H`           | `NOP`                 | `Vd.4H -> result`  | `A32/A64`                 |
 | <code>int32x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_bf16" target="_blank">vreinterpret_s32_bf16</a>(bfloat16x4_t a)</code>      | `a -> Vd.4H`           | `NOP`                 | `Vd.2S -> result`  | `A32/A64`                 |
+| <code>float16x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_bf16" target="_blank">vreinterpret_f16_bf16</a>(bfloat16x4_t a)</code>    | `a -> Vd.4H`           | `NOP`                 | `Vd.4H -> result`  | `A32/A64`                 |
 | <code>float32x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_bf16" target="_blank">vreinterpret_f32_bf16</a>(bfloat16x4_t a)</code>    | `a -> Vd.4H`           | `NOP`                 | `Vd.2S -> result`  | `A32/A64`                 |
 | <code>uint8x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_bf16" target="_blank">vreinterpret_u8_bf16</a>(bfloat16x4_t a)</code>        | `a -> Vd.4H`           | `NOP`                 | `Vd.8B -> result`  | `A32/A64`                 |
 | <code>uint16x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_bf16" target="_blank">vreinterpret_u16_bf16</a>(bfloat16x4_t a)</code>     | `a -> Vd.4H`           | `NOP`                 | `Vd.4H -> result`  | `A32/A64`                 |
@@ -6077,6 +6096,7 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``.
 | <code>float64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_bf16" target="_blank">vreinterpretq_f64_bf16</a>(bfloat16x8_t a)</code>  | `a -> Vd.8H`           | `NOP`                 | `Vd.2D -> result`  | `A64`                     |
 | <code>poly64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_bf16" target="_blank">vreinterpretq_p64_bf16</a>(bfloat16x8_t a)</code>   | `a -> Vd.8H`           | `NOP`                 | `Vd.2D -> result`  | `A32/A64`                 |
 | <code>poly128_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_bf16" target="_blank">vreinterpretq_p128_bf16</a>(bfloat16x8_t a)</code>  | `a -> Vd.8H`           | `NOP`                 | `Vd.1Q -> result`  | `A32/A64`                 |
+| <code>float16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_bf16" target="_blank">vreinterpretq_f16_bf16</a>(bfloat16x8_t a)</code>  | `a -> Vd.8H`           | `NOP`                 | `Vd.8H -> result`  | `A32/A64`                 |
 
 #### Conversions
 
diff --git a/neon_intrinsics/advsimd.template.md b/neon_intrinsics/advsimd.template.md
index 25c61dc8..b700428f 100644
--- a/neon_intrinsics/advsimd.template.md
+++ b/neon_intrinsics/advsimd.template.md
@@ -129,6 +129,7 @@ for more information about Arm’s trademarks.
 | M     | 21 February 2025  | 2024Q4               |
 | N     | 06 June 2025      | 2025Q2               |
 | O     | 15 May 2026       | 2026Q1               |
+| P     | 07 July 2026      | 2026Q2               |
 
 ### Changes between 2021Q2 and 2021Q3
 
@@ -174,6 +175,7 @@ for more information about Arm’s trademarks.
 
 * Added support for FEAT_F16F32DOT
 * Added support for FEAT_F16F32MM and FEAT_F16MM
+* Added documentation for missing Neon intrinsics
 
 <!---
 **** Do not remove! ****
diff --git a/tools/intrinsic_db/advsimd.csv b/tools/intrinsic_db/advsimd.csv
index 6de70af8..a8902671 100644
--- a/tools/intrinsic_db/advsimd.csv
+++ b/tools/intrinsic_db/advsimd.csv
@@ -685,6 +685,8 @@ uint32x2_t vtst_u32(uint32x2_t a, uint32x2_t b)	a -> Vn.2S;b -> Vm.2S	CMTST Vd.2
 uint32x4_t vtstq_u32(uint32x4_t a, uint32x4_t b)	a -> Vn.4S;b -> Vm.4S	CMTST Vd.4S,Vn.4S,Vm.4S	Vd.4S -> result	v7/A32/A64
 uint8x8_t vtst_p8(poly8x8_t a, poly8x8_t b)	a -> Vn.8B;b -> Vm.8B	CMTST Vd.8B,Vn.8B,Vm.8B	Vd.8B -> result	v7/A32/A64
 uint8x16_t vtstq_p8(poly8x16_t a, poly8x16_t b)	a -> Vn.16B;b -> Vm.16B	CMTST Vd.16B,Vn.16B,Vm.16B	Vd.16B -> result	v7/A32/A64
+uint16x4_t vtst_p16(poly16x4_t a, poly16x4_t b)	a -> Vn.4H;b -> Vm.4H	CMTST Vd.4H,Vn.4H,Vm.4H	Vd.4H -> result	v7/A32/A64
+uint16x8_t vtstq_p16(poly16x8_t a, poly16x8_t b)	a -> Vn.8H;b -> Vm.8H	CMTST Vd.8H,Vn.8H,Vm.8H	Vd.8H -> result	v7/A32/A64
 uint64x1_t vtst_s64(int64x1_t a, int64x1_t b)	a -> Dn;b -> Dm	CMTST Dd,Dn,Dm	Dd -> result	A64
 uint64x2_t vtstq_s64(int64x2_t a, int64x2_t b)	a -> Vn.2D;b -> Vm.2D	CMTST Vd.2D,Vn.2D,Vm.2D	Vd.2D -> result	A64
 uint64x1_t vtst_u64(uint64x1_t a, uint64x1_t b)	a -> Dn;b -> Dm	CMTST Dd,Dn,Dm	Dd -> result	A64
@@ -1967,6 +1969,8 @@ poly8x8_t vmov_n_p8(poly8_t value)	value -> rn	DUP Vd.8B,rn	Vd.8B -> result	v7/A
 poly8x16_t vmovq_n_p8(poly8_t value)	value -> rn	DUP Vd.16B,rn	Vd.16B -> result	v7/A32/A64
 poly16x4_t vmov_n_p16(poly16_t value)	value -> rn	DUP Vd.4H,rn	Vd.4H -> result	v7/A32/A64
 poly16x8_t vmovq_n_p16(poly16_t value)	value -> rn	DUP Vd.8H,rn	Vd.8H -> result	v7/A32/A64
+poly64x1_t vmov_n_p64(poly64_t value)	value -> rn	INS Dd.D[0],xn	Vd.1D -> result	A32/A64
+poly64x2_t vmovq_n_p64(poly64_t value)	value -> rn	DUP Vd.2D,rn	Vd.2D -> result	A32/A64
 float64x1_t vmov_n_f64(float64_t value)	value -> rn	DUP Vd.1D,rn	Vd.1D -> result	A64
 float64x2_t vmovq_n_f64(float64_t value)	value -> rn	DUP Vd.2D,rn	Vd.2D -> result	A64
 mfloat8x8_t vmov_n_mf8(mfloat8_t value)	value -> rn	DUP Vd.8B,rn	Vd.8B -> result	A64
@@ -3595,6 +3599,7 @@ uint8x8_t vreinterpret_u8_p8(poly8x8_t a)	a -> Vd.8B	NOP	Vd.8B -> result	v7/A32/
 uint16x4_t vreinterpret_u16_p8(poly8x8_t a)	a -> Vd.8B	NOP	Vd.4H -> result	v7/A32/A64
 uint32x2_t vreinterpret_u32_p8(poly8x8_t a)	a -> Vd.8B	NOP	Vd.2S -> result	v7/A32/A64
 poly16x4_t vreinterpret_p16_p8(poly8x8_t a)	a -> Vd.8B	NOP	Vd.4H -> result	v7/A32/A64
+mfloat8x8_t vreinterpret_mf8_p8(poly8x8_t a)	a -> Vd.8B	NOP	Vd.8B -> result	A64
 uint64x1_t vreinterpret_u64_p8(poly8x8_t a)	a -> Vd.8B	NOP	Vd.1D -> result	v7/A32/A64
 int64x1_t vreinterpret_s64_p8(poly8x8_t a)	a -> Vd.8B	NOP	Vd.1D -> result	v7/A32/A64
 float64x1_t vreinterpret_f64_p8(poly8x8_t a)	a -> Vd.8B	NOP	Vd.1D -> result	A64
@@ -3607,6 +3612,7 @@ float32x2_t vreinterpret_f32_mf8(mfloat8x8_t a)	a -> Vd.8B	NOP	Vd.2S -> result	A
 uint8x8_t vreinterpret_u8_mf8(mfloat8x8_t a)	a -> Vd.8B	NOP	Vd.8B -> result	A64
 uint16x4_t vreinterpret_u16_mf8(mfloat8x8_t a)	a -> Vd.8B	NOP	Vd.4H -> result	A64
 uint32x2_t vreinterpret_u32_mf8(mfloat8x8_t a)	a -> Vd.8B	NOP	Vd.2S -> result	A64
+poly8x8_t vreinterpret_p8_mf8(mfloat8x8_t a)	a -> Vd.8B	NOP	Vd.8B -> result	A64
 poly16x4_t vreinterpret_p16_mf8(mfloat8x8_t a)	a -> Vd.8B	NOP	Vd.4H -> result	A64
 uint64x1_t vreinterpret_u64_mf8(mfloat8x8_t a)	a -> Vd.8B	NOP	Vd.1D -> result	A64
 int64x1_t vreinterpret_s64_mf8(mfloat8x8_t a)	a -> Vd.8B	NOP	Vd.1D -> result	A64
@@ -3653,6 +3659,7 @@ poly16x4_t vreinterpret_p16_s64(int64x1_t a)	a -> Vd.1D	NOP	Vd.4H -> result	v7/A
 mfloat8x8_t vreinterpret_mf8_s64(int64x1_t a)	a -> Vd.1D	NOP	Vd.8B -> result	A64
 uint64x1_t vreinterpret_u64_s64(int64x1_t a)	a -> Vd.1D	NOP	Vd.1D -> result	v7/A32/A64
 float64x1_t vreinterpret_f64_s64(int64x1_t a)	a -> Vd.1D	NOP	Vd.1D -> result	A64
+poly64x1_t vreinterpret_p64_s64(int64x1_t a)	a -> Vd.1D	NOP	Vd.1D -> result	A32/A64
 uint64x1_t vreinterpret_u64_p64(poly64x1_t a)	a -> Vd.1D	NOP	Vd.1D -> result	A32/A64
 float16x4_t vreinterpret_f16_s64(int64x1_t a)	a -> Vd.1D	NOP	Vd.4H -> result	v7/A32/A64
 int8x8_t vreinterpret_s8_f16(float16x4_t a)	a -> Vd.4H	NOP	Vd.8B -> result	v7/A32/A64
@@ -3784,6 +3791,7 @@ uint8x16_t vreinterpretq_u8_p8(poly8x16_t a)	a -> Vd.16B	NOP	Vd.16B -> result	v7
 uint16x8_t vreinterpretq_u16_p8(poly8x16_t a)	a -> Vd.16B	NOP	Vd.8H -> result	v7/A32/A64
 uint32x4_t vreinterpretq_u32_p8(poly8x16_t a)	a -> Vd.16B	NOP	Vd.4S -> result	v7/A32/A64
 poly16x8_t vreinterpretq_p16_p8(poly8x16_t a)	a -> Vd.16B	NOP	Vd.8H -> result	v7/A32/A64
+mfloat8x16_t vreinterpretq_mf8_p8(poly8x16_t a)	a -> Vd.16B	NOP	Vd.16B -> result	A64
 uint64x2_t vreinterpretq_u64_p8(poly8x16_t a)	a -> Vd.16B	NOP	Vd.2D -> result	v7/A32/A64
 int64x2_t vreinterpretq_s64_p8(poly8x16_t a)	a -> Vd.16B	NOP	Vd.2D -> result	v7/A32/A64
 float64x2_t vreinterpretq_f64_p8(poly8x16_t a)	a -> Vd.16B	NOP	Vd.2D -> result	A64
@@ -3797,6 +3805,7 @@ float32x4_t vreinterpretq_f32_mf8(mfloat8x16_t a)	a -> Vd.16B	NOP	Vd.4S -> resul
 uint8x16_t vreinterpretq_u8_mf8(mfloat8x16_t a)	a -> Vd.16B	NOP	Vd.16B -> result	A64
 uint16x8_t vreinterpretq_u16_mf8(mfloat8x16_t a)	a -> Vd.16B	NOP	Vd.8H -> result	A64
 uint32x4_t vreinterpretq_u32_mf8(mfloat8x16_t a)	a -> Vd.16B	NOP	Vd.4S -> result	A64
+poly8x16_t vreinterpretq_p8_mf8(mfloat8x16_t a)	a -> Vd.16B	NOP	Vd.16B -> result	A64
 poly16x8_t vreinterpretq_p16_mf8(mfloat8x16_t a)	a -> Vd.16B	NOP	Vd.8H -> result	A64
 uint64x2_t vreinterpretq_u64_mf8(mfloat8x16_t a)	a -> Vd.16B	NOP	Vd.2D -> result	A64
 int64x2_t vreinterpretq_s64_mf8(mfloat8x16_t a)	a -> Vd.16B	NOP	Vd.2D -> result	A64
@@ -3894,6 +3903,7 @@ float32x4_t vreinterpretq_f32_f64(float64x2_t a)	a -> Vd.2D	NOP	Vd.4S -> result
 int8x8_t vreinterpret_s8_p64(poly64x1_t a)	a -> Vd.1D	NOP	Vd.8B -> result	A32/A64
 int16x4_t vreinterpret_s16_p64(poly64x1_t a)	a -> Vd.1D	NOP	Vd.4H -> result	A32/A64
 int32x2_t vreinterpret_s32_p64(poly64x1_t a)	a -> Vd.1D	NOP	Vd.2S -> result	A32/A64
+float32x2_t vreinterpret_f32_p64(poly64x1_t a)	a -> Vd.1D	NOP	Vd.2S -> result	A32/A64
 uint8x8_t vreinterpret_u8_p64(poly64x1_t a)	a -> Vd.1D	NOP	Vd.8B -> result	A32/A64
 uint16x4_t vreinterpret_u16_p64(poly64x1_t a)	a -> Vd.1D	NOP	Vd.4H -> result	A32/A64
 uint32x2_t vreinterpret_u32_p64(poly64x1_t a)	a -> Vd.1D	NOP	Vd.2S -> result	A32/A64
@@ -3906,6 +3916,7 @@ float16x4_t vreinterpret_f16_p64(poly64x1_t a)	a -> Vd.1D	NOP	Vd.4H -> result	A3
 int8x16_t vreinterpretq_s8_p64(poly64x2_t a)	a -> Vd.2D	NOP	Vd.16B -> result	A32/A64
 int16x8_t vreinterpretq_s16_p64(poly64x2_t a)	a -> Vd.2D	NOP	Vd.8H -> result	A32/A64
 int32x4_t vreinterpretq_s32_p64(poly64x2_t a)	a -> Vd.2D	NOP	Vd.4S -> result	A32/A64
+float32x4_t vreinterpretq_f32_p64(poly64x2_t a)	a -> Vd.2D	NOP	Vd.4S -> result	A32/A64
 uint8x16_t vreinterpretq_u8_p64(poly64x2_t a)	a -> Vd.2D	NOP	Vd.16B -> result	A32/A64
 uint16x8_t vreinterpretq_u16_p64(poly64x2_t a)	a -> Vd.2D	NOP	Vd.8H -> result	A32/A64
 uint32x4_t vreinterpretq_u32_p64(poly64x2_t a)	a -> Vd.2D	NOP	Vd.4S -> result	A32/A64
@@ -3914,10 +3925,12 @@ poly16x8_t vreinterpretq_p16_p64(poly64x2_t a)	a -> Vd.2D	NOP	Vd.8H -> result	A3
 mfloat8x16_t vreinterpretq_mf8_p64(poly64x2_t a)	a -> Vd.2D	NOP	Vd.16B -> result	A64
 int64x2_t vreinterpretq_s64_p64(poly64x2_t a)	a -> Vd.2D	NOP	Vd.2D -> result	A32/A64
 float64x2_t vreinterpretq_f64_p64(poly64x2_t a)	a -> Vd.2D	NOP	Vd.2D -> result	A64
+poly128_t vreinterpretq_p128_p64(poly64x2_t a)	a -> Vd.2D	NOP	Vd.1Q -> result	A32/A64
 float16x8_t vreinterpretq_f16_p64(poly64x2_t a)	a -> Vd.2D	NOP	Vd.8H -> result	A32/A64
 int8x16_t vreinterpretq_s8_p128(poly128_t a)	a -> Vd.1Q	NOP	Vd.16B -> result	A32/A64
 int16x8_t vreinterpretq_s16_p128(poly128_t a)	a -> Vd.1Q	NOP	Vd.8H -> result	A32/A64
 int32x4_t vreinterpretq_s32_p128(poly128_t a)	a -> Vd.1Q	NOP	Vd.4S -> result	A32/A64
+float32x4_t vreinterpretq_f32_p128(poly128_t a)	a -> Vd.1Q	NOP	Vd.4S -> result	A32/A64
 uint8x16_t vreinterpretq_u8_p128(poly128_t a)	a -> Vd.1Q	NOP	Vd.16B -> result	A32/A64
 uint16x8_t vreinterpretq_u16_p128(poly128_t a)	a -> Vd.1Q	NOP	Vd.8H -> result	A32/A64
 uint32x4_t vreinterpretq_u32_p128(poly128_t a)	a -> Vd.1Q	NOP	Vd.4S -> result	A32/A64
@@ -3927,6 +3940,7 @@ mfloat8x16_t vreinterpretq_mf8_p128(poly128_t a)	a -> Vd.1Q	NOP	Vd.16B -> result
 uint64x2_t vreinterpretq_u64_p128(poly128_t a)	a -> Vd.1Q	NOP	Vd.2D -> result	A32/A64
 int64x2_t vreinterpretq_s64_p128(poly128_t a)	a -> Vd.1Q	NOP	Vd.2D -> result	A32/A64
 float64x2_t vreinterpretq_f64_p128(poly128_t a)	a -> Vd.1Q	NOP	Vd.2D -> result	A64
+poly64x2_t vreinterpretq_p64_p128(poly128_t a)	a -> Vd.1Q	NOP	Vd.2D -> result	A32/A64
 float16x8_t vreinterpretq_f16_p128(poly128_t a)	a -> Vd.1Q	NOP	Vd.8H -> result	A32/A64
 mfloat8x8_t vreinterpret_mf8_u8(uint8x8_t a)	a -> Vd.8B	NOP	Vd.8B -> result	A64
 mfloat8x16_t vreinterpretq_mf8_u8(uint8x16_t a)	a -> Vd.16B	NOP	Vd.16B -> result	A64
@@ -4676,6 +4690,7 @@ bfloat16x8x4_t vld1q_bf16_x4(bfloat16_t const *ptr)	ptr -> Xn	LD1 {Vt.8H - Vt4.8
 bfloat16x4_t vreinterpret_bf16_s8(int8x8_t a)	a -> Vd.8B	NOP	Vd.4H -> result	A32/A64
 bfloat16x4_t vreinterpret_bf16_s16(int16x4_t a)	a -> Vd.4H	NOP	Vd.4H -> result	A32/A64
 bfloat16x4_t vreinterpret_bf16_s32(int32x2_t a)	a -> Vd.2S	NOP	Vd.4H -> result	A32/A64
+bfloat16x4_t vreinterpret_bf16_f16(float16x4_t a)	a -> Vd.4H	NOP	Vd.4H -> result	A32/A64
 bfloat16x4_t vreinterpret_bf16_f32(float32x2_t a)	a -> Vd.2S	NOP	Vd.4H -> result	A32/A64
 bfloat16x4_t vreinterpret_bf16_u8(uint8x8_t a)	a -> Vd.8B	NOP	Vd.4H -> result	A32/A64
 bfloat16x4_t vreinterpret_bf16_u16(uint16x4_t a)	a -> Vd.4H	NOP	Vd.4H -> result	A32/A64
@@ -4688,6 +4703,7 @@ bfloat16x4_t vreinterpret_bf16_s64(int64x1_t a)	a -> Vd.1D	NOP	Vd.4H -> result	A
 bfloat16x8_t vreinterpretq_bf16_s8(int8x16_t a)	a -> Vd.16B	NOP	Vd.8H -> result	A32/A64
 bfloat16x8_t vreinterpretq_bf16_s16(int16x8_t a)	a -> Vd.8H	NOP	Vd.8H -> result	A32/A64
 bfloat16x8_t vreinterpretq_bf16_s32(int32x4_t a)	a -> Vd.4S	NOP	Vd.8H -> result	A32/A64
+bfloat16x8_t vreinterpretq_bf16_f16(float16x8_t a)	a -> Vd.8H	NOP	Vd.8H -> result	A32/A64
 bfloat16x8_t vreinterpretq_bf16_f32(float32x4_t a)	a -> Vd.4S	NOP	Vd.8H -> result	A32/A64
 bfloat16x8_t vreinterpretq_bf16_u8(uint8x16_t a)	a -> Vd.16B	NOP	Vd.8H -> result	A32/A64
 bfloat16x8_t vreinterpretq_bf16_u16(uint16x8_t a)	a -> Vd.8H	NOP	Vd.8H -> result	A32/A64
@@ -4706,6 +4722,7 @@ bfloat16x8_t vreinterpretq_bf16_p128(poly128_t a)	a -> Vd.1Q	NOP	Vd.8H -> result
 int8x8_t vreinterpret_s8_bf16(bfloat16x4_t a)	a -> Vd.4H	NOP	Vd.8B -> result	A32/A64
 int16x4_t vreinterpret_s16_bf16(bfloat16x4_t a)	a -> Vd.4H	NOP	Vd.4H -> result	A32/A64
 int32x2_t vreinterpret_s32_bf16(bfloat16x4_t a)	a -> Vd.4H	NOP	Vd.2S -> result	A32/A64
+float16x4_t vreinterpret_f16_bf16(bfloat16x4_t a)	a -> Vd.4H	NOP	Vd.4H -> result	A32/A64
 float32x2_t vreinterpret_f32_bf16(bfloat16x4_t a)	a -> Vd.4H	NOP	Vd.2S -> result	A32/A64
 uint8x8_t vreinterpret_u8_bf16(bfloat16x4_t a)	a -> Vd.4H	NOP	Vd.8B -> result	A32/A64
 uint16x4_t vreinterpret_u16_bf16(bfloat16x4_t a)	a -> Vd.4H	NOP	Vd.4H -> result	A32/A64
@@ -4732,6 +4749,7 @@ int64x2_t vreinterpretq_s64_bf16(bfloat16x8_t a)	a -> Vd.8H	NOP	Vd.2D -> result
 float64x2_t vreinterpretq_f64_bf16(bfloat16x8_t a)	a -> Vd.8H	NOP	Vd.2D -> result	A64
 poly64x2_t vreinterpretq_p64_bf16(bfloat16x8_t a)	a -> Vd.8H	NOP	Vd.2D -> result	A32/A64
 poly128_t vreinterpretq_p128_bf16(bfloat16x8_t a)	a -> Vd.8H	NOP	Vd.1Q -> result	A32/A64
+float16x8_t vreinterpretq_f16_bf16(bfloat16x8_t a)	a -> Vd.8H	NOP	Vd.8H -> result	A32/A64
 
 float32x4_t vcvt_f32_bf16(bfloat16x4_t a)	a -> Vn.8H	SHLL Vd.4S,Vn.8H, #16	Vd.4S -> result	A32/A64
 float32x4_t vcvtq_low_f32_bf16(bfloat16x8_t a)	a -> Vn.8H	SHLL Vd.4S,Vn.8H, #16	Vd.4S -> result	A32/A64
diff --git a/tools/intrinsic_db/advsimd_classification.csv b/tools/intrinsic_db/advsimd_classification.csv
index 1c3de29c..55f85f15 100644
--- a/tools/intrinsic_db/advsimd_classification.csv
+++ b/tools/intrinsic_db/advsimd_classification.csv
@@ -684,6 +684,8 @@ vtst_u32	Compare|Bitwise not equal to zero
 vtstq_u32	Compare|Bitwise not equal to zero
 vtst_p8	Compare|Bitwise not equal to zero
 vtstq_p8	Compare|Bitwise not equal to zero
+vtst_p16	Compare|Bitwise not equal to zero
+vtstq_p16	Compare|Bitwise not equal to zero
 vtst_s64	Compare|Bitwise not equal to zero
 vtstq_s64	Compare|Bitwise not equal to zero
 vtst_u64	Compare|Bitwise not equal to zero
@@ -1966,6 +1968,8 @@ vmov_n_p8	Vector manipulation|Set all lanes to the same value
 vmovq_n_p8	Vector manipulation|Set all lanes to the same value
 vmov_n_p16	Vector manipulation|Set all lanes to the same value
 vmovq_n_p16	Vector manipulation|Set all lanes to the same value
+vmov_n_p64	Vector manipulation|Set all lanes to the same value
+vmovq_n_p64	Vector manipulation|Set all lanes to the same value
 vmov_n_f64	Vector manipulation|Set all lanes to the same value
 vmovq_n_f64	Vector manipulation|Set all lanes to the same value
 vmov_n_mf8	Vector manipulation|Set all lanes to the same value
@@ -3594,6 +3598,7 @@ vreinterpret_u8_p8	Data type conversion|Reinterpret casts
 vreinterpret_u16_p8	Data type conversion|Reinterpret casts
 vreinterpret_u32_p8	Data type conversion|Reinterpret casts
 vreinterpret_p16_p8	Data type conversion|Reinterpret casts
+vreinterpret_mf8_p8	Data type conversion|Reinterpret casts
 vreinterpret_u64_p8	Data type conversion|Reinterpret casts
 vreinterpret_s64_p8	Data type conversion|Reinterpret casts
 vreinterpret_f64_p8	Data type conversion|Reinterpret casts
@@ -3607,6 +3612,7 @@ vreinterpret_f32_mf8	Data type conversion|Reinterpret casts
 vreinterpret_u8_mf8	Data type conversion|Reinterpret casts
 vreinterpret_u16_mf8	Data type conversion|Reinterpret casts
 vreinterpret_u32_mf8	Data type conversion|Reinterpret casts
+vreinterpret_p8_mf8	Data type conversion|Reinterpret casts
 vreinterpret_p16_mf8	Data type conversion|Reinterpret casts
 vreinterpret_u64_mf8	Data type conversion|Reinterpret casts
 vreinterpret_s64_mf8	Data type conversion|Reinterpret casts
@@ -3654,6 +3660,7 @@ vreinterpret_p16_s64	Data type conversion|Reinterpret casts
 vreinterpret_mf8_s64	Data type conversion|Reinterpret casts
 vreinterpret_u64_s64	Data type conversion|Reinterpret casts
 vreinterpret_f64_s64	Data type conversion|Reinterpret casts
+vreinterpret_p64_s64	Data type conversion|Reinterpret casts
 vreinterpret_u64_p64	Data type conversion|Reinterpret casts
 vreinterpret_f16_s64	Data type conversion|Reinterpret casts
 vreinterpret_s8_f16	Data type conversion|Reinterpret casts
@@ -3785,6 +3792,7 @@ vreinterpretq_u8_p8	Data type conversion|Reinterpret casts
 vreinterpretq_u16_p8	Data type conversion|Reinterpret casts
 vreinterpretq_u32_p8	Data type conversion|Reinterpret casts
 vreinterpretq_p16_p8	Data type conversion|Reinterpret casts
+vreinterpretq_mf8_p8	Data type conversion|Reinterpret casts
 vreinterpretq_u64_p8	Data type conversion|Reinterpret casts
 vreinterpretq_s64_p8	Data type conversion|Reinterpret casts
 vreinterpretq_f64_p8	Data type conversion|Reinterpret casts
@@ -3799,6 +3807,7 @@ vreinterpretq_f32_mf8	Data type conversion|Reinterpret casts
 vreinterpretq_u8_mf8	Data type conversion|Reinterpret casts
 vreinterpretq_u16_mf8	Data type conversion|Reinterpret casts
 vreinterpretq_u32_mf8	Data type conversion|Reinterpret casts
+vreinterpretq_p8_mf8	Data type conversion|Reinterpret casts
 vreinterpretq_p16_mf8	Data type conversion|Reinterpret casts
 vreinterpretq_u64_mf8	Data type conversion|Reinterpret casts
 vreinterpretq_s64_mf8	Data type conversion|Reinterpret casts
@@ -3897,6 +3906,7 @@ vreinterpretq_f32_f64	Data type conversion|Reinterpret casts
 vreinterpret_s8_p64	Data type conversion|Reinterpret casts
 vreinterpret_s16_p64	Data type conversion|Reinterpret casts
 vreinterpret_s32_p64	Data type conversion|Reinterpret casts
+vreinterpret_f32_p64	Data type conversion|Reinterpret casts
 vreinterpret_u8_p64	Data type conversion|Reinterpret casts
 vreinterpret_u16_p64	Data type conversion|Reinterpret casts
 vreinterpret_u32_p64	Data type conversion|Reinterpret casts
@@ -3909,6 +3919,7 @@ vreinterpret_f16_p64	Data type conversion|Reinterpret casts
 vreinterpretq_s8_p64	Data type conversion|Reinterpret casts
 vreinterpretq_s16_p64	Data type conversion|Reinterpret casts
 vreinterpretq_s32_p64	Data type conversion|Reinterpret casts
+vreinterpretq_f32_p64	Data type conversion|Reinterpret casts
 vreinterpretq_u8_p64	Data type conversion|Reinterpret casts
 vreinterpretq_u16_p64	Data type conversion|Reinterpret casts
 vreinterpretq_u32_p64	Data type conversion|Reinterpret casts
@@ -3917,10 +3928,12 @@ vreinterpretq_p16_p64	Data type conversion|Reinterpret casts
 vreinterpretq_mf8_p64	Data type conversion|Reinterpret casts
 vreinterpretq_s64_p64	Data type conversion|Reinterpret casts
 vreinterpretq_f64_p64	Data type conversion|Reinterpret casts
+vreinterpretq_p128_p64	Data type conversion|Reinterpret casts
 vreinterpretq_f16_p64	Data type conversion|Reinterpret casts
 vreinterpretq_s8_p128	Data type conversion|Reinterpret casts
 vreinterpretq_s16_p128	Data type conversion|Reinterpret casts
 vreinterpretq_s32_p128	Data type conversion|Reinterpret casts
+vreinterpretq_f32_p128	Data type conversion|Reinterpret casts
 vreinterpretq_u8_p128	Data type conversion|Reinterpret casts
 vreinterpretq_u16_p128	Data type conversion|Reinterpret casts
 vreinterpretq_u32_p128	Data type conversion|Reinterpret casts
@@ -3930,6 +3943,7 @@ vreinterpretq_mf8_p128	Data type conversion|Reinterpret casts
 vreinterpretq_u64_p128	Data type conversion|Reinterpret casts
 vreinterpretq_s64_p128	Data type conversion|Reinterpret casts
 vreinterpretq_f64_p128	Data type conversion|Reinterpret casts
+vreinterpretq_p64_p128	Data type conversion|Reinterpret casts
 vreinterpretq_f16_p128	Data type conversion|Reinterpret casts
 vreinterpret_mf8_u8	Data type conversion|Reinterpret casts
 vreinterpretq_mf8_u8	Data type conversion|Reinterpret casts
@@ -4522,6 +4536,7 @@ vld1q_bf16_x4	Load|Stride
 vreinterpret_bf16_s8	Data type conversion|Reinterpret casts
 vreinterpret_bf16_s16	Data type conversion|Reinterpret casts
 vreinterpret_bf16_s32	Data type conversion|Reinterpret casts
+vreinterpret_bf16_f16	Data type conversion|Reinterpret casts
 vreinterpret_bf16_f32	Data type conversion|Reinterpret casts
 vreinterpret_bf16_u8	Data type conversion|Reinterpret casts
 vreinterpret_bf16_u16	Data type conversion|Reinterpret casts
@@ -4534,6 +4549,7 @@ vreinterpret_bf16_s64	Data type conversion|Reinterpret casts
 vreinterpretq_bf16_s8	Data type conversion|Reinterpret casts
 vreinterpretq_bf16_s16	Data type conversion|Reinterpret casts
 vreinterpretq_bf16_s32	Data type conversion|Reinterpret casts
+vreinterpretq_bf16_f16	Data type conversion|Reinterpret casts
 vreinterpretq_bf16_f32	Data type conversion|Reinterpret casts
 vreinterpretq_bf16_u8	Data type conversion|Reinterpret casts
 vreinterpretq_bf16_u16	Data type conversion|Reinterpret casts
@@ -4551,6 +4567,7 @@ vreinterpretq_bf16_p128	Data type conversion|Reinterpret casts
 vreinterpret_s8_bf16	Data type conversion|Reinterpret casts
 vreinterpret_s16_bf16	Data type conversion|Reinterpret casts
 vreinterpret_s32_bf16	Data type conversion|Reinterpret casts
+vreinterpret_f16_bf16	Data type conversion|Reinterpret casts
 vreinterpret_f32_bf16	Data type conversion|Reinterpret casts
 vreinterpret_u8_bf16	Data type conversion|Reinterpret casts
 vreinterpret_u16_bf16	Data type conversion|Reinterpret casts
@@ -4565,6 +4582,7 @@ vreinterpret_p64_bf16	Data type conversion|Reinterpret casts
 vreinterpretq_s8_bf16	Data type conversion|Reinterpret casts
 vreinterpretq_s16_bf16	Data type conversion|Reinterpret casts
 vreinterpretq_s32_bf16	Data type conversion|Reinterpret casts
+vreinterpretq_f16_bf16	Data type conversion|Reinterpret casts
 vreinterpretq_f32_bf16	Data type conversion|Reinterpret casts
 vreinterpretq_u8_bf16	Data type conversion|Reinterpret casts
 vreinterpretq_u16_bf16	Data type conversion|Reinterpret casts