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aknautiyalgregkh
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drm/i915/dp: Add device specific quirk to limit eDP rate to HBR2
commit 21c586d9233a1f258e8d437466c441d50885d30f upstream. Some ICL/TGL platforms with combo PHY ports suffer from signal integrity issues at HBR3. While certain systems include a Parade PS8461 mux to mitigate this, its presence cannot be reliably detected. Furthermore, broken or missing VBT entries make it unsafe to rely on VBT for enforcing link rate limits. To address this introduce a device specific quirk to cap the eDP link rate to HBR2 (540000 kHz). This will override any higher advertised rates from the sink or DPCD for specific devices. Currently, the quirk is added for Dell XPS 13 7390 2-in-1 which is reported in gitlab issue #5969 [1]. [1] https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5969 v2: Align the quirk with the intended quirk name and refactor the condition to use min(). (Jani) v3: Use condition `rate > 540000`. Drop extra parentheses. (Ville) Cc: Jani Nikula <[email protected]> Cc: Ville Syrjälä <[email protected]> Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5969 Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Ankit Nautiyal <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
1 parent a6d47b0 commit f1ad80f

3 files changed

Lines changed: 44 additions & 7 deletions

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drivers/gpu/drm/i915/display/intel_dp.c

Lines changed: 34 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -173,10 +173,24 @@ int intel_dp_link_symbol_clock(int rate)
173173

174174
static int max_dprx_rate(struct intel_dp *intel_dp)
175175
{
176+
struct intel_display *display = to_intel_display(intel_dp);
177+
int max_rate;
178+
176179
if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
177-
return drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel);
180+
max_rate = drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel);
181+
else
182+
max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
183+
184+
/*
185+
* Some platforms + eDP panels may not reliably support HBR3
186+
* due to signal integrity limitations, despite advertising it.
187+
* Cap the link rate to HBR2 to avoid unstable configurations for the
188+
* known machines.
189+
*/
190+
if (intel_dp_is_edp(intel_dp) && intel_has_quirk(display, QUIRK_EDP_LIMIT_RATE_HBR2))
191+
max_rate = min(max_rate, 540000);
178192

179-
return drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
193+
return max_rate;
180194
}
181195

182196
static int max_dprx_lane_count(struct intel_dp *intel_dp)
@@ -4261,6 +4275,8 @@ static void intel_edp_mso_init(struct intel_dp *intel_dp)
42614275
static void
42624276
intel_edp_set_sink_rates(struct intel_dp *intel_dp)
42634277
{
4278+
struct intel_display *display = to_intel_display(intel_dp);
4279+
42644280
intel_dp->num_sink_rates = 0;
42654281

42664282
if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
@@ -4271,18 +4287,29 @@ intel_edp_set_sink_rates(struct intel_dp *intel_dp)
42714287
sink_rates, sizeof(sink_rates));
42724288

42734289
for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4274-
int val = le16_to_cpu(sink_rates[i]);
4275-
4276-
if (val == 0)
4277-
break;
4290+
int rate;
42784291

42794292
/* Value read multiplied by 200kHz gives the per-lane
42804293
* link rate in kHz. The source rates are, however,
42814294
* stored in terms of LS_Clk kHz. The full conversion
42824295
* back to symbols is
42834296
* (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
42844297
*/
4285-
intel_dp->sink_rates[i] = (val * 200) / 10;
4298+
rate = le16_to_cpu(sink_rates[i]) * 200 / 10;
4299+
4300+
if (rate == 0)
4301+
break;
4302+
4303+
/*
4304+
* Some platforms cannot reliably drive HBR3 rates due to PHY limitations,
4305+
* even if the sink advertises support. Reject any sink rates above HBR2 on
4306+
* the known machines for stable output.
4307+
*/
4308+
if (rate > 540000 &&
4309+
intel_has_quirk(display, QUIRK_EDP_LIMIT_RATE_HBR2))
4310+
break;
4311+
4312+
intel_dp->sink_rates[i] = rate;
42864313
}
42874314
intel_dp->num_sink_rates = i;
42884315
}

drivers/gpu/drm/i915/display/intel_quirks.c

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -80,6 +80,12 @@ static void quirk_fw_sync_len(struct intel_dp *intel_dp)
8080
drm_info(display->drm, "Applying Fast Wake sync pulse count quirk\n");
8181
}
8282

83+
static void quirk_edp_limit_rate_hbr2(struct intel_display *display)
84+
{
85+
intel_set_quirk(display, QUIRK_EDP_LIMIT_RATE_HBR2);
86+
drm_info(display->drm, "Applying eDP Limit rate to HBR2 quirk\n");
87+
}
88+
8389
struct intel_quirk {
8490
int device;
8591
int subsystem_vendor;
@@ -231,6 +237,9 @@ static struct intel_quirk intel_quirks[] = {
231237
{ 0x3184, 0x1019, 0xa94d, quirk_increase_ddi_disabled_time },
232238
/* HP Notebook - 14-r206nv */
233239
{ 0x0f31, 0x103c, 0x220f, quirk_invert_brightness },
240+
241+
/* Dell XPS 13 7390 2-in-1 */
242+
{ 0x8a12, 0x1028, 0x08b0, quirk_edp_limit_rate_hbr2 },
234243
};
235244

236245
static const struct intel_dpcd_quirk intel_dpcd_quirks[] = {

drivers/gpu/drm/i915/display/intel_quirks.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,7 @@ enum intel_quirk_id {
2020
QUIRK_LVDS_SSC_DISABLE,
2121
QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK,
2222
QUIRK_FW_SYNC_LEN,
23+
QUIRK_EDP_LIMIT_RATE_HBR2,
2324
};
2425

2526
void intel_init_quirks(struct intel_display *display);

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