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Merge remote-tracking branch 'stable/linux-6.14.y' into v6.14+
2 parents d1b1f83 + d12acd7 commit 32fca0b

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‎Documentation/admin-guide/kernel-parameters.txt‎

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* max_sec_lba48: Set or clear transfer size limit to
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65535 sectors.
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* external: Mark port as external (hotplug-capable).
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* [no]lpm: Enable or disable link power management.
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* [no]setxfer: Indicate if transfer speed mode setting

‎Documentation/arch/arm64/silicon-errata.rst‎

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@@ -284,6 +284,8 @@ stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
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| Rockchip | RK3588 | #3588001 | ROCKCHIP_ERRATUM_3588001 |
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+----------------+-----------------+-----------------+-----------------------------+
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| Rockchip | RK3568 | #3568002 | ROCKCHIP_ERRATUM_3568002 |
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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| Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 |
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+----------------+-----------------+-----------------+-----------------------------+

‎Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml‎

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- const: arm,primecell
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reg:
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minItems: 1
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maxItems: 2
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maxItems: 1
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clocks:
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maxItems: 1

‎Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml‎

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- const: arm,primecell
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reg:
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minItems: 1
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maxItems: 2
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maxItems: 1
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qcom,dsb-element-bits:
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description:

‎Documentation/devicetree/bindings/media/i2c/st,st-mipid02.yaml‎

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description:
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Any lane can be inverted or not.
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minItems: 1
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maxItems: 2
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maxItems: 3
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required:
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- data-lanes

‎Makefile‎

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# SPDX-License-Identifier: GPL-2.0
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VERSION = 6
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PATCHLEVEL = 14
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SUBLEVEL = 2
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SUBLEVEL = 3
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EXTRAVERSION =
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NAME = Baby Opossum Posse
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@@ -1064,6 +1064,9 @@ KBUILD_CFLAGS += -fno-strict-overflow
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# Make sure -fstack-check isn't enabled (like gentoo apparently did)
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KBUILD_CFLAGS += -fno-stack-check
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# Ensure compilers do not transform certain loops into calls to wcslen()
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KBUILD_CFLAGS += -fno-builtin-wcslen
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# change __FILE__ to the relative path to the source directory
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ifdef building_out_of_srctree
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KBUILD_CPPFLAGS += $(call cc-option,-fmacro-prefix-map=$(srcroot)/=)

‎arch/arm/lib/crc-t10dif-glue.c‎

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@@ -44,9 +44,7 @@ u16 crc_t10dif_arch(u16 crc, const u8 *data, size_t length)
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crc_t10dif_pmull8(crc, data, length, buf);
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kernel_neon_end();
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crc = 0;
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data = buf;
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length = sizeof(buf);
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return crc_t10dif_generic(0, buf, sizeof(buf));
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}
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}
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return crc_t10dif_generic(crc, data, length);

‎arch/arm64/Kconfig‎

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If unsure, say Y.
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config ROCKCHIP_ERRATUM_3568002
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bool "Rockchip 3568002: GIC600 can not access physical addresses higher than 4GB"
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default y
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help
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The Rockchip RK3566 and RK3568 GIC600 SoC integrations have AXI
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addressing limited to the first 32bit of physical address space.
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If unsure, say Y.
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config ROCKCHIP_ERRATUM_3588001
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bool "Rockchip 3588001: GIC600 can not support shareability attributes"
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default y

‎arch/arm64/boot/dts/exynos/google/gs101.dtsi‎

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/* TODO: update once support for this CMU exists */
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clocks = <0>;
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clock-names = "pclk";
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status = "disabled";
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};
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cmu_top: clock-controller@1e080000 {

‎arch/arm64/boot/dts/mediatek/mt8173.dtsi‎

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};
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pwm0: pwm@1401e000 {
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compatible = "mediatek,mt8173-disp-pwm",
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"mediatek,mt6595-disp-pwm";
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compatible = "mediatek,mt8173-disp-pwm";
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reg = <0 0x1401e000 0 0x1000>;
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#pwm-cells = <2>;
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clocks = <&mmsys CLK_MM_DISP_PWM026M>,
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};
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pwm1: pwm@1401f000 {
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compatible = "mediatek,mt8173-disp-pwm",
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"mediatek,mt6595-disp-pwm";
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compatible = "mediatek,mt8173-disp-pwm";
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reg = <0 0x1401f000 0 0x1000>;
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#pwm-cells = <2>;
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clocks = <&mmsys CLK_MM_DISP_PWM126M>,

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