You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
Copy file name to clipboardExpand all lines: README.md
+61-12Lines changed: 61 additions & 12 deletions
Display the source diff
Display the rich diff
Original file line number
Diff line number
Diff line change
@@ -4,8 +4,10 @@ This is a GCC plugin and helper ABI for a balanced-ternary ISA. It analyzes tern
4
4
expressions in C/C++ and can lower them to helper calls that map to ternary ISA
5
5
instructions.
6
6
7
+
**Note:** This project is a passion/research effort exploring ternary logic, which has theoretical advantages in arithmetic and AI contexts. It is currently at an early stage, compiling and running toy examples, rather than a mature toolchain component.
@@ -90,10 +112,9 @@ Ternary logic is defined with min/max semantics:
90
112
91
113
- tand(a,b) = min(a,b)
92
114
- tor(a,b) = max(a,b)
93
-
- txor(a,b) = a + b - 2 * min(a,b) - 2 * max(a,b) (ISA may choose alternative ternary XOR)
115
+
- txor(a,b) = 0 if a == b, else -a if b == 0, else -b if a == 0, else 0
94
116
95
-
Implementations may choose a different ternary XOR definition, but it must be
96
-
documented and stable.
117
+
This definition is stable and documented.
97
118
98
119
### Comparisons
99
120
@@ -176,8 +197,8 @@ but operand formats and semantics are fully specified. The ISA operates on packe
176
197
- Fn: IEEE floating-point register (f32/f64).
177
198
- Imm: immediate value (binary-encoded).
178
199
179
-
Ternary registers have a fixed trit width per instruction variant (e.g., t6, t12,
180
-
t24, t48, t96, t192). The width is encoded in the mnemonic suffix.
200
+
Ternary registers have a fixed trit width per instruction variant (e.g., t32, t64,
201
+
t128). The width is encoded in the mnemonic suffix.
181
202
182
203
### Register and Instruction Formats
183
204
@@ -190,6 +211,18 @@ The base ISA assumes a three-operand format for ternary ALU operations:
190
211
191
212
Where:
192
213
- Td/Ta/Tb/Tc are ternary registers of width tN.
214
+
215
+
## Roadmap / Next Steps
216
+
217
+
Priority | Suggestion | Why it helps | Status
218
+
--- | --- | --- | ---
219
+
High | Finish/clean lowering for common ops (add/sub/mul/neg/cmp/select/conv) | Lets users write straightforward ternary arithmetic without manual loops | In progress
220
+
High | Small portable runtime lib for t32/t64 | Enables real programs and benchmarking | Implemented (reference runtime in `runtime/`)
221
+
Medium | Trit-count-aware constant folding in plugin | Allows constants like `t32_t x = 42` to fold when representable | In progress
222
+
Medium | Better ternary type creation and user-facing syntax (e.g., `__ternary(32)` or attributes) | Easier adoption | Planned
223
+
Medium | Dump stats on how many ternary ops survive to RTL/assembly | Quantifies remaining work for hardware targets | Planned
0 commit comments