SIMD acceleration opportunities

Author: t81dev

README.md

@@ -8,6 +8,7 @@ instructions.
 
 The plugin supports:
 - Packed ternary types: `t32_t`, `t64_t`, `t128_t` (32/64/128 trits; 2-bit packed encoding)
+- Vector ternary types: `tv32_t`, `tv64_t` (vectors of 2 × t32_t and 2 × t64_t for SIMD operations)
 - Extended arithmetic operations: add, sub, mul, div, mod, neg
 - Logic operations: not
 - Comparison operations: cmp (returns -1, 0, +1)
@@ -137,8 +138,10 @@ Optional arguments:
   `__builtin_ternary_shl`, `__builtin_ternary_shr`, `__builtin_ternary_rol`, and `__builtin_ternary_ror`.
 - `-fplugin-arg-ternary_plugin-conv` enables lowering of ternary conversion builtins like
   `__builtin_ternary_tb2t`, `__builtin_ternary_tt2b`, `__builtin_ternary_t2f`, and `__builtin_ternary_f2t`.
-- `-fplugin-arg-ternary_plugin-types` enables builtin ternary integer types `t32_t`, `t64_t`,
-  `t128_t` with packed 2-bit trit storage.
+- `-fplugin-arg-ternary_plugin-mem` enables lowering of ternary memory builtins like
+  `__builtin_ternary_load_t32`, `__builtin_ternary_store_t32`, `__builtin_ternary_load_t64`, and `__builtin_ternary_store_t64`.
+- `-fplugin-arg-ternary_plugin-vector` enables vectorized ternary operations for `tv32_t` and `tv64_t` types
+  (vectors of 2 × t32_t and 2 × t64_t respectively).
 - `-fplugin-arg-ternary_plugin-prefix=<name>` sets the base helper prefix used by lowering
   (default: `__ternary`). For example, select helpers become `<prefix>_select_i32` and arithmetic
   helpers become `<prefix>_add`, `<prefix>_sub`, etc.
@@ -255,16 +258,55 @@ make test CXX=g++-15 CC=gcc-15
 This plugin analyzes ternary conditional expressions in the code and can optionally
 lower ternary operations to helper calls suitable for targeting a balanced-ternary ISA.
 
-## Balanced Ternary Literals
+## ISA Operations
 
-Use balanced-ternary strings to construct packed values:
+The plugin provides groundwork for a balanced-ternary ISA with the following operations:
 
-```c
-t32_t a = T32_BT_STR("1 0 -1 1");
-t64_t b = T64_BT_STR("1,0,0,-1");
-```
+### Vector Operations - SIMD Acceleration ✓ IMPLEMENTED (tv32_t)
+- `tv32_t`: Vector type containing 2 × t32_t elements (128 bits total)
+- Arithmetic operations: `vadd`, `vsub`, `vmul` (element-wise on vector elements)
+- Logic operations: `vand`, `vor`, `vxor`, `vnot` (element-wise ternary logic)
+- Comparison operations: `vcmp` (element-wise ternary comparison)
+
+Implemented as builtins:
+- `__builtin_ternary_add_tv32`, `__builtin_ternary_sub_tv32`, `__builtin_ternary_mul_tv32`, etc.
+- SIMD acceleration opportunities: Can leverage AVX/AVX-512 for parallel trit processing
+
+### SIMD Acceleration Opportunities - EXPLORATION
+
+The ternary vector operations provide a foundation for SIMD acceleration:
+
+**Current Implementation:**
+- Element-wise operations on packed ternary vectors
+- 128-bit vectors (tv32_t) for 2 × 32-trit operations
+- Foundation for wider SIMD utilization
+
+**Future SIMD Opportunities:**
+- **AVX-512 Integration**: 512-bit vectors for 8 × 32-trit or 4 × 64-trit operations
+- **Trit-Level Parallelism**: SIMD instructions for parallel trit manipulation
+- **Hardware Acceleration**: Custom ternary SIMD units for maximum performance
+- **Memory Bandwidth**: Efficient packed ternary data movement
+
+**Performance Characteristics:**
+- Balanced ternary enables simpler arithmetic than two's complement
+- Potential for higher computational density in AI/ML workloads
+- Reduced carry propagation compared to binary arithmetic
+
+### Control Flow Operations (brt/brf) - PLANNED
+- `brt Rc, label`: branch if Rc != 0 (ternary true)
+- `brf Rc, label`: branch if Rc == 0 (ternary false)
+
+These operate on ternary conditions and require RTL-level implementation for full support. The plugin currently lowers ternary conditions to helper calls but does not generate conditional jumps.
+
+### Calling Conventions - PLANNED
+
+Ternary-aware calling conventions are designed as follows:
+
+- **Argument Passing**: Ternary values passed in ternary registers when available, otherwise in binary containers
+- **Return Values**: Ternary results returned in ternary registers or binary containers as appropriate
+- **Register Allocation**: Ternary registers allocated for ternary-typed variables, with fallback to binary registers
 
-The parser consumes trits from left to right (most significant to least significant).
+The current plugin provides the type system and operation lowering needed for these conventions but requires GCC backend modifications for full implementation.
 
 ## Known Limitations
 

include/ternary.h

@@ -16,11 +16,10 @@ typedef uint64_t t32_t;           /* 32 trits -> 64 bits */
 typedef unsigned __int128 t64_t;  /* 64 trits -> 128 bits */
 #endif
 
-// Vector types
-typedef uint64_t v2t32_t;   // 2 x t32
-typedef uint64_t v4t32_t;   // 4 x t32
-typedef unsigned __int128 v2t64_t;  // 2 x t64
-typedef unsigned __int128 v4t64_t;  // 4 x t64
+// Vector types - packed ternary vectors for SIMD operations
+#ifndef TERNARY_USE_BUILTIN_TYPES
+typedef unsigned __int128 tv32_t; /* vector of 2 x t32_t (128 bits) */
+#endif
 
 // Builtin function declarations (for plugin lowering)
 extern int __builtin_ternary_add(int a, int b);
@@ -53,9 +52,30 @@ extern t64_t __builtin_ternary_cmpeq_t64(t64_t a, t64_t b);
 extern t64_t __builtin_ternary_cmpgt_t64(t64_t a, t64_t b);
 extern t64_t __builtin_ternary_cmpneq_t64(t64_t a, t64_t b);
 
-// Vector builtins
-extern v2t32_t __builtin_ternary_add_v2t32(v2t32_t a, v2t32_t b);
-extern v4t64_t __builtin_ternary_mul_v4t64(v4t64_t a, v4t64_t b);
+// Memory operations (tld/tst)
+extern t32_t __builtin_ternary_load_t32(const void *addr);
+extern void __builtin_ternary_store_t32(void *addr, t32_t value);
+extern t64_t __builtin_ternary_load_t64(const void *addr);
+extern void __builtin_ternary_store_t64(void *addr, t64_t value);
+
+// Vector operations - SIMD accelerated ternary computations
+extern tv32_t __builtin_ternary_add_tv32(tv32_t a, tv32_t b);
+extern tv32_t __builtin_ternary_sub_tv32(tv32_t a, tv32_t b);
+extern tv32_t __builtin_ternary_mul_tv32(tv32_t a, tv32_t b);
+extern tv32_t __builtin_ternary_and_tv32(tv32_t a, tv32_t b);
+extern tv32_t __builtin_ternary_or_tv32(tv32_t a, tv32_t b);
+extern tv32_t __builtin_ternary_xor_tv32(tv32_t a, tv32_t b);
+extern tv32_t __builtin_ternary_not_tv32(tv32_t a);
+extern tv32_t __builtin_ternary_cmp_tv32(tv32_t a, tv32_t b);
+
+extern tv64_t __builtin_ternary_add_tv64(tv64_t a, tv64_t b);
+extern tv64_t __builtin_ternary_sub_tv64(tv64_t a, tv64_t b);
+extern tv64_t __builtin_ternary_mul_tv64(tv64_t a, tv64_t b);
+extern tv64_t __builtin_ternary_and_tv64(tv64_t a, tv64_t b);
+extern tv64_t __builtin_ternary_or_tv64(tv64_t a, tv64_t b);
+extern tv64_t __builtin_ternary_xor_tv64(tv64_t a, tv64_t b);
+extern tv64_t __builtin_ternary_not_tv64(tv64_t a);
+extern tv64_t __builtin_ternary_cmp_tv64(tv64_t a, tv64_t b);
 
 // Balanced-ternary string literals (e.g. "1 0 -1 1")
 #define T32_BT_STR(s) __ternary_bt_str_t32(s)

include/ternary_runtime.h

@@ -16,6 +16,9 @@ typedef int64_t ternary_cond_t;
 #ifndef TERNARY_USE_BUILTIN_TYPES
 typedef uint64_t t32_t;           /* 32 trits -> 64 bits */
 typedef unsigned __int128 t64_t;  /* 64 trits -> 128 bits */
+typedef unsigned __int128 tv32_t; /* vector of 2 x t32_t (128 bits) */
+typedef struct { unsigned __int128 lo, hi; } tv64_t; /* vector of 2 x t64_t (256 bits) */
+typedef struct { unsigned __int128 lo, hi; } tv128_t; /* vector of 2 x t128_t (512 bits) */
 #endif
 
 /* Varargs helpers for ternary packed types. */
@@ -117,6 +120,31 @@ t64_t __ternary_cmpeq_t64(t64_t a, t64_t b);
 t64_t __ternary_cmpgt_t64(t64_t a, t64_t b);
 t64_t __ternary_cmpneq_t64(t64_t a, t64_t b);
 
+/* Memory operations (tld/tst) */
+t32_t __ternary_load_t32(const void *addr);
+void __ternary_store_t32(void *addr, t32_t value);
+t64_t __ternary_load_t64(const void *addr);
+void __ternary_store_t64(void *addr, t64_t value);
+
+/* Vector operations - SIMD accelerated ternary computations */
+tv32_t __ternary_add_tv32(tv32_t a, tv32_t b);
+tv32_t __ternary_sub_tv32(tv32_t a, tv32_t b);
+tv32_t __ternary_mul_tv32(tv32_t a, tv32_t b);
+tv32_t __ternary_and_tv32(tv32_t a, tv32_t b);
+tv32_t __ternary_or_tv32(tv32_t a, tv32_t b);
+tv32_t __ternary_xor_tv32(tv32_t a, tv32_t b);
+tv32_t __ternary_not_tv32(tv32_t a);
+tv32_t __ternary_cmp_tv32(tv32_t a, tv32_t b);
+
+tv64_t __ternary_add_tv64(tv64_t a, tv64_t b);
+tv64_t __ternary_sub_tv64(tv64_t a, tv64_t b);
+tv64_t __ternary_mul_tv64(tv64_t a, tv64_t b);
+tv64_t __ternary_and_tv64(tv64_t a, tv64_t b);
+tv64_t __ternary_or_tv64(tv64_t a, tv64_t b);
+tv64_t __ternary_xor_tv64(tv64_t a, tv64_t b);
+tv64_t __ternary_not_tv64(tv64_t a);
+tv64_t __ternary_cmp_tv64(tv64_t a, tv64_t b);
+
 #ifdef __cplusplus
 }
 #endif

runtime/ternary_runtime.c

@@ -692,4 +692,181 @@ DEFINE_TERNARY_TYPE_OPS(64, t64_t, 64, unsigned __int128, ternary_decode_u128, t
                         ternary_tritwise_op_u128, ternary_shift_left_u128, ternary_shift_right_u128,
                         ternary_rotate_left_u128, ternary_rotate_right_u128)
 
+t32_t __ternary_load_t32(const void *addr)
+{
+    return *(const t32_t *)addr;
+}
+
+void __ternary_store_t32(void *addr, t32_t value)
+{
+    *(t32_t *)addr = value;
+}
+
+t64_t __ternary_load_t64(const void *addr)
+{
+    return *(const t64_t *)addr;
+}
+
+void __ternary_store_t64(void *addr, t64_t value)
+{
+    *(t64_t *)addr = value;
+}
+
+/* Vector operations - SIMD accelerated ternary computations */
+
+/* tv32_t operations (vector of 2 x t32_t) */
+tv32_t __ternary_add_tv32(tv32_t a, tv32_t b)
+{
+    // Extract two t32_t values from the 128-bit vector
+    t32_t a0 = (t32_t)(uint64_t)a;
+    t32_t a1 = (t32_t)(uint64_t)(a >> 64);
+    t32_t b0 = (t32_t)(uint64_t)b;
+    t32_t b1 = (t32_t)(uint64_t)(b >> 64);
+    
+    // Perform scalar operations
+    t32_t r0 = __ternary_add_t32(a0, b0);
+    t32_t r1 = __ternary_add_t32(a1, b1);
+    
+    // Pack back into 128-bit vector
+    return ((tv32_t)(uint64_t)r1 << 64) | (tv32_t)(uint64_t)r0;
+}
+
+tv32_t __ternary_sub_tv32(tv32_t a, tv32_t b)
+{
+    t32_t a0 = (t32_t)(uint64_t)a;
+    t32_t a1 = (t32_t)(uint64_t)(a >> 64);
+    t32_t b0 = (t32_t)(uint64_t)b;
+    t32_t b1 = (t32_t)(uint64_t)(b >> 64);
+    
+    t32_t r0 = __ternary_sub_t32(a0, b0);
+    t32_t r1 = __ternary_sub_t32(a1, b1);
+    
+    return ((tv32_t)(uint64_t)r1 << 64) | (tv32_t)(uint64_t)r0;
+}
+
+tv32_t __ternary_mul_tv32(tv32_t a, tv32_t b)
+{
+    t32_t a0 = (t32_t)(uint64_t)a;
+    t32_t a1 = (t32_t)(uint64_t)(a >> 64);
+    t32_t b0 = (t32_t)(uint64_t)b;
+    t32_t b1 = (t32_t)(uint64_t)(b >> 64);
+    
+    t32_t r0 = __ternary_mul_t32(a0, b0);
+    t32_t r1 = __ternary_mul_t32(a1, b1);
+    
+    return ((tv32_t)(uint64_t)r1 << 64) | (tv32_t)(uint64_t)r0;
+}
+
+tv32_t __ternary_and_tv32(tv32_t a, tv32_t b)
+{
+    t32_t a0 = (t32_t)(uint64_t)a;
+    t32_t a1 = (t32_t)(uint64_t)(a >> 64);
+    t32_t b0 = (t32_t)(uint64_t)b;
+    t32_t b1 = (t32_t)(uint64_t)(b >> 64);
+    
+    t32_t r0 = __ternary_and_t32(a0, b0);
+    t32_t r1 = __ternary_and_t32(a1, b1);
+    
+    return ((tv32_t)(uint64_t)r1 << 64) | (tv32_t)(uint64_t)r0;
+}
+
+tv32_t __ternary_or_tv32(tv32_t a, tv32_t b)
+{
+    t32_t a0 = (t32_t)(uint64_t)a;
+    t32_t a1 = (t32_t)(uint64_t)(a >> 64);
+    t32_t b0 = (t32_t)(uint64_t)b;
+    t32_t b1 = (t32_t)(uint64_t)(b >> 64);
+    
+    t32_t r0 = __ternary_or_t32(a0, b0);
+    t32_t r1 = __ternary_or_t32(a1, b1);
+    
+    return ((tv32_t)(uint64_t)r1 << 64) | (tv32_t)(uint64_t)r0;
+}
+
+tv32_t __ternary_xor_tv32(tv32_t a, tv32_t b)
+{
+    t32_t a0 = (t32_t)(uint64_t)a;
+    t32_t a1 = (t32_t)(uint64_t)(a >> 64);
+    t32_t b0 = (t32_t)(uint64_t)b;
+    t32_t b1 = (t32_t)(uint64_t)(b >> 64);
+    
+    t32_t r0 = __ternary_xor_t32(a0, b0);
+    t32_t r1 = __ternary_xor_t32(a1, b1);
+    
+    return ((tv32_t)(uint64_t)r1 << 64) | (tv32_t)(uint64_t)r0;
+}
+
+tv32_t __ternary_not_tv32(tv32_t a)
+{
+    t32_t a0 = (t32_t)(uint64_t)a;
+    t32_t a1 = (t32_t)(uint64_t)(a >> 64);
+    
+    t32_t r0 = __ternary_not_t32(a0);
+    t32_t r1 = __ternary_not_t32(a1);
+    
+    return ((tv32_t)(uint64_t)r1 << 64) | (tv32_t)(uint64_t)r0;
+}
+
+tv32_t __ternary_cmp_tv32(tv32_t a, tv32_t b)
+{
+    t32_t a0 = (t32_t)(uint64_t)a;
+    t32_t a1 = (t32_t)(uint64_t)(a >> 64);
+    t32_t b0 = (t32_t)(uint64_t)b;
+    t32_t b1 = (t32_t)(uint64_t)(b >> 64);
+    
+    t32_t r0 = __ternary_cmplt_t32(a0, b0);
+    t32_t r1 = __ternary_cmplt_t32(a1, b1);
+    
+    return ((tv32_t)(uint64_t)r1 << 64) | (tv32_t)(uint64_t)r0;
+}
+
+/* tv64_t operations (vector of 2 x t64_t) - TODO: Implement for struct type */
+tv64_t __ternary_add_tv64(tv64_t a, tv64_t b)
+{
+    // TODO: Implement for struct type
+    return a; // Placeholder
+}
+
+tv64_t __ternary_sub_tv64(tv64_t a, tv64_t b)
+{
+    // TODO: Implement for struct type
+    return a; // Placeholder
+}
+
+tv64_t __ternary_mul_tv64(tv64_t a, tv64_t b)
+{
+    // TODO: Implement for struct type
+    return a; // Placeholder
+}
+
+tv64_t __ternary_and_tv64(tv64_t a, tv64_t b)
+{
+    // TODO: Implement for struct type
+    return a; // Placeholder
+}
+
+tv64_t __ternary_or_tv64(tv64_t a, tv64_t b)
+{
+    // TODO: Implement for struct type
+    return a; // Placeholder
+}
+
+tv64_t __ternary_xor_tv64(tv64_t a, tv64_t b)
+{
+    // TODO: Implement for struct type
+    return a; // Placeholder
+}
+
+tv64_t __ternary_not_tv64(tv64_t a)
+{
+    // TODO: Implement for struct type
+    return a; // Placeholder
+}
+
+tv64_t __ternary_cmp_tv64(tv64_t a, tv64_t b)
+{
+    // TODO: Implement for struct type
+    return a; // Placeholder
+}
+
 #undef DEFINE_TERNARY_TYPE_OPS