Set SourceLocation for begin/end of initlist for hlsl. (#4091)

* Set SourceLocation for begin/end of initlist for hlsl.

* Add VectorInitWithCXXFunctionalCastExpr to mark vector init like float4(a, b, c, d).

Author: python3kgae

tools/clang/include/clang/AST/Expr.h

@@ -3910,6 +3910,13 @@ class InitListExpr : public Expr {
     InitListExprBits.HadArrayRangeDesignator = ARD;
   }
 
+  bool isVectorInitWithCXXFunctionalCastExpr() const {
+    return InitListExprBits.VectorInitWithCXXFunctionalCastExpr != 0;
+  }
+  void sawVectorInitWithCXXFunctionalCastExpr(bool InitWithCast) {
+    InitListExprBits.VectorInitWithCXXFunctionalCastExpr = InitWithCast;
+  }
+
   SourceLocation getLocStart() const LLVM_READONLY;
   SourceLocation getLocEnd() const LLVM_READONLY;
 

tools/clang/include/clang/AST/Stmt.h

@@ -272,6 +272,9 @@ class LLVM_ALIGNAS(LLVM_PTR_SIZE) Stmt {
     /// Whether this initializer list originally had a GNU array-range
     /// designator in it. This is a temporary marker used by CodeGen.
     unsigned HadArrayRangeDesignator : 1;
+    // HLSL Change begin - mark vector init like float4(a,b,c,d).
+    unsigned VectorInitWithCXXFunctionalCastExpr : 1;
+    // HLSL Change end.
   };
 
   class TypeTraitExprBitfields {

tools/clang/lib/AST/Expr.cpp

@@ -1921,6 +1921,7 @@ InitListExpr::InitListExpr(const ASTContext &C, SourceLocation lbraceloc,
     LBraceLoc(lbraceloc), RBraceLoc(rbraceloc), AltForm(nullptr, true)
 {
   sawArrayRangeDesignator(false);
+  sawVectorInitWithCXXFunctionalCastExpr(false); // HLSL change.
   for (unsigned I = 0; I != initExprs.size(); ++I) {
     if (initExprs[I]->isTypeDependent())
       ExprBits.TypeDependent = true;

tools/clang/lib/AST/StmtPrinter.cpp

@@ -1479,7 +1479,8 @@ void StmtPrinter::VisitInitListExpr(InitListExpr* Node) {
     return;
   }
 
-  if (!Policy.LangOpts.HLSL || (Node->getLBraceLoc().isValid() || Node->getRBraceLoc().isValid())) // HLSL Change
+  if (!Policy.LangOpts.HLSL ||
+      !Node->isVectorInitWithCXXFunctionalCastExpr()) // HLSL Change
     OS << "{ "; 
 
   for (unsigned i = 0, e = Node->getNumInits(); i != e; ++i) {
@@ -1490,7 +1491,8 @@ void StmtPrinter::VisitInitListExpr(InitListExpr* Node) {
       OS << "{}";
   }
 
-  if (!Policy.LangOpts.HLSL || (Node->getLBraceLoc().isValid() || Node->getRBraceLoc().isValid())) // HLSL Change
+  if (!Policy.LangOpts.HLSL ||
+      !Node->isVectorInitWithCXXFunctionalCastExpr()) // HLSL Change
     OS << " }";
 }
 

tools/clang/lib/Sema/SemaInit.cpp

@@ -6183,7 +6183,11 @@ InitializationSequence::Perform(Sema &S,
             CK_LValueToRValue, Args[i], /*BasePath=*/0, VK_RValue);
         }
       }
-      CurInit = new (S.getASTContext())InitListExpr(S.getASTContext(), SourceLocation(), Args, SourceLocation());
+      InitListExpr *castInit = new (S.getASTContext())
+          InitListExpr(S.getASTContext(), Kind.getParenRange().getBegin(), Args,
+                       Kind.getParenRange().getEnd());
+      castInit->sawVectorInitWithCXXFunctionalCastExpr(true);
+      CurInit = castInit;
     }
     break;
   }

tools/clang/test/CodeGenSPIRV/spirv.debug.opline.composite.hlsl

@@ -57,7 +57,7 @@ void main() {
   };
 
 // CHECK:                        OpFDiv %float {{%\d+}} %float_2
-// CHECK-NEXT:                   OpLine [[file]] 64 25
+// CHECK-NEXT:                   OpLine [[file]] 64 24
 // CHECK-NEXT:  [[first:%\d+]] = OpCompositeConstruct %v2float {{%\d+}} {{%\d+}}
 // CHECK-NEXT: [[second:%\d+]] = OpCompositeConstruct %v2float {{%\d+}} {{%\d+}}
 // CHECK-NEXT:        {{%\d+}} = OpCompositeConstruct %mat2v2float [[first]] [[second]]
@@ -104,7 +104,7 @@ void main() {
 // CHECK-NEXT: OpConvertFToS %int
   int4 e = {1, 2, bar};
 
-// CHECK:      OpLine [[file]] 111 16
+// CHECK:      OpLine [[file]] 111 15
 // CHECK-NEXT: OpCompositeConstruct %v2float %float_1 %float_2
 // CHECK-NEXT: OpLine [[file]] 111 22
 // CHECK-NEXT: OpCompositeExtract %int