Merge branch 'main' into user/alsepkow/UpdateGitHubActions

Author: alsepkow

.github/workflows/clang-format-checker.yml

@@ -20,10 +20,10 @@ jobs:
 
       - name: Get changed files
         id: changed-files
-        uses: tj-actions/changed-files@v41
+        uses: step-security/changed-files@3dbe17c78367e7d60f00d78ae6781a35be47b4a1 # v45.0.1
         with:
           separator: ","
-          fetch_depth: 100 # Fetches only the last 100 commits
+          skip_initial_fetch: true
 
       - name: "Listed files"
         env:

tools/clang/include/clang/Basic/DiagnosticSemaKinds.td

@@ -7549,6 +7549,8 @@ def err_hlsl_vector_element_index_out_of_bounds: Error<
   "vector element index '%0' is out of bounds">;
 def err_hlsl_vector_member_too_many_positions: Error<
   "more than four positions are referenced in '%0'">;
+def err_hlsl_vector_member_on_long_vector: Error<
+   "invalid swizzle '%0' on vector of over 4 elements.">;
 def err_hlsl_missing_type_specifier : Error< // Patterened after err_missing_type_specifier
   "HLSL requires a type specifier for all declarations">;
 def err_hlsl_multiple_concrete_bases : Error<

tools/clang/lib/SPIRV/SpirvBuilder.cpp

@@ -994,6 +994,8 @@ SpirvInstruction *SpirvBuilder::createEmulatedBitFieldExtract(
     rightShift->setResultType(baseType);
   }
 
+  rightShift->setRValue(true);
+
   return rightShift;
 }
 

tools/clang/lib/Sema/SemaHLSL.cpp

@@ -8643,6 +8643,9 @@ ExprResult HLSLExternalSource::LookupVectorMemberExprForHLSL(
     llvm_unreachable("Unknown VectorMemberAccessError value");
   }
 
+  if (colCount > 4)
+    msg = diag::err_hlsl_vector_member_on_long_vector;
+
   if (msg != 0) {
     m_sema->Diag(MemberLoc, msg) << memberText;
 

tools/clang/test/CodeGenSPIRV/op.struct.access.bitfield.sized.rvalue.hlsl

@@ -0,0 +1,22 @@
+// RUN: %dxc -T cs_6_2 -E main -spirv -fcgl -enable-16bit-types %s | FileCheck %s
+
+struct S1
+{
+  uint16_t a : 8;
+};
+
+S1 foo()
+{
+  return (S1)0;
+}
+
+[numthreads(1, 1, 1)]
+void main() {
+  uint16_t test = foo().a;
+// CHECK: [[ptr:%[0-9]+]] = OpAccessChain %_ptr_Function_ushort %temp_var_S1 %int_0
+// CHECK: [[raw:%[0-9]+]] = OpLoad %ushort [[ptr]]
+// CHECK: [[tmp:%[0-9]+]] = OpShiftLeftLogical %ushort [[raw]] %uint_8
+// CHECK: [[out:%[0-9]+]] = OpShiftRightLogical %ushort [[tmp]] %uint_8
+// CHECK-NOT:               OpLoad %ushort [[out]]
+// CHECK:                   OpStore %test [[out]]
+}

tools/clang/test/SemaHLSL/hlsl/types/invalid-longvec-swizzle.hlsl

@@ -0,0 +1,27 @@
+// RUN: %dxc -Tlib_6_9 -verify %s -DTYPE=float
+// RUN: %dxc -Tlib_6_9 -verify %s -DTYPE=bool
+// RUN: %dxc -Tlib_6_9 -verify %s -DTYPE=uint64_t
+// RUN: %dxc -Tlib_6_9 -verify %s -DTYPE=double
+// RUN: %dxc -Tlib_6_9 -verify %s -enable-16bit-types -DTYPE=float16_t
+// RUN: %dxc -Tlib_6_9 -verify %s -enable-16bit-types -DTYPE=int16_t
+
+export
+vector<double, 3> doit(vector<double, 5> vec5) {
+  vec5.x = 1; // expected-error {{invalid swizzle 'x' on vector of over 4 elements.}}
+  return vec5.xyw; // expected-error {{invalid swizzle 'xyw' on vector of over 4 elements.}}
+}
+
+export
+TYPE arr_to_vec(TYPE arr[5]) {
+
+  TYPE val = (vector<TYPE, 6>(arr, 1)).x; // expected-error {{invalid swizzle 'x' on vector of over 4 elements.}}
+
+  TYPE val2 = ((vector<TYPE, 5>)arr).x; // expected-error {{invalid swizzle 'x' on vector of over 4 elements.}}
+
+  return val;
+}
+
+export TYPE lv_ctor(TYPE s) {
+  TYPE ret = (vector<TYPE,6>(1, 2, 3, 4, 5, s)).x; // expected-error {{invalid swizzle 'x' on vector of over 4 elements.}}
+  return ret;
+}