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alsepkowCopilot
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Trim verbose comments to explain why, not what
Shorten 3 comments in HLOperationLower.cpp that re-described code behavior. Each now explains the underlying reason in 1 line. The TODO(#8314) comment was already concise and left unchanged. Co-authored-by: Copilot <[email protected]>
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Lines changed: 3 additions & 6 deletions

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lib/HLSL/HLOperationLower.cpp

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4358,8 +4358,7 @@ Value *TranslateBufLoad(ResLoadHelper &helper, HLResource::Kind RK,
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const bool isMinPrec = (WidenedTy != Ty);
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const bool is64 = (EltTy->isIntegerTy(64) || EltTy->isDoubleTy());
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const bool isBool = EltTy->isIntegerTy(1);
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// If bool (i1), load from memory-representation (i32),
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// or if 64-bits and typed, load i32 chunks, then reconstruct values.
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// DXIL buffer loads require i32; narrow types are reconverted after load.
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if (isBool || (is64 && isTyped))
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EltTy = Builder.getInt32Ty();
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@@ -4475,7 +4474,7 @@ Value *TranslateBufLoad(ResLoadHelper &helper, HLResource::Kind RK,
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retValNew = Builder.CreateICmpNE(
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retValNew, Constant::getNullValue(retValNew->getType()));
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// Truncate widened min precision loads back to original type.
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// DXIL loads min precision as 32-bit; narrow back to original IR type.
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if (isMinPrec) {
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if (OrigEltTy->isIntegerTy())
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retValNew = Builder.CreateTrunc(retValNew, Ty);
@@ -4603,9 +4602,7 @@ void TranslateStore(DxilResource::Kind RK, Value *handle, Value *val,
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val = Builder.CreateZExt(val, Ty);
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}
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// Widen min precision types to i32/f32 for raw buffer stores.
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// Min precision types have 32-bit alloc size, so the address math and
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// store intrinsic must use 32-bit values to match.
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// Min precision alloc size is 32-bit; widen to match store intrinsic.
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if (opcode == OP::OpCode::RawBufferStore ||
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opcode == OP::OpCode::RawBufferVectorStore) {
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const DataLayout &DL =

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