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11 | 11 | #include <linux/types.h> |
12 | 12 |
|
13 | 13 | #include <libnvme.h> |
| 14 | +#include <libnvme-mi.h> |
| 15 | + |
| 16 | +#include <ccan/endian/endian.h> |
14 | 17 |
|
15 | 18 | #include "logging.h" |
16 | 19 | #include "sighdl.h" |
17 | 20 |
|
| 21 | +struct submit_data { |
| 22 | + struct timeval start; |
| 23 | + struct timeval end; |
| 24 | +}; |
| 25 | + |
18 | 26 | int log_level; |
19 | 27 | static bool dry_run; |
| 28 | +static struct submit_data sb; |
20 | 29 |
|
21 | 30 | int map_log_level(int verbose, bool quiet) |
22 | 31 | { |
@@ -167,3 +176,103 @@ int nvme_submit_passthru64(int fd, unsigned long ioctl_cmd, |
167 | 176 |
|
168 | 177 | return err; |
169 | 178 | } |
| 179 | + |
| 180 | +static void nvme_show_req_admin(const struct nvme_mi_admin_req_hdr *hdr, size_t hdr_len, |
| 181 | + const void *data, size_t data_len) |
| 182 | +{ |
| 183 | + struct nvme_passthru_cmd cmd = { |
| 184 | + .opcode = hdr->opcode, |
| 185 | + .flags = hdr->flags, |
| 186 | + .nsid = le32_to_cpu(hdr->cdw1), |
| 187 | + .cdw2 = le32_to_cpu(hdr->cdw2), |
| 188 | + .cdw3 = le32_to_cpu(hdr->cdw3), |
| 189 | + .addr = (uint64_t)(uintptr_t)data, |
| 190 | + .data_len = data_len, |
| 191 | + .cdw10 = le32_to_cpu(hdr->cdw10), |
| 192 | + .cdw11 = le32_to_cpu(hdr->cdw11), |
| 193 | + .cdw12 = le32_to_cpu(hdr->cdw12), |
| 194 | + .cdw13 = le32_to_cpu(hdr->cdw13), |
| 195 | + .cdw14 = le32_to_cpu(hdr->cdw14), |
| 196 | + .cdw15 = le32_to_cpu(hdr->cdw15), |
| 197 | + }; |
| 198 | + |
| 199 | + nvme_show_common(&cmd); |
| 200 | +} |
| 201 | + |
| 202 | +static void nvme_show_req(__u8 type, const struct nvme_mi_msg_hdr *hdr, size_t hdr_len, |
| 203 | + const void *data, size_t data_len) |
| 204 | +{ |
| 205 | + if (type != NVME_MI_MSGTYPE_NVME) |
| 206 | + return; |
| 207 | + |
| 208 | + switch (hdr->nmp >> 3 & 0xf) { |
| 209 | + case NVME_MI_MT_CONTROL: |
| 210 | + break; |
| 211 | + case NVME_MI_MT_MI: |
| 212 | + break; |
| 213 | + case NVME_MI_MT_ADMIN: |
| 214 | + nvme_show_req_admin((struct nvme_mi_admin_req_hdr *)hdr, hdr_len, data, data_len); |
| 215 | + break; |
| 216 | + case NVME_MI_MT_PCIE: |
| 217 | + break; |
| 218 | + case NVME_MI_MT_AE: |
| 219 | + break; |
| 220 | + default: |
| 221 | + break; |
| 222 | + } |
| 223 | +} |
| 224 | + |
| 225 | +void *nvme_mi_submit_entry(__u8 type, const struct nvme_mi_msg_hdr *hdr, size_t hdr_len, |
| 226 | + const void *data, size_t data_len) |
| 227 | +{ |
| 228 | + memset(&sb, 0, sizeof(sb)); |
| 229 | + |
| 230 | + if (log_level >= LOG_DEBUG) { |
| 231 | + nvme_show_req(type, hdr, hdr_len, data, data_len); |
| 232 | + gettimeofday(&sb.start, NULL); |
| 233 | + } |
| 234 | + |
| 235 | + return &sb; |
| 236 | +} |
| 237 | + |
| 238 | +static void nvme_show_resp_admin(const struct nvme_mi_admin_resp_hdr *hdr, size_t hdr_len, |
| 239 | + const void *data, size_t data_len) |
| 240 | +{ |
| 241 | + printf("result : %08x\n", hdr->cdw0); |
| 242 | + printf("err : %d\n", hdr->status); |
| 243 | +} |
| 244 | + |
| 245 | +static void nvme_show_resp(__u8 type, const struct nvme_mi_msg_hdr *hdr, size_t hdr_len, |
| 246 | + const void *data, size_t data_len) |
| 247 | +{ |
| 248 | + if (type != NVME_MI_MSGTYPE_NVME) |
| 249 | + return; |
| 250 | + |
| 251 | + switch (hdr->nmp >> 3 & 0xf) { |
| 252 | + case NVME_MI_MT_CONTROL: |
| 253 | + break; |
| 254 | + case NVME_MI_MT_MI: |
| 255 | + break; |
| 256 | + case NVME_MI_MT_ADMIN: |
| 257 | + nvme_show_resp_admin((struct nvme_mi_admin_resp_hdr *)hdr, hdr_len, data, data_len); |
| 258 | + break; |
| 259 | + case NVME_MI_MT_PCIE: |
| 260 | + break; |
| 261 | + case NVME_MI_MT_AE: |
| 262 | + break; |
| 263 | + default: |
| 264 | + break; |
| 265 | + } |
| 266 | +} |
| 267 | + |
| 268 | +void nvme_mi_submit_exit(__u8 type, const struct nvme_mi_msg_hdr *hdr, size_t hdr_len, |
| 269 | + const void *data, size_t data_len, void *user_data) |
| 270 | +{ |
| 271 | + struct submit_data *sb = user_data; |
| 272 | + |
| 273 | + if (log_level >= LOG_DEBUG) { |
| 274 | + gettimeofday(&sb->end, NULL); |
| 275 | + nvme_show_resp(type, hdr, hdr_len, data, data_len); |
| 276 | + nvme_show_latency(sb->start, sb->end); |
| 277 | + } |
| 278 | +} |
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