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types: add controller properties enum documentation
All remained enum definitions missed documentation added. Signed-off-by: Tokunori Ikegami <[email protected]>
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‎src/nvme/types.h‎

Lines changed: 177 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -334,6 +334,15 @@ enum nvme_cap {
334334
#define NVME_CAP_NSSS(cap) NVME_GET(cap, CAP_NSSS)
335335
#define NVME_CAP_CRMS(cap) NVME_GET(cap, CAP_CRMS)
336336

337+
/**
338+
* enum nvme_vs - This field indicates the version
339+
* @NVME_VS_TER_SHIFT: Shift amount to get the tertiary version
340+
* @NVME_VS_MNR_SHIFT: Shift amount to get the minor version
341+
* @NVME_VS_MJR_SHIFT: Shift amount to get the major version
342+
* @NVME_VS_TER_MASK: Mask to get the tertiary version
343+
* @NVME_VS_MNR_MASK: Mask to get the minor version
344+
* @NVME_VS_MJR_MASK: Mask to get the major version
345+
*/
337346
enum nvme_vs {
338347
NVME_VS_TER_SHIFT = 0,
339348
NVME_VS_MNR_SHIFT = 8,
@@ -351,6 +360,36 @@ enum nvme_vs {
351360
#define NVME_MINOR(ver) NVME_VS_MNR(ver)
352361
#define NVME_TERTIARY(ver) NVME_VS_TER(ver)
353362

363+
/**
364+
* enum nvme_cc - This field indicates the controller configuration
365+
* @NVME_CC_EN_SHIFT: Shift amount to get the enable
366+
* @NVME_CC_CSS_SHIFT: Shift amount to get the I/O command set selected
367+
* @NVME_CC_MPS_SHIFT: Shift amount to get the memory page size
368+
* @NVME_CC_AMS_SHIFT: Shift amount to get the arbitration mechanism selected
369+
* @NVME_CC_SHN_SHIFT: Shift amount to get the shutdown notification
370+
* @NVME_CC_IOSQES_SHIFT: Shift amount to get the I/O submission queue entry size
371+
* @NVME_CC_IOCQES_SHIFT: Shift amount to get the I/O completion queue entry size
372+
* @NVME_CC_CRIME_SHIFT: Shift amount to get the controller ready independent of media enable
373+
* @NVME_CC_EN_MASK: Mask to get the enable
374+
* @NVME_CC_CSS_MASK: Mask to get the I/O command set selected
375+
* @NVME_CC_MPS_MASK: Mask to get the memory page size
376+
* @NVME_CC_AMS_MASK: Mask to get the arbitration mechanism selected
377+
* @NVME_CC_SHN_MASK: Mask to get the shutdown notification
378+
* @NVME_CC_CRIME_MASK: Mask to get the I/O submission queue entry size
379+
* @NVME_CC_IOSQES_MASK: Mask to get the I/O completion queue entry size
380+
* @NVME_CC_IOCQES_MASK: Mask to get the controller ready independent of media enable
381+
* @NVME_CC_CSS_NVM: NVM command set
382+
* @NVME_CC_CSS_CSI: All supported I/O command sets
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* @NVME_CC_CSS_ADMIN: Admin command set only
384+
* @NVME_CC_AMS_RR: Round robin
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* @NVME_CC_AMS_WRRU: Weighted round robin with urgent priority class
386+
* @NVME_CC_AMS_VS: Vendor specific
387+
* @NVME_CC_SHN_NONE: No notification; no effect
388+
* @NVME_CC_SHN_NORMAL: Normal shutdown notification
389+
* @NVME_CC_SHN_ABRUPT: Abrupt shutdown notification
390+
* @NVME_CC_CRWME: Controller ready with media enable
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* @NVME_CC_CRIME: Controller ready independent of media enable
392+
*/
354393
enum nvme_cc {
355394
NVME_CC_EN_SHIFT = 0,
356395
NVME_CC_CSS_SHIFT = 4,
@@ -435,6 +474,13 @@ enum nvme_csts {
435474
#define NVME_CSTS_PP(csts) NVME_GET(csts, CSTS_PP)
436475
#define NVME_CSTS_ST(csts) NVME_GET(csts, CSTS_ST)
437476

477+
/**
478+
* enum nvme_aqa - This field indicates the admin queue attributes
479+
* @NVME_AQA_ASQS_SHIFT: Shift amount to get the admin submission queue size
480+
* @NVME_AQA_ACQS_SHIFT: Shift amount to get the admin completion queue size
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* @NVME_AQA_ASQS_MASK: Mask to get the admin submission queue size
482+
* @NVME_AQA_ACQS_MASK: Mask to get the admin completion queue size
483+
*/
438484
enum nvme_aqa {
439485
NVME_AQA_ASQS_SHIFT = 0,
440486
NVME_AQA_ACQS_SHIFT = 16,
@@ -445,6 +491,25 @@ enum nvme_aqa {
445491
#define NVME_AQA_ASQS(aqa) NVME_GET(aqa, AQA_ASQS)
446492
#define NVME_AQA_ACQS(aqa) NVME_GET(aqa, AQA_ACQS)
447493

494+
/**
495+
* enum nvme_cmbloc - This field indicates the controller memory buffer location
496+
* @NVME_CMBLOC_BIR_SHIFT: Shift amount to get the base indicator register
497+
* @NVME_CMBLOC_CQMMS_SHIFT: Shift amount to get the CMB queue mixed memory support
498+
* @NVME_CMBLOC_CQPDS_SHIFT: Shift amount to get the CMB queue physically discontiguous support
499+
* @NVME_CMBLOC_CDPLMS_SHIFT: Shift amount to get the CMB data pointer mixed locations support
500+
* @NVME_CMBLOC_CDPCILS_SHIFT: Shift amount to get the CMB data pointer and command independent locations support
501+
* @NVME_CMBLOC_CDMMMS_SHIFT: Shift amount to get the CMB data metadata mixed memory support
502+
* @NVME_CMBLOC_CQDA_SHIFT: Shift amount to get the CMB queue dword alignment
503+
* @NVME_CMBLOC_OFST_SHIFT: Shift amount to get the offset
504+
* @NVME_CMBLOC_BIR_MASK: Mask to get the base indicator register
505+
* @NVME_CMBLOC_CQMMS_MASK: Mask to get the CMB queue mixed memory support
506+
* @NVME_CMBLOC_CQPDS_MASK: Mask to get the CMB queue physically discontiguous support
507+
* @NVME_CMBLOC_CDPLMS_MASK: Mask to get the CMB data pointer mixed locations support
508+
* @NVME_CMBLOC_CDPCILS_MASK: Mask to get the CMB data pointer and command independent locations support
509+
* @NVME_CMBLOC_CDMMMS_MASK: Mask to get the CMB data metadata mixed memory support
510+
* @NVME_CMBLOC_CQDA_MASK: Mask to get the CMB queue dword alignment
511+
* @NVME_CMBLOC_OFST_MASK: Mask to get the offset
512+
*/
448513
enum nvme_cmbloc {
449514
NVME_CMBLOC_BIR_SHIFT = 0,
450515
NVME_CMBLOC_CQMMS_SHIFT = 3,
@@ -473,6 +538,30 @@ enum nvme_cmbloc {
473538
#define NVME_CMBLOC_CQDA(cmbloc) NVME_GET(cmbloc, CMBLOC_CQDA)
474539
#define NVME_CMBLOC_OFST(cmbloc) NVME_GET(cmbloc, CMBLOC_OFST)
475540

541+
/**
542+
* enum nvme_cmbsz - This field indicates the controller memory buffer size
543+
* @NVME_CMBSZ_SQS_SHIFT: Shift amount to get the submission queue support
544+
* @NVME_CMBSZ_CQS_SHIFT: Shift amount to get the completion queue support
545+
* @NVME_CMBSZ_LISTS_SHIFT: Shift amount to get the PLP SGL list support
546+
* @NVME_CMBSZ_RDS_SHIFT: Shift amount to get the read data support
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* @NVME_CMBSZ_WDS_SHIFT: Shift amount to get the write data support
548+
* @NVME_CMBSZ_SZU_SHIFT: Shift amount to get the size units
549+
* @NVME_CMBSZ_SZ_SHIFT: Shift amount to get the size
550+
* @NVME_CMBSZ_SQS_MASK: Mask to get the submission queue support
551+
* @NVME_CMBSZ_CQS_MASK: Mask to get the completion queue support
552+
* @NVME_CMBSZ_LISTS_MASK: Mask to get the PLP SGL list support
553+
* @NVME_CMBSZ_RDS_MASK: Mask to get the read data support
554+
* @NVME_CMBSZ_WDS_MASK: Mask to get the write data support
555+
* @NVME_CMBSZ_SZU_MASK: Mask to get the size units
556+
* @NVME_CMBSZ_SZ_MASK: Mask to get the size
557+
* @NVME_CMBSZ_SZU_4K: 4 KiB
558+
* @NVME_CMBSZ_SZU_64K: 64 KiB
559+
* @NVME_CMBSZ_SZU_1M: 1 MiB
560+
* @NVME_CMBSZ_SZU_16M: 16 MiB
561+
* @NVME_CMBSZ_SZU_256M: 256 MiB
562+
* @NVME_CMBSZ_SZU_4G: 4 GiB
563+
* @NVME_CMBSZ_SZU_64G: 64 GiB
564+
*/
476565
enum nvme_cmbsz {
477566
NVME_CMBSZ_SQS_SHIFT = 0,
478567
NVME_CMBSZ_CQS_SHIFT = 1,
@@ -517,6 +606,19 @@ static inline __u64 nvme_cmb_size(__u32 cmbsz)
517606
(1ULL << (12 + 4 * NVME_CMBSZ_SZU(cmbsz)));
518607
}
519608

609+
/**
610+
* enum nvme_bpinfo - This field indicates the boot partition information
611+
* @NVME_BPINFO_BPSZ_SHIFT: Shift amount to get the boot partition size
612+
* @NVME_BPINFO_BRS_SHIFT: Shift amount to get the boot read status
613+
* @NVME_BPINFO_ABPID_SHIFT: Shift amount to get the active boot partition ID
614+
* @NVME_BPINFO_BPSZ_MASK: Mask to get the boot partition size
615+
* @NVME_BPINFO_BRS_MASK: Mask to get the boot read status
616+
* @NVME_BPINFO_ABPID_MASK: Mask to get the active boot partition ID
617+
* @NVME_BPINFO_BRS_NONE: No boot partition read operation requested
618+
* @NVME_BPINFO_BRS_READ_IN_PROGRESS: Boot partition read in progress
619+
* @NVME_BPINFO_BRS_READ_SUCCESS: Boot partition read completed successfully
620+
* @NVME_BPINFO_BRS_READ_ERROR: Error completing boot partition read
621+
*/
520622
enum nvme_bpinfo {
521623
NVME_BPINFO_BPSZ_SHIFT = 0,
522624
NVME_BPINFO_BRS_SHIFT = 24,
@@ -534,6 +636,15 @@ enum nvme_bpinfo {
534636
#define NVME_BPINFO_BRS(bpinfo) NVME_GET(bpinfo, BPINFO_BRS)
535637
#define NVME_BPINFO_ABPID(bpinfo) NVME_GET(bpinfo, BPINFO_ABPID)
536638

639+
/**
640+
* enum nvme_bprsel - This field indicates the boot partition read select
641+
* @NVME_BPRSEL_BPRSZ_SHIFT: Shift amount to get the boot partition read size
642+
* @NVME_BPRSEL_BPROF_SHIFT: Shift amount to get the boot partition read offset
643+
* @NVME_BPRSEL_BPID_SHIFT: Shift amount to get the boot partition identifier
644+
* @NVME_BPRSEL_BPRSZ_MASK: Mask to get the boot partition read size
645+
* @NVME_BPRSEL_BPROF_MASK: Mask to get the boot partition read offset
646+
* @NVME_BPRSEL_BPID_MASK: Mask to get the boot partition identifier
647+
*/
537648
enum nvme_bprsel {
538649
NVME_BPRSEL_BPRSZ_SHIFT = 0,
539650
NVME_BPRSEL_BPROF_SHIFT = 10,
@@ -547,6 +658,14 @@ enum nvme_bprsel {
547658
#define NVME_BPRSEL_BPROF(bprsel) NVME_GET(bprsel, BPRSEL_BPROF)
548659
#define NVME_BPRSEL_BPID(bprsel) NVME_GET(bprsel, BPRSEL_BPID)
549660

661+
/**
662+
* enum nvme_cmbmsc - This field indicates the controller memory buffer memory space control
663+
* @NVME_CMBMSC_CRE_SHIFT: Shift amount to get the capabilities registers enabled
664+
* @NVME_CMBMSC_CMSE_SHIFT: Shift amount to get the controller memory space enable
665+
* @NVME_CMBMSC_CBA_SHIFT: Shift amount to get the controller base address
666+
* @NVME_CMBMSC_CRE_MASK: Mask to get the capabilities registers enabled
667+
* @NVME_CMBMSC_CMSE_MASK: Mask to get the controller memory space enable
668+
*/
550669
enum nvme_cmbmsc {
551670
NVME_CMBMSC_CRE_SHIFT = 0,
552671
NVME_CMBMSC_CMSE_SHIFT = 1,
@@ -560,6 +679,11 @@ static const __u64 NVME_CMBMSC_CBA_MASK = 0xfffffffffffffull;
560679
#define NVME_CMBMSC_CMSE(cmbmsc) NVME_GET(cmbmsc, CMBMSC_CMSE)
561680
#define NVME_CMBMSC_CBA(cmbmsc) NVME_GET(cmbmsc, CMBMSC_CBA)
562681

682+
/**
683+
* enum nvme_cmbsts - This field indicates the controller memory buffer status
684+
* @NVME_CMBSTS_CBAI_SHIFT: Shift amount to get the controller base address invalid
685+
* @NVME_CMBSTS_CBAI_MASK: Mask to get the controller base address invalid
686+
*/
563687
enum nvme_cmbsts {
564688
NVME_CMBSTS_CBAI_SHIFT = 0,
565689
NVME_CMBSTS_CBAI_MASK = 0x1,
@@ -636,6 +760,13 @@ enum nvme_cmbswtp {
636760
#define NVME_CMBSWTP_CMBSWTU(cmbswtp) NVME_GET(cmbswtp, CMBSWTP_CMBSWTU)
637761
#define NVME_CMBSWTP_CMBSWTV(cmbswtp) NVME_GET(cmbswtp, CMBSWTP_CMBSWTV)
638762

763+
/**
764+
* enum nvme_crto - This field indicates the controller ready timeouts
765+
* @NVME_CRTO_CRWMT_SHIFT: Shift amount to get the controller ready with media timeout
766+
* @NVME_CRTO_CRIMT_SHIFT: Shift amount to get the controller ready independent of media timeout
767+
* @NVME_CRTO_CRWMT_MASK: Mask to get the controller ready with media timeout
768+
* @NVME_CRTO_CRIMT_MASK: Mask to get the controller ready independent of media timeout
769+
*/
639770
enum nvme_crto {
640771
NVME_CRTO_CRWMT_SHIFT = 0,
641772
NVME_CRTO_CRIMT_SHIFT = 16,
@@ -697,13 +828,29 @@ enum nvme_pmrcap {
697828
#define NVME_PMRCAP_CMSS(pmrcap) NVME_GET(pmrcap, PMRCAP_CMSS)
698829
#define NVME_PMRCAP_PMRWMB(pmrcap) NVME_GET(pmrcap, PMRCAP_PMRWMB) /* Deprecated */
699830

831+
/**
832+
* enum nvme_pmrctl - This field indicates the persistent memory region control
833+
* @NVME_PMRCTL_EN_SHIFT: Shift amount to get the enable
834+
* @NVME_PMRCTL_EN_MASK: Mask to get the enable
835+
*/
700836
enum nvme_pmrctl {
701837
NVME_PMRCTL_EN_SHIFT = 0,
702838
NVME_PMRCTL_EN_MASK = 0x1,
703839
};
704840

705841
#define NVME_PMRCTL_EN(pmrctl) NVME_GET(pmrctl, PMRCTL_EN)
706842

843+
/**
844+
* enum nvme_pmrsts - This field indicates the persistent memory region status
845+
* @NVME_PMRSTS_ERR_SHIFT: Shift amount to get the error
846+
* @NVME_PMRSTS_NRDY_SHIFT: Shift amount to get the not ready
847+
* @NVME_PMRSTS_HSTS_SHIFT: Shift amount to get the health status
848+
* @NVME_PMRSTS_CBAI_SHIFT: Shift amount to get the controller base address invalid
849+
* @NVME_PMRSTS_ERR_MASK: Mask to get the error
850+
* @NVME_PMRSTS_NRDY_MASK: Mask to get the not ready
851+
* @NVME_PMRSTS_HSTS_MASK: Mask to get the health status
852+
* @NVME_PMRSTS_CBAI_MASK: Mask to get the controller base address invalid
853+
*/
707854
enum nvme_pmrsts {
708855
NVME_PMRSTS_ERR_SHIFT = 0,
709856
NVME_PMRSTS_NRDY_SHIFT = 8,
@@ -720,6 +867,19 @@ enum nvme_pmrsts {
720867
#define NVME_PMRSTS_HSTS(pmrsts) NVME_GET(pmrsts, PMRSTS_HSTS)
721868
#define NVME_PMRSTS_CBAI(pmrsts) NVME_GET(pmrsts, PMRSTS_CBAI)
722869

870+
/**
871+
* enum nvme_pmrebs - This field indicates the persistent memory region elasticity buffer size
872+
* @NVME_PMREBS_PMRSZU_SHIFT: Shift amount to get the PMR elasticity buffer size units
873+
* @NVME_PMREBS_RBB_SHIFT: Shift amount to get the read bypass behavior
874+
* @NVME_PMREBS_PMRWBZ_SHIFT: Shift amount to get the PMR elasticity buffer size base
875+
* @NVME_PMREBS_PMRSZU_MASK: Mask to get the PMR elasticity buffer size units
876+
* @NVME_PMREBS_RBB_MASK: Mask to get the read bypass behavior
877+
* @NVME_PMREBS_PMRWBZ_MASK: Mask to get the PMR elasticity buffer size base
878+
* @NVME_PMREBS_PMRSZU_B: Bytes
879+
* @NVME_PMREBS_PMRSZU_1K: 1 KiB
880+
* @NVME_PMREBS_PMRSZU_1M: 1 MiB
881+
* @NVME_PMREBS_PMRSZU_1G: 1 GiB
882+
*/
723883
enum nvme_pmrebs {
724884
NVME_PMREBS_PMRSZU_SHIFT = 0,
725885
NVME_PMREBS_RBB_SHIFT = 4,
@@ -750,6 +910,17 @@ static inline __u64 nvme_pmr_size(__u32 pmrebs)
750910
(1ULL << (10 * NVME_PMREBS_PMRSZU(pmrebs)));
751911
}
752912

913+
/**
914+
* enum nvme_pmrswtp - This field indicates the persistent memory region sustained write throughput
915+
* @NVME_PMRSWTP_PMRSWTU_SHIFT: Shift amount to get the PMR sustained write throughput units
916+
* @NVME_PMRSWTP_PMRSWTV_SHIFT: Shift amount to get the PMR sustained write throughput
917+
* @NVME_PMRSWTP_PMRSWTU_MASK: Mask to get the PMR sustained write throughput units
918+
* @NVME_PMRSWTP_PMRSWTV_MASK: Mask to get the PMR sustained write throughput
919+
* @NVME_PMRSWTP_PMRSWTU_BPS: Bytes per second
920+
* @NVME_PMRSWTP_PMRSWTU_KBPS: 1 KiB / s
921+
* @NVME_PMRSWTP_PMRSWTU_MBPS: 1 MiB / s
922+
* @NVME_PMRSWTP_PMRSWTU_GBPS: 1 GiB / s
923+
*/
753924
enum nvme_pmrswtp {
754925
NVME_PMRSWTP_PMRSWTU_SHIFT = 0,
755926
NVME_PMRSWTP_PMRSWTV_SHIFT = 8,
@@ -776,6 +947,12 @@ static inline __u64 nvme_pmr_throughput(__u32 pmrswtp)
776947
(1ULL << (10 * NVME_PMRSWTP_PMRSWTU(pmrswtp)));
777948
}
778949

950+
/**
951+
* enum nvme_pmrmsc - This field indicates the persistent memory region memory space control
952+
* @NVME_PMRMSC_CMSE_SHIFT: Shift amount to get the controller memory space enable
953+
* @NVME_PMRMSC_CBA_SHIFT: Shift amount to get the controller base address
954+
* @NVME_PMRMSC_CMSE_MASK: Mask to get the controller memory space enable
955+
*/
779956
enum nvme_pmrmsc {
780957
NVME_PMRMSC_CMSE_SHIFT = 1,
781958
NVME_PMRMSC_CBA_SHIFT = 12,

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