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Merge pull request #76 from jk-ozlabs/mi
Initial NVMe-MI protocol support
2 parents f603510 + f87fa1c commit bbee294

12 files changed

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‎examples/meson.build‎

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@@ -32,3 +32,10 @@ executable(
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dependencies: libnvme_dep,
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include_directories: [incdir, internal_incdir]
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)
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executable(
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'mi-mctp',
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['mi-mctp.c'],
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dependencies: libnvme_mi_dep,
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include_directories: [incdir, internal_incdir]
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)

‎examples/mi-mctp.c‎

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// SPDX-License-Identifier: LGPL-2.1-or-later
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/**
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* This file is part of libnvme.
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* Copyright (c) 2021 Code Construct Pty Ltd.
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*
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* Authors: Jeremy Kerr <[email protected]>
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*/
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/**
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* mi-mctp: open a MI connection over MCTP, and query controller info
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*/
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#include <assert.h>
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#include <err.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <stddef.h>
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#include <string.h>
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#include <libnvme-mi.h>
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#include <ccan/array_size/array_size.h>
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#include <ccan/endian/endian.h>
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static void show_port_pcie(struct nvme_mi_read_port_info *port)
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{
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printf(" PCIe max payload: 0x%x\n", 0x80 << port->pcie.mps);
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printf(" PCIe link speeds: 0x%02x\n", port->pcie.sls);
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printf(" PCIe current speed: 0x%02x\n", port->pcie.cls);
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printf(" PCIe max link width: 0x%02x\n", port->pcie.mlw);
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printf(" PCIe neg link width: 0x%02x\n", port->pcie.nlw);
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printf(" PCIe port: 0x%02x\n", port->pcie.pn);
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}
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static void show_port_smbus(struct nvme_mi_read_port_info *port)
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{
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printf(" SMBus address: 0x%02x\n", port->smb.vpd_addr);
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printf(" VPD access freq: 0x%02x\n", port->smb.mvpd_freq);
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printf(" MCTP address: 0x%02x\n", port->smb.mme_addr);
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printf(" MCTP access freq: 0x%02x\n", port->smb.mme_freq);
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printf(" NVMe basic management: %s\n",
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(port->smb.nvmebm & 0x1) ? "enabled" : "disabled");
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}
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static struct {
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int typeid;
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const char *name;
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void (*fn)(struct nvme_mi_read_port_info *);
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} port_types[] = {
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{ 0x00, "inactive", NULL },
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{ 0x01, "PCIe", show_port_pcie },
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{ 0x02, "SMBus", show_port_smbus },
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};
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static int show_port(nvme_mi_ep_t ep, int portid)
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{
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void (*show_fn)(struct nvme_mi_read_port_info *);
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struct nvme_mi_read_port_info port;
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const char *typestr;
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int rc;
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rc = nvme_mi_mi_read_mi_data_port(ep, portid, &port);
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if (rc)
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return rc;
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if (port.portt < ARRAY_SIZE(port_types)) {
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show_fn = port_types[port.portt].fn;
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typestr = port_types[port.portt].name;
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} else {
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show_fn = NULL;
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typestr = "INVALID";
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}
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printf(" port %d\n", portid);
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printf(" type %s[%d]\n", typestr, port.portt);
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printf(" MCTP MTU: %d\n", port.mmctptus);
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printf(" MEB size: %d\n", port.meb);
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if (show_fn)
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show_fn(&port);
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return 0;
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}
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int do_info(nvme_mi_ep_t ep)
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{
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struct nvme_mi_nvm_ss_health_status ss_health;
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struct nvme_mi_read_nvm_ss_info ss_info;
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int i, rc;
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rc = nvme_mi_mi_read_mi_data_subsys(ep, &ss_info);
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if (rc) {
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warn("can't perform Read MI Data operation");
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return -1;
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}
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printf("NVMe MI subsys info:\n");
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printf(" num ports: %d\n", ss_info.nump + 1);
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printf(" major ver: %d\n", ss_info.mjr);
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printf(" minor ver: %d\n", ss_info.mnr);
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printf("NVMe MI port info:\n");
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for (i = 0; i <= ss_info.nump; i++)
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show_port(ep, i);
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rc = nvme_mi_mi_subsystem_health_status_poll(ep, true, &ss_health);
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if (rc)
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err(EXIT_FAILURE, "can't perform Health Status Poll operation");
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printf("NVMe MI subsys health:\n");
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printf(" subsystem status: 0x%x\n", ss_health.nss);
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printf(" smart warnings: 0x%x\n", ss_health.sw);
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printf(" composite temp: %d\n", ss_health.ctemp);
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printf(" drive life used: %d%%\n", ss_health.pdlu);
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printf(" controller status: 0x%04x\n", le16_to_cpu(ss_health.pdlu));
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return 0;
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}
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static int show_ctrl(nvme_mi_ep_t ep, uint16_t ctrl_id)
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{
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struct nvme_mi_read_ctrl_info ctrl;
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int rc;
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rc = nvme_mi_mi_read_mi_data_ctrl(ep, ctrl_id, &ctrl);
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if (rc)
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return rc;
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printf(" Controller id: %d\n", ctrl_id);
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printf(" port id: %d\n", ctrl.portid);
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if (ctrl.prii & 0x1) {
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uint16_t bdfn = le16_to_cpu(ctrl.pri);
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printf(" PCIe routing valid\n");
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printf(" PCIe bus: 0x%02x\n", bdfn >> 8);
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printf(" PCIe dev: 0x%02x\n", bdfn >> 3 & 0x1f);
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printf(" PCIe fn : 0x%02x\n", bdfn & 0x7);
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} else {
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printf(" PCIe routing invalid\n");
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}
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printf(" PCI vendor: %04x\n", le16_to_cpu(ctrl.vid));
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printf(" PCI device: %04x\n", le16_to_cpu(ctrl.did));
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printf(" PCI subsys vendor: %04x\n", le16_to_cpu(ctrl.ssvid));
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printf(" PCI subsys device: %04x\n", le16_to_cpu(ctrl.ssvid));
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return 0;
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}
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static int do_controllers(nvme_mi_ep_t ep)
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{
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struct nvme_ctrl_list ctrl_list;
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int rc, i;
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rc = nvme_mi_mi_read_mi_data_ctrl_list(ep, 0, &ctrl_list);
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if (rc) {
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warnx("Can't perform Controller List operation");
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return rc;
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}
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printf("NVMe controller list:\n");
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for (i = 0; i < le16_to_cpu(ctrl_list.num); i++) {
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uint16_t id = le16_to_cpu(ctrl_list.identifier[i]);
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show_ctrl(ep, id);
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}
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return 0;
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}
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static const char *__copy_id_str(const void *field, size_t size,
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char *buf, size_t buf_size)
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{
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assert(size < buf_size);
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strncpy(buf, field, size);
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buf[size] = '\0';
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return buf;
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}
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#define copy_id_str(f,b) __copy_id_str(f, sizeof(f), b, sizeof(b))
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int do_identify(nvme_mi_ep_t ep, int argc, char **argv)
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{
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struct nvme_mi_ctrl *ctrl;
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struct nvme_id_ctrl id;
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uint16_t ctrl_id;
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char buf[41];
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int rc, tmp;
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if (argc != 2) {
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fprintf(stderr, "no controller ID specified\n");
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return -1;
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}
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tmp = atoi(argv[1]);
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if (tmp < 0 || tmp > 0xffff) {
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fprintf(stderr, "invalid controller ID\n");
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return -1;
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}
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ctrl_id = tmp & 0xffff;
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ctrl = nvme_mi_init_ctrl(ep, tmp);
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if (!ctrl) {
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warn("can't create controller");
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return -1;
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}
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/* we only use the fields before rab; just request partial ID data */
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rc = nvme_mi_admin_identify_ctrl_partial(ctrl, &id, 0,
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offsetof(struct nvme_id_ctrl, rab));
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if (rc) {
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warn("can't perform Admin Identify command");
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return -1;
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}
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printf("NVMe Controller %d identify\n", ctrl_id);
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printf(" PCI vendor: %04x\n", le16_to_cpu(id.vid));
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printf(" PCI subsys vendor: %04x\n", le16_to_cpu(id.ssvid));
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printf(" Serial number: %s\n", copy_id_str(id.sn, buf));
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printf(" Model number: %s\n", copy_id_str(id.mn, buf));
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printf(" Firmware rev: %s\n", copy_id_str(id.fr, buf));
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return 0;
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}
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enum action {
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ACTION_INFO,
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ACTION_CONTROLLERS,
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ACTION_IDENTIFY,
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};
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int main(int argc, char **argv)
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{
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enum action action;
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nvme_root_t root;
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nvme_mi_ep_t ep;
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uint8_t eid;
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int rc, net;
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if (argc < 3) {
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fprintf(stderr,
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"usage: %s <net> <eid> [action] [action args]\n",
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argv[0]);
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fprintf(stderr, "where action is:\n"
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" info\n"
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" controllers\n"
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" identify <controller-id>\n");
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return EXIT_FAILURE;
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}
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net = atoi(argv[1]);
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eid = atoi(argv[2]) & 0xff;
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argv += 2;
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argc -= 2;
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if (argc == 1) {
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action = ACTION_INFO;
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} else {
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char *action_str = argv[1];
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argc--;
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argv++;
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if (!strcmp(action_str, "info")) {
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action = ACTION_INFO;
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} else if (!strcmp(action_str, "controllers")) {
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action = ACTION_CONTROLLERS;
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} else if (!strcmp(action_str, "identify")) {
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action = ACTION_IDENTIFY;
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} else {
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fprintf(stderr, "invalid action '%s'\n", action_str);
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return EXIT_FAILURE;
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}
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}
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root = nvme_mi_create_root(stderr, DEFAULT_LOGLEVEL);
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if (!root)
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err(EXIT_FAILURE, "can't create NVMe root");
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ep = nvme_mi_open_mctp(root, net, eid);
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if (!ep)
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err(EXIT_FAILURE, "can't open MCTP endpoint %d:%d", net, eid);
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switch (action) {
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case ACTION_INFO:
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rc = do_info(ep);
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break;
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case ACTION_CONTROLLERS:
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rc = do_controllers(ep);
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break;
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case ACTION_IDENTIFY:
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rc = do_identify(ep, argc, argv);
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break;
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}
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nvme_mi_close(ep);
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nvme_mi_free_root(root);
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return rc ? EXIT_FAILURE : EXIT_SUCCESS;
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}
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‎meson.build‎

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@@ -156,6 +156,14 @@ conf.set10(
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),
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description: 'Is isblank() available?'
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)
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conf.set10(
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'HAVE_LINUX_MCTP_H',
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cc.compiles(
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'''#include <linux/mctp.h>''',
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name: 'linux/mctp.h'
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),
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description: 'Is linux/mctp.h include-able?'
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)
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################################################################################
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substs = configuration_data()

‎src/libnvme-mi.h‎

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// SPDX-License-Identifier: LGPL-2.1-or-later
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/*
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* This file is part of libnvme.
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* Copyright (c) 2021 Code Construct Pty Ltd
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*
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* Authors: Jeremy Kerr <[email protected]>
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*/
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#ifndef _LIBNVME_MI_H
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#define _LIBNVME_MI_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "nvme/types.h"
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#include "nvme/mi.h"
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#include "nvme/log.h"
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#ifdef __cplusplus
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}
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#endif
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#endif /* _LIBNVME_MI_H */

‎src/libnvme-mi.map‎

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LIBNVME_MI_1_1 {
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global:
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nvme_mi_create_root;
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nvme_mi_free_root;
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nvme_mi_init_ctrl;
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nvme_mi_close_ctrl;
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nvme_mi_close;
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nvme_mi_mi_read_mi_data_subsys;
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nvme_mi_mi_read_mi_data_port;
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nvme_mi_mi_read_mi_data_ctrl_list;
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nvme_mi_mi_read_mi_data_ctrl;
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nvme_mi_mi_subsystem_health_status_poll;
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nvme_mi_admin_identify_ctrl;
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nvme_mi_admin_identify_ctrl_partial;
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nvme_mi_admin_identify_ctrl_list;
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nvme_mi_open_mctp;
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local:
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*;
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};

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