@@ -5189,34 +5189,48 @@ struct nvme_mi_nvm_ss_health_status {
51895189};
51905190
51915191/**
5192- * enum nvme_mi_css - Get State Control Primitive Success Response Fields - Control Primitive Specific Response
5192+ * enum nvme_mi_ccs - Get State Control Primitive Success Response Fields - Control Primitive Specific Response
51935193 * @NVME_MI_CCS_RDY: Ready
5194- * @NVME_MI_CSS_CFS : Controller Fatal Status
5195- * @NVME_MI_CSS_SHST : Shutdown Status
5196- * @NVME_MI_CSS_NSSRO : NVM Subsystem Reset Occurred
5197- * @NVME_MI_CSS_CECO : Controller Enable Change Occurred
5198- * @NVME_MI_CSS_NAC : Namespace Attribute Changed
5199- * @NVME_MI_CSS_FA : Firmware Activated
5200- * @NVME_MI_CSS_CSTS : Controller Status Change
5201- * @NVME_MI_CSS_CTEMP : Composite Temperature Change
5202- * @NVME_MI_CSS_PDLU : Percentage Used
5203- * @NVME_MI_CSS_SPARE : Available Spare
5204- * @NVME_MI_CSS_CCWARN : Critical Warning
5205- */
5206- enum nvme_mi_css {
5194+ * @NVME_MI_CCS_CFS : Controller Fatal Status
5195+ * @NVME_MI_CCS_SHST : Shutdown Status
5196+ * @NVME_MI_CCS_NSSRO : NVM Subsystem Reset Occurred
5197+ * @NVME_MI_CCS_CECO : Controller Enable Change Occurred
5198+ * @NVME_MI_CCS_NAC : Namespace Attribute Changed
5199+ * @NVME_MI_CCS_FA : Firmware Activated
5200+ * @NVME_MI_CCS_CSTS : Controller Status Change
5201+ * @NVME_MI_CCS_CTEMP : Composite Temperature Change
5202+ * @NVME_MI_CCS_PDLU : Percentage Used
5203+ * @NVME_MI_CCS_SPARE : Available Spare
5204+ * @NVME_MI_CCS_CCWARN : Critical Warning
5205+ */
5206+ enum nvme_mi_ccs {
52075207 NVME_MI_CCS_RDY = 1 << 0 ,
5208- NVME_MI_CSS_CFS = 1 << 1 ,
5209- NVME_MI_CSS_SHST = 1 << 2 ,
5210- NVME_MI_CSS_NSSRO = 1 << 4 ,
5211- NVME_MI_CSS_CECO = 1 << 5 ,
5212- NVME_MI_CSS_NAC = 1 << 6 ,
5213- NVME_MI_CSS_FA = 1 << 7 ,
5214- NVME_MI_CSS_CSTS = 1 << 8 ,
5215- NVME_MI_CSS_CTEMP = 1 << 9 ,
5216- NVME_MI_CSS_PDLU = 1 << 10 ,
5217- NVME_MI_CSS_SPARE = 1 << 11 ,
5218- NVME_MI_CSS_CCWARN = 1 << 12 ,
5219- };
5208+ NVME_MI_CCS_CFS = 1 << 1 ,
5209+ NVME_MI_CCS_SHST = 1 << 2 ,
5210+ NVME_MI_CCS_NSSRO = 1 << 4 ,
5211+ NVME_MI_CCS_CECO = 1 << 5 ,
5212+ NVME_MI_CCS_NAC = 1 << 6 ,
5213+ NVME_MI_CCS_FA = 1 << 7 ,
5214+ NVME_MI_CCS_CSTS = 1 << 8 ,
5215+ NVME_MI_CCS_CTEMP = 1 << 9 ,
5216+ NVME_MI_CCS_PDLU = 1 << 10 ,
5217+ NVME_MI_CCS_SPARE = 1 << 11 ,
5218+ NVME_MI_CCS_CCWARN = 1 << 12 ,
5219+ };
5220+
5221+ /* backwards compat for old "CCS" definitions */
5222+ #define nvme_mi_css nvme_mi_ccs
5223+ #define NVME_MI_CSS_CFS NVME_MI_CCS_CFS
5224+ #define NVME_MI_CSS_SHST NVME_MI_CCS_SHST
5225+ #define NVME_MI_CSS_NSSRO NVME_MI_CCS_NSSRO
5226+ #define NVME_MI_CSS_CECO NVME_MI_CCS_CECO
5227+ #define NVME_MI_CSS_NAC NVME_MI_CCS_NAC
5228+ #define NVME_MI_CSS_FA NVME_MI_CCS_FA
5229+ #define NVME_MI_CSS_CSTS NVME_MI_CCS_CSTS
5230+ #define NVME_MI_CSS_CTEMP NVME_MI_CCS_CTEMP
5231+ #define NVME_MI_CSS_PDLU NVME_MI_CCS_PDLU
5232+ #define NVME_MI_CSS_SPARE NVME_MI_CCS_SPARE
5233+ #define NVME_MI_CSS_CCWARN NVME_MI_CCS_CCWARN
52205234
52215235/**
52225236 * struct nvme_mi_ctrl_health_status - Controller Health Data Structure (CHDS)
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