@@ -646,21 +646,44 @@ enum nvme_crto {
646646#define NVME_CRTO_CRIMT (crto ) NVME_GET(crto, CRTO_CRIMT)
647647#define NVME_CRTO_CRWMT (crto ) NVME_GET(crto, CRTO_CRWMT)
648648
649+ /**
650+ * enum nvme_pmrcap - This field indicates the persistent memory region capabilities
651+ * @NVME_PMRCAP_RDS_SHIFT: Shift amount to get the read data support
652+ * @NVME_PMRCAP_WDS_SHIFT: Shift amount to get the write data support
653+ * @NVME_PMRCAP_BIR_SHIFT: Shift amount to get the base indicator register
654+ * @NVME_PMRCAP_PMRTU_SHIFT: Shift amount to get the persistent memory region time units
655+ * @NVME_PMRCAP_PMRWBM_SHIFT: Shift amount to get the persistent memory region write barrier mechanisms
656+ * @NVME_PMRCAP_PMRTO_SHIFT: Shift amount to get the persistent memory region timeout
657+ * @NVME_PMRCAP_CMSS_SHIFT: Shift amount to get the controller memory space supported
658+ * @NVME_PMRCAP_PMRWMB_SHIFT: Deprecated shift amount to get the persistent memory region write barrier mechanisms
659+ * @NVME_PMRCAP_RDS_MASK: Mask to get the read data support
660+ * @NVME_PMRCAP_WDS_MASK: Mask to get the write data support
661+ * @NVME_PMRCAP_BIR_MASK: Mask to get the base indicator register
662+ * @NVME_PMRCAP_PMRTU_MASK: Mask to get the persistent memory region time units
663+ * @NVME_PMRCAP_PMRWBM_MASK: Mask to get the persistent memory region write barrier mechanisms
664+ * @NVME_PMRCAP_PMRTO_MASK: Mask to get the persistent memory region timeout
665+ * @NVME_PMRCAP_CMSS_MASK: Mask to get the controller memory space supported
666+ * @NVME_PMRCAP_PMRWMB_MASK: Deprecated mask to get the persistent memory region write barrier mechanisms
667+ * @NVME_PMRCAP_PMRTU_500MS: 500 milliseconds
668+ * @NVME_PMRCAP_PMRTU_60S: minutes
669+ */
649670enum nvme_pmrcap {
650671 NVME_PMRCAP_RDS_SHIFT = 3 ,
651672 NVME_PMRCAP_WDS_SHIFT = 4 ,
652673 NVME_PMRCAP_BIR_SHIFT = 5 ,
653674 NVME_PMRCAP_PMRTU_SHIFT = 8 ,
654- NVME_PMRCAP_PMRWMB_SHIFT = 10 ,
675+ NVME_PMRCAP_PMRWBM_SHIFT = 10 ,
655676 NVME_PMRCAP_PMRTO_SHIFT = 16 ,
656677 NVME_PMRCAP_CMSS_SHIFT = 24 ,
678+ NVME_PMRCAP_PMRWMB_SHIFT = NVME_PMRCAP_PMRWBM_SHIFT , /* Deprecated */
657679 NVME_PMRCAP_RDS_MASK = 0x1 ,
658680 NVME_PMRCAP_WDS_MASK = 0x1 ,
659681 NVME_PMRCAP_BIR_MASK = 0x7 ,
660682 NVME_PMRCAP_PMRTU_MASK = 0x3 ,
661- NVME_PMRCAP_PMRWMB_MASK = 0xf ,
683+ NVME_PMRCAP_PMRWBM_MASK = 0xf ,
662684 NVME_PMRCAP_PMRTO_MASK = 0xff ,
663685 NVME_PMRCAP_CMSS_MASK = 0x1 ,
686+ NVME_PMRCAP_PMRWMB_MASK = NVME_PMRCAP_PMRWBM_MASK , /* Deprecated */
664687 NVME_PMRCAP_PMRTU_500MS = 0 ,
665688 NVME_PMRCAP_PMRTU_60S = 1 ,
666689};
@@ -669,9 +692,10 @@ enum nvme_pmrcap {
669692#define NVME_PMRCAP_WDS (pmrcap ) NVME_GET(pmrcap, PMRCAP_WDS)
670693#define NVME_PMRCAP_BIR (pmrcap ) NVME_GET(pmrcap, PMRCAP_BIR)
671694#define NVME_PMRCAP_PMRTU (pmrcap ) NVME_GET(pmrcap, PMRCAP_PMRTU)
672- #define NVME_PMRCAP_PMRWMB (pmrcap ) NVME_GET(pmrcap, PMRCAP_PMRWMB )
695+ #define NVME_PMRCAP_PMRWBM (pmrcap ) NVME_GET(pmrcap, PMRCAP_PMRWBM )
673696#define NVME_PMRCAP_PMRTO (pmrcap ) NVME_GET(pmrcap, PMRCAP_PMRTO)
674697#define NVME_PMRCAP_CMSS (pmrcap ) NVME_GET(pmrcap, PMRCAP_CMSS)
698+ #define NVME_PMRCAP_PMRWMB (pmrcap ) NVME_GET(pmrcap, PMRCAP_PMRWMB) /* Deprecated */
675699
676700enum nvme_pmrctl {
677701 NVME_PMRCTL_EN_SHIFT = 0 ,
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