diff --git a/.clang-format b/.clang-format index 86c20ee744dec..48405c54ef271 100644 --- a/.clang-format +++ b/.clang-format @@ -722,6 +722,13 @@ ForEachMacros: - 'v4l2_m2m_for_each_src_buf' - 'v4l2_m2m_for_each_src_buf_safe' - 'virtio_device_for_each_vq' + - 'vkms_config_for_each_connector' + - 'vkms_config_for_each_crtc' + - 'vkms_config_for_each_encoder' + - 'vkms_config_for_each_plane' + - 'vkms_config_connector_for_each_possible_encoder' + - 'vkms_config_encoder_for_each_possible_crtc' + - 'vkms_config_plane_for_each_possible_crtc' - 'while_for_each_ftrace_op' - 'workloads__for_each' - 'xa_for_each' diff --git a/.github/workflows/kernel_build.yml b/.github/workflows/kernel_build.yml new file mode 100644 index 0000000000000..cd0f9d145429c --- /dev/null +++ b/.github/workflows/kernel_build.yml @@ -0,0 +1,28 @@ +name: blktests-ci + +on: + pull_request: + +jobs: + build-kernel: + runs-on: ubuntu-latest + steps: + - name: Configure git + run: | + git config --global --add safe.directory '*' + - name: Checkout git + run: | + sudo apt-get install -y libelf-dev + mkdir -p linux + cd linux + git init + git remote add origin https://github.com/${{ github.repository }} + git fetch origin --depth=5 ${{ github.event.pull_request.head.sha }} + git reset --hard ${{ github.event.pull_request.head.sha }} + git log -1 + - name: Build kernel + run: | + cd linux + make defconfig + make -j 8 + diff --git a/.gitignore b/.gitignore index f2f63e47fb886..bf5ee6e01cd42 100644 --- a/.gitignore +++ b/.gitignore @@ -40,6 +40,7 @@ *.o *.o.* *.patch +*.pyc *.rmeta *.rpm *.rsi diff --git a/.mailmap b/.mailmap index a885e2eefc697..9ad98690876af 100644 --- a/.mailmap +++ b/.mailmap @@ -155,6 +155,9 @@ Brian King Brian Silverman Bryan Tan Cai Huoqing +Casey Connolly +Casey Connolly +Casey Connolly Can Guo Carl Huang Carlos Bilbao @@ -511,6 +514,7 @@ Mayuresh Janorkar Md Sadre Alam Miaoqing Pan Michael Buesch +Michael Riesch Michal Simek Michel Dänzer Michel Lespinasse @@ -545,6 +549,8 @@ Naveen N Rao Neeraj Upadhyay Neeraj Upadhyay Neil Armstrong +NeilBrown +NeilBrown Nguyen Anh Quynh Nicholas Piggin Nicholas Piggin @@ -722,6 +728,7 @@ Sven Eckelmann Sven Eckelmann Sven Eckelmann Sven Eckelmann +Sven Peter Takashi YOSHII Tamizh Chelvam Raja Taniya Das diff --git a/.pylintrc b/.pylintrc new file mode 100644 index 0000000000000..30b8ae1659f8a --- /dev/null +++ b/.pylintrc @@ -0,0 +1,2 @@ +[MASTER] +init-hook='import sys; sys.path += ["scripts/lib/kdoc", "scripts/lib/abi"]' diff --git a/CREDITS b/CREDITS index f74d230992d6c..45446ae322ec5 100644 --- a/CREDITS +++ b/CREDITS @@ -2336,7 +2336,7 @@ D: Author of the dialog utility, foundation D: for Menuconfig's lxdialog. N: Christoph Lameter -E: christoph@lameter.com +E: cl@gentwo.org D: Digiboard PC/Xe and PC/Xi, Digiboard EPCA D: NUMA support, Slab allocators, Page migration D: Scalability, Time subsystem diff --git a/Documentation/ABI/stable/sysfs-class-backlight b/Documentation/ABI/stable/sysfs-class-backlight index 6102d6bebdf9a..40b8c46b95b28 100644 --- a/Documentation/ABI/stable/sysfs-class-backlight +++ b/Documentation/ABI/stable/sysfs-class-backlight @@ -26,7 +26,12 @@ Date: March 2006 KernelVersion: 2.6.17 Contact: Richard Purdie Description: - Show the actual brightness by querying the hardware. + Show the actual brightness by querying the hardware. Due + to implementation differences in hardware this may not + match the value in 'brightness'. For example some hardware + may treat blanking differently or have custom power saving + features. Userspace should generally use the values in + 'brightness' to make decisions. Users: HAL What: /sys/class/backlight//max_brightness diff --git a/Documentation/ABI/stable/sysfs-driver-mlxreg-io b/Documentation/ABI/stable/sysfs-driver-mlxreg-io index 2cdfd09123da0..f59461111221c 100644 --- a/Documentation/ABI/stable/sysfs-driver-mlxreg-io +++ b/Documentation/ABI/stable/sysfs-driver-mlxreg-io @@ -715,3 +715,101 @@ Description: This file shows 1 in case the system reset happened due to the switch board. The file is read only. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/global_wp_request +Date: May 2025 +KernelVersion: 6.16 +Contact: Vadim Pasternak +Description: This file when written 1 activates request to allow access to + the write protected flashes. Such request can be performed only + for system equipped with BMC (Board Management Controller), + which can grant access to protected flashes. In case BMC allows + access - it will respond with "global_wp_response". BMC decides + regarding time window of granted access. After granted window is + expired, BMC will change value back to 0. + Default value is 0. + + The file is read/write. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/global_wp_response +Date: May 2025 +KernelVersion: 6.16 +Contact: Vadim Pasternak +Description: This file, when set 1, indicates that access to protected + flashes have been granted to host CPU by BMC. + Default value is 0. + + The file is read only. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/shutdown_unlock +Date: May 2025 +KernelVersion: 6.16 +Contact: Vadim Pasternak +Description: When ASICs are getting overheated, system protection + hardware mechanism enforces system reboot. After system + reboot ASICs come up in locked state. To unlock ASICs, + this file should be written 1 + Default value is 0. + + The file is read/write. + +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/boot_progress +Date: May 2025 +KernelVersion: 6.16 +Contact: Vadim Pasternak +Description: These files show the Data Process Unit board boot progress + state. Valid states are: + - 4 : OS starting. + - 5 : OS running. + - 6 : Low-Power Standby. + + The file is read only. + +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/dpu_id +Date: May 2025 +KernelVersion: 6.16 +Contact: Vadim Pasternak +Description: This file shows hardware Id of Data Process Unit board. + + The file is read only. + +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/reset_aux_pwr_or_reload +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/reset_dpu_thermal +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/reset_from_main_board +Date: May 2025 +KernelVersion: 6.16 +Contact: Vadim Pasternak +Description: These files expose the cause of the most recent reset of the Data + Processing Unit (DPU) board. The possible causes are: + - Power auxiliary outage or power reload. + - Thermal shutdown. + - Reset request from the main board. + Value 1 in file means this is reset cause, 0 - otherwise. Only one of + the above causes could be 1 at the same time, representing only last + reset cause. + + The files are read only. + +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/perst_rst +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/phy_rst +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/tpm_rst +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/usbphy_rst +Date: May 2025 +KernelVersion: 6.16 +Contact: Vadim Pasternak +Description: These files allow to reset hardware components of Data Process + Unit board. Respectively PCI, Ethernet PHY, TPM and USB PHY + resets. + Default values for all the attributes is 1. Writing 0 will + cause reset of the related component. + + The files are read/write. + +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/ufm_upgrade +Date: May 2025 +KernelVersion: 6.16 +Contact: Vadim Pasternak +Description: These files show status of Unified Fabric Manager upgrade. + state. 0 - means upgrade is done, 1 - otherwise. + + The file is read only. diff --git a/Documentation/ABI/testing/configfs-tsm b/Documentation/ABI/testing/configfs-tsm-report similarity index 100% rename from Documentation/ABI/testing/configfs-tsm rename to Documentation/ABI/testing/configfs-tsm-report diff --git a/Documentation/ABI/testing/debugfs-alienware-wmi b/Documentation/ABI/testing/debugfs-alienware-wmi new file mode 100644 index 0000000000000..c7f525d6baac9 --- /dev/null +++ b/Documentation/ABI/testing/debugfs-alienware-wmi @@ -0,0 +1,64 @@ +What: /sys/kernel/debug/alienware-wmi-/system_description +Date: March 2025 +KernelVersion: 6.15 +Contact: Kurt Borja +Description: + This file exposes the raw ``system_description`` number reported + by the WMAX device. + + Only present on devices with the AWCC interface. + + See Documentation/admin-guide/laptops/alienware-wmi.rst for + details. + + RO + +What: /sys/kernel/debug/alienware-wmi-/hwmon_data +Date: March 2025 +KernelVersion: 6.15 +Contact: Kurt Borja +Description: + This file exposes HWMON private data. + + Includes fan sensor count, temperature sensor count, internal + fan IDs and internal temp IDs. + + See Documentation/admin-guide/laptops/alienware-wmi.rst for + details. + + RO + +What: /sys/kernel/debug/alienware-wmi-/pprof_data +Date: March 2025 +KernelVersion: 6.15 +Contact: Kurt Borja +Description: + This file exposes Platform Profile private data. + + Includes internal mapping to platform profiles and thermal + profile IDs. + + See Documentation/admin-guide/laptops/alienware-wmi.rst for + details. + + RO + +What: /sys/kernel/debug/alienware-wmi-/gpio_ctl/total_gpios +Date: May 2025 +KernelVersion: 6.16 +Contact: Kurt Borja +Description: + Total number of GPIO pins reported by the device. + + RO + +What: /sys/kernel/debug/alienware-wmi-/gpio_ctl/pinX +Date: May 2025 +KernelVersion: 6.16 +Contact: Kurt Borja +Description: + This file controls GPIO pin X status. + + See Documentation/wmi/devices/alienware-wmi.rst for details. + + RW diff --git a/Documentation/ABI/testing/debugfs-scmi-raw b/Documentation/ABI/testing/debugfs-scmi-raw index 97678cc9535c3..5847b96b3896e 100644 --- a/Documentation/ABI/testing/debugfs-scmi-raw +++ b/Documentation/ABI/testing/debugfs-scmi-raw @@ -31,6 +31,42 @@ Description: SCMI Raw asynchronous message injection/snooping facility; write (receiving an EOF at each message boundary). Users: Debugging, any userspace test suite +What: /sys/kernel/debug/scmi//raw/message_poll +Date: June 2025 +KernelVersion: 6.16 +Contact: cristian.marussi@arm.com +Description: SCMI Raw message injection/snooping facility using polling mode; + write a complete SCMI command message (header included) in + little-endian binary format to have it sent to the configured + backend SCMI server for instance , using polling mode on + the reception path. (if transport is polling capable) + Any subsequently received response can be read from this same + entry if it arrived within the configured timeout. + Each write to the entry causes one command request to be built + and sent while the replies are read back one message at time + (receiving an EOF at each message boundary). +Users: Debugging, any userspace test suite + +What: /sys/kernel/debug/scmi//raw/message_poll_async +Date: June 2025 +KernelVersion: 6.16 +Contact: cristian.marussi@arm.com +Description: SCMI Raw asynchronous message injection/snooping facility using + polling-mode; write a complete SCMI asynchronous command message + (header included) in little-endian binary format to have it sent + to the configured backend SCMI server for instance , using + polling-mode on the reception path of the immediate part of the + asynchronous command. (if transport is polling capable) + Any subsequently received response can be read from this same + entry if it arrived within the configured timeout. + Any additional delayed response received afterwards can be read + from this same entry too if it arrived within the configured + timeout. + Each write to the entry causes one command request to be built + and sent while the replies are read back one message at time + (receiving an EOF at each message boundary). +Users: Debugging, any userspace test suite + What: /sys/kernel/debug/scmi//raw/errors Date: March 2023 KernelVersion: 6.3 @@ -115,3 +151,58 @@ Description: SCMI Raw asynchronous message injection/snooping facility; write exist only if the transport is configured to have more than one default channel. Users: Debugging, any userspace test suite + + +What: /sys/kernel/debug/scmi//raw/channels//message_poll +Date: June 2025 +KernelVersion: 6.16 +Contact: cristian.marussi@arm.com +Description: SCMI Raw message injection/snooping facility using polling mode; + write a complete SCMI command message (header included) in + little-endian binary format to have it sent to the configured + backend SCMI server for instance through the transport + channel, using polling mode on the reception path. + (if transport is polling capable) + Any subsequently received response can be read from this same + entry if it arrived on channel within the configured + timeout. + Each write to the entry causes one command request to be built + and sent while the replies are read back one message at time + (receiving an EOF at each message boundary). + Channel identifier matches the SCMI protocol number which + has been associated with this transport channel in the DT + description, with base protocol number 0x10 being the default + channel for this instance. + Note that these per-channel entries rooted at <..>/channels + exist only if the transport is configured to have more than + one default channel. +Users: Debugging, any userspace test suite + +What: /sys/kernel/debug/scmi//raw/channels//message_poll_async +Date: June 2025 +KernelVersion: 6.16 +Contact: cristian.marussi@arm.com +Description: SCMI Raw asynchronous message injection/snooping facility using + polling-mode; write a complete SCMI asynchronous command message + (header included) in little-endian binary format to have it sent + to the configured backend SCMI server for instance through + the transport channel, using polling mode on the reception + path of the immediate part of the asynchronous command. + (if transport is polling capable) + Any subsequently received response can be read from this same + entry if it arrived on channel within the configured + timeout. + Any additional delayed response received afterwards can be read + from this same entry too if it arrived within the configured + timeout. + Each write to the entry causes one command request to be built + and sent while the replies are read back one message at time + (receiving an EOF at each message boundary). + Channel identifier matches the SCMI protocol number which + has been associated with this transport channel in the DT + description, with base protocol number 0x10 being the default + channel for this instance. + Note that these per-channel entries rooted at <..>/channels + exist only if the transport is configured to have more than + one default channel. +Users: Debugging, any userspace test suite diff --git a/Documentation/ABI/testing/debugfs-turris-mox-rwtm b/Documentation/ABI/testing/debugfs-turris-mox-rwtm deleted file mode 100644 index 813987d5de4e9..0000000000000 --- a/Documentation/ABI/testing/debugfs-turris-mox-rwtm +++ /dev/null @@ -1,14 +0,0 @@ -What: /sys/kernel/debug/turris-mox-rwtm/do_sign -Date: Jun 2020 -KernelVersion: 5.8 -Contact: Marek Behún -Description: - - ======= =========================================================== - (Write) Message to sign with the ECDSA private key stored in - device's OTP. The message must be exactly 64 bytes - (since this is intended for SHA-512 hashes). - (Read) The resulting signature, 136 bytes. This contains the - R and S values of the ECDSA signature, both in - big-endian format. - ======= =========================================================== diff --git a/Documentation/ABI/testing/sysfs-bus-wmi b/Documentation/ABI/testing/sysfs-bus-wmi index aadb35b821982..d71a219c610e5 100644 --- a/Documentation/ABI/testing/sysfs-bus-wmi +++ b/Documentation/ABI/testing/sysfs-bus-wmi @@ -76,6 +76,6 @@ Date: May 2017 Contact: Darren Hart (VMware) Description: This file contains a boolean flags signaling the data block - aassociated with the given WMI device is writable. If the + associated with the given WMI device is writable. If the given WMI device is not associated with a data block, then this file will not exist. diff --git a/Documentation/ABI/testing/sysfs-class-power b/Documentation/ABI/testing/sysfs-class-power index 2a5c1a09a28f9..87a058e14e7ed 100644 --- a/Documentation/ABI/testing/sysfs-class-power +++ b/Documentation/ABI/testing/sysfs-class-power @@ -456,7 +456,7 @@ Description: "Over voltage", "Under voltage", "Unspecified failure", "Cold", "Watchdog timer expire", "Safety timer expire", "Over current", "Calibration required", "Warm", - "Cool", "Hot", "No battery" + "Cool", "Hot", "No battery", "Blown fuse", "Cell imbalance" What: /sys/class/power_supply//precharge_current Date: June 2017 @@ -508,11 +508,12 @@ Description: Access: Read, Write Valid values: - ================ ==================================== - auto: Charge normally, respect thresholds - inhibit-charge: Do not charge while AC is attached - force-discharge: Force discharge while AC is attached - ================ ==================================== + ===================== ======================================== + auto: Charge normally, respect thresholds + inhibit-charge: Do not charge while AC is attached + inhibit-charge-awake: inhibit-charge only when device is awake + force-discharge: Force discharge while AC is attached + ===================== ======================================== What: /sys/class/power_supply//technology Date: May 2007 @@ -822,3 +823,46 @@ Description: Each entry is a link to the device which registered the extension. Access: Read + +What: /sys/class/power_supply/max8971-charger/fast_charge_timer +Date: May 2025 +KernelVersion: 6.15.0 +Contact: Svyatoslav Ryhel +Description: + This entry shows and sets the maximum time the max8971 + charger operates in fast-charge mode. When the timer expires + the device will terminate fast-charge mode (charging current + will drop to 0 A) and will trigger interrupt. + + Valid values: + + - 4 - 10 (hours), step by 1 + - 0: disabled. + +What: /sys/class/power_supply/max8971-charger/top_off_threshold_current +Date: May 2025 +KernelVersion: 6.15.0 +Contact: Svyatoslav Ryhel +Description: + This entry shows and sets the charging current threshold for + entering top-off charging mode. When charging current in fast + charge mode drops below this value, the charger will trigger + interrupt and start top-off charging mode. + + Valid values: + + - 50000 - 200000 (microamps), step by 50000 (rounded down) + +What: /sys/class/power_supply/max8971-charger/top_off_timer +Date: May 2025 +KernelVersion: 6.15.0 +Contact: Svyatoslav Ryhel +Description: + This entry shows and sets the maximum time the max8971 + charger operates in top-off charge mode. When the timer expires + the device will terminate top-off charge mode (charging current + will drop to 0 A) and will trigger interrupt. + + Valid values: + + - 0 - 70 (minutes), step by 10 (rounded down) diff --git a/Documentation/ABI/testing/sysfs-class-power-gaokun b/Documentation/ABI/testing/sysfs-class-power-gaokun new file mode 100644 index 0000000000000..0633aed7b3557 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-class-power-gaokun @@ -0,0 +1,27 @@ +What: /sys/class/power_supply/gaokun-ec-battery/smart_charge_delay +Date: March 2025 +KernelVersion: 6.15 +Contact: Pengyu Luo +Description: + This entry allows configuration of smart charging delay. + + Smart charging behavior: when the power adapter is connected + for delay hours, battery charging will follow the rules of + charge_control_start_threshold and charge_control_end_threshold. + For more information about charge control, please refer to + sysfs-class-power. + + Access: Read, Write + + Valid values: In hours (non-negative) + +What: /sys/class/power_supply/gaokun-ec-battery/battery_adaptive_charge +Date: March 2025 +KernelVersion: 6.15 +Contact: Pengyu Luo +Description: + This entry allows enabling battery adaptive charging. + + Access: Read, Write + + Valid values: 0 (disabled) or 1 (enabled) diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu index 7772d4f034d26..bf85f4de6862b 100644 --- a/Documentation/ABI/testing/sysfs-devices-system-cpu +++ b/Documentation/ABI/testing/sysfs-devices-system-cpu @@ -111,6 +111,7 @@ What: /sys/devices/system/cpu/cpuidle/available_governors /sys/devices/system/cpu/cpuidle/current_driver /sys/devices/system/cpu/cpuidle/current_governor /sys/devices/system/cpu/cpuidle/current_governer_ro + /sys/devices/system/cpu/cpuidle/intel_c1_demotion Date: September 2007 Contact: Linux kernel mailing list Description: Discover cpuidle policy and mechanism @@ -132,7 +133,11 @@ Description: Discover cpuidle policy and mechanism current_governor_ro: (RO) displays current idle policy. - See Documentation/admin-guide/pm/cpuidle.rst and + intel_c1_demotion: (RW) enables/disables the C1 demotion + feature on Intel CPUs. + + See Documentation/admin-guide/pm/cpuidle.rst, + Documentation/admin-guide/pm/intel_idle.rst, and Documentation/driver-api/pm/cpuidle.rst for more information. @@ -268,6 +273,60 @@ Description: Discover CPUs in the same CPU frequency coordination domain This file is only present if the acpi-cpufreq or the cppc-cpufreq drivers are in use. +What: /sys/devices/system/cpu/cpuX/cpufreq/auto_select +Date: May 2025 +Contact: linux-pm@vger.kernel.org +Description: Autonomous selection enable + + Read/write interface to control autonomous selection enable + Read returns autonomous selection status: + 0: autonomous selection is disabled + 1: autonomous selection is enabled + + Write 'y' or '1' or 'on' to enable autonomous selection. + Write 'n' or '0' or 'off' to disable autonomous selection. + + This file is only present if the cppc-cpufreq driver is in use. + +What: /sys/devices/system/cpu/cpuX/cpufreq/auto_act_window +Date: May 2025 +Contact: linux-pm@vger.kernel.org +Description: Autonomous activity window + + This file indicates a moving utilization sensitivity window to + the platform's autonomous selection policy. + + Read/write an integer represents autonomous activity window (in + microseconds) from/to this file. The max value to write is + 1270000000 but the max significand is 127. This means that if 128 + is written to this file, 127 will be stored. If the value is + greater than 130, only the first two digits will be saved as + significand. + + Writing a zero value to this file enable the platform to + determine an appropriate Activity Window depending on the workload. + + Writing to this file only has meaning when Autonomous Selection is + enabled. + + This file is only present if the cppc-cpufreq driver is in use. + +What: /sys/devices/system/cpu/cpuX/cpufreq/energy_performance_preference_val +Date: May 2025 +Contact: linux-pm@vger.kernel.org +Description: Energy performance preference + + Read/write an 8-bit integer from/to this file. This file + represents a range of values from 0 (performance preference) to + 0xFF (energy efficiency preference) that influences the rate of + performance increase/decrease and the result of the hardware's + energy efficiency and performance optimization policies. + + Writing to this file only has meaning when Autonomous Selection is + enabled. + + This file is only present if the cppc-cpufreq driver is in use. + What: /sys/devices/system/cpu/cpu*/cache/index3/cache_disable_{0,1} Date: August 2008 @@ -485,6 +544,7 @@ What: /sys/devices/system/cpu/cpuX/regs/ /sys/devices/system/cpu/cpuX/regs/identification/ /sys/devices/system/cpu/cpuX/regs/identification/midr_el1 /sys/devices/system/cpu/cpuX/regs/identification/revidr_el1 + /sys/devices/system/cpu/cpuX/regs/identification/aidr_el1 /sys/devices/system/cpu/cpuX/regs/identification/smidr_el1 Date: June 2016 Contact: Linux ARM Kernel Mailing list diff --git a/Documentation/ABI/testing/sysfs-devices-virtual-misc-tdx_guest b/Documentation/ABI/testing/sysfs-devices-virtual-misc-tdx_guest new file mode 100644 index 0000000000000..8fca56c8c9dfe --- /dev/null +++ b/Documentation/ABI/testing/sysfs-devices-virtual-misc-tdx_guest @@ -0,0 +1,63 @@ +What: /sys/devices/virtual/misc/tdx_guest/measurements/MRNAME[:HASH] +Date: April, 2025 +KernelVersion: v6.16 +Contact: linux-coco@lists.linux.dev +Description: + Value of a TDX measurement register (MR). MRNAME and HASH above + are placeholders. The optional suffix :HASH is used for MRs + that have associated hash algorithms. See below for a complete + list of TDX MRs exposed via sysfs. Refer to Intel TDX Module + ABI Specification for the definition of TDREPORT and the full + list of TDX measurements. + + Intel TDX Module ABI Specification can be found at: + https://www.intel.com/content/www/us/en/developer/tools/trust-domain-extensions/documentation.html#architecture + + See also: + https://docs.kernel.org/driver-api/coco/measurement-registers.html + +What: /sys/devices/virtual/misc/tdx_guest/measurements/mrconfigid +Date: April, 2025 +KernelVersion: v6.16 +Contact: linux-coco@lists.linux.dev +Description: + (RO) MRCONFIGID - 48-byte immutable storage typically used for + software-defined ID for non-owner-defined configuration of the + guest TD – e.g., run-time or OS configuration. + +What: /sys/devices/virtual/misc/tdx_guest/measurements/mrowner +Date: April, 2025 +KernelVersion: v6.16 +Contact: linux-coco@lists.linux.dev +Description: + (RO) MROWNER - 48-byte immutable storage typically used for + software-defined ID for the guest TD’s owner. + +What: /sys/devices/virtual/misc/tdx_guest/measurements/mrownerconfig +Date: April, 2025 +KernelVersion: v6.16 +Contact: linux-coco@lists.linux.dev +Description: + (RO) MROWNERCONFIG - 48-byte immutable storage typically used + for software-defined ID for owner-defined configuration of the + guest TD – e.g., specific to the workload rather than the + run-time or OS. + +What: /sys/devices/virtual/misc/tdx_guest/measurements/mrtd:sha384 +Date: April, 2025 +KernelVersion: v6.16 +Contact: linux-coco@lists.linux.dev +Description: + (RO) MRTD - Measurement of the initial contents of the TD. + +What: /sys/devices/virtual/misc/tdx_guest/measurements/rtmr[0123]:sha384 +Date: April, 2025 +KernelVersion: v6.16 +Contact: linux-coco@lists.linux.dev +Description: + (RW) RTMR[0123] - 4 Run-Time extendable Measurement Registers. + Read from any of these returns the current value of the + corresponding RTMR. Write extends the written buffer to the + RTMR. All writes must start at offset 0 and be 48 bytes in + size. Partial writes will result in EINVAL returned by the + write() syscall. diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon index cb207c79680d9..4ca917ac6382d 100644 --- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon +++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon @@ -124,3 +124,27 @@ Contact: intel-xe@lists.freedesktop.org Description: RO. VRAM temperature in millidegree Celsius. Only supported for particular Intel Xe graphics platforms. + +What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon/fan1_input +Date: March 2025 +KernelVersion: 6.16 +Contact: intel-xe@lists.freedesktop.org +Description: RO. Fan 1 speed in RPM. + + Only supported for particular Intel Xe graphics platforms. + +What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon/fan2_input +Date: March 2025 +KernelVersion: 6.16 +Contact: intel-xe@lists.freedesktop.org +Description: RO. Fan 2 speed in RPM. + + Only supported for particular Intel Xe graphics platforms. + +What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon/fan3_input +Date: March 2025 +KernelVersion: 6.16 +Contact: intel-xe@lists.freedesktop.org +Description: RO. Fan 3 speed in RPM. + + Only supported for particular Intel Xe graphics platforms. diff --git a/Documentation/ABI/testing/sysfs-driver-ufs b/Documentation/ABI/testing/sysfs-driver-ufs index e36d2de16cbda..d4140dc6c5ba2 100644 --- a/Documentation/ABI/testing/sysfs-driver-ufs +++ b/Documentation/ABI/testing/sysfs-driver-ufs @@ -1636,3 +1636,52 @@ Description: attribute value. The attribute is read only. + +What: /sys/bus/platform/drivers/ufshcd/*/wb_resize_enable +What: /sys/bus/platform/devices/*.ufs/wb_resize_enable +Date: April 2025 +Contact: Huan Tang +Description: + The host can enable the WriteBooster buffer resize by setting this + attribute. + + ======== ====================================== + idle There is no resize operation + decrease Decrease WriteBooster buffer size + increase Increase WriteBooster buffer size + ======== ====================================== + + The file is write only. + +What: /sys/bus/platform/drivers/ufshcd/*/attributes/wb_resize_hint +What: /sys/bus/platform/devices/*.ufs/attributes/wb_resize_hint +Date: April 2025 +Contact: Huan Tang +Description: + wb_resize_hint indicates hint information about which type of resize + for WriteBooster buffer is recommended by the device. + + ========= ====================================== + keep Recommend keep the buffer size + decrease Recommend to decrease the buffer size + increase Recommend to increase the buffer size + ========= ====================================== + + The file is read only. + +What: /sys/bus/platform/drivers/ufshcd/*/attributes/wb_resize_status +What: /sys/bus/platform/devices/*.ufs/attributes/wb_resize_status +Date: April 2025 +Contact: Huan Tang +Description: + The host can check the resize operation status of the WriteBooster + buffer by reading this attribute. + + ================ ======================================== + idle Resize operation is not issued + in_progress Resize operation in progress + complete_success Resize operation completed successfully + general_failure Resize operation general failure + ================ ======================================== + + The file is read only. diff --git a/Documentation/ABI/testing/sysfs-firmware-acpi b/Documentation/ABI/testing/sysfs-firmware-acpi index 5249ad5a96d98..f4de60c4134d4 100644 --- a/Documentation/ABI/testing/sysfs-firmware-acpi +++ b/Documentation/ABI/testing/sysfs-firmware-acpi @@ -248,3 +248,24 @@ Description: # cat ff_pwr_btn 7 enabled +What: /sys/firmware/acpi/memory_ranges/rangeX +Date: February 2025 +Contact: Tony Luck +Description: + On systems with the ACPI MRRM table reports the parameters for + each range. + + base: Starting system physical address. + + length: Length of this range in bytes. + + node: NUMA node that this range belongs to. Negative numbers + indicate that the node number could not be determined (e.g + for an address range that is reserved for future hot add of + memory). + + local_region_id: ID associated with access by agents + local to this range of addresses. + + remote_region_id: ID associated with access by agents + non-local to this range of addresses. diff --git a/Documentation/ABI/testing/sysfs-firmware-turris-mox-rwtm b/Documentation/ABI/testing/sysfs-firmware-turris-mox-rwtm index ea5e5b489bc77..26741cb845043 100644 --- a/Documentation/ABI/testing/sysfs-firmware-turris-mox-rwtm +++ b/Documentation/ABI/testing/sysfs-firmware-turris-mox-rwtm @@ -12,15 +12,6 @@ Contact: Marek Behún Description: (Read) MAC addresses burned into eFuses of this Turris Mox board. Format: %pM -What: /sys/firmware/turris-mox-rwtm/pubkey -Date: August 2019 -KernelVersion: 5.4 -Contact: Marek Behún -Description: (Read) ECDSA public key (in pubkey hex compressed form) computed - as pair to the ECDSA private key burned into eFuses of this - Turris Mox Board. - Format: string - What: /sys/firmware/turris-mox-rwtm/ram_size Date: August 2019 KernelVersion: 5.4 diff --git a/Documentation/ABI/testing/sysfs-fs-f2fs b/Documentation/ABI/testing/sysfs-fs-f2fs index 59adb7dc6f9ef..bf03263b9f468 100644 --- a/Documentation/ABI/testing/sysfs-fs-f2fs +++ b/Documentation/ABI/testing/sysfs-fs-f2fs @@ -270,7 +270,7 @@ Description: Shows all enabled kernel features. inode_checksum, flexible_inline_xattr, quota_ino, inode_crtime, lost_found, verity, sb_checksum, casefold, readonly, compression, test_dummy_encryption_v2, - atomic_write, pin_file, encrypted_casefold. + atomic_write, pin_file, encrypted_casefold, linear_lookup. What: /sys/fs/f2fs//inject_rate Date: May 2016 @@ -710,32 +710,34 @@ Description: Support configuring fault injection type, should be enabled with fault_injection option, fault type value is shown below, it supports single or combined type. - =========================== =========== + =========================== ========== Type_Name Type_Value - =========================== =========== - FAULT_KMALLOC 0x000000001 - FAULT_KVMALLOC 0x000000002 - FAULT_PAGE_ALLOC 0x000000004 - FAULT_PAGE_GET 0x000000008 - FAULT_ALLOC_BIO 0x000000010 (obsolete) - FAULT_ALLOC_NID 0x000000020 - FAULT_ORPHAN 0x000000040 - FAULT_BLOCK 0x000000080 - FAULT_DIR_DEPTH 0x000000100 - FAULT_EVICT_INODE 0x000000200 - FAULT_TRUNCATE 0x000000400 - FAULT_READ_IO 0x000000800 - FAULT_CHECKPOINT 0x000001000 - FAULT_DISCARD 0x000002000 - FAULT_WRITE_IO 0x000004000 - FAULT_SLAB_ALLOC 0x000008000 - FAULT_DQUOT_INIT 0x000010000 - FAULT_LOCK_OP 0x000020000 - FAULT_BLKADDR_VALIDITY 0x000040000 - FAULT_BLKADDR_CONSISTENCE 0x000080000 - FAULT_NO_SEGMENT 0x000100000 - FAULT_INCONSISTENT_FOOTER 0x000200000 - =========================== =========== + =========================== ========== + FAULT_KMALLOC 0x00000001 + FAULT_KVMALLOC 0x00000002 + FAULT_PAGE_ALLOC 0x00000004 + FAULT_PAGE_GET 0x00000008 + FAULT_ALLOC_BIO 0x00000010 (obsolete) + FAULT_ALLOC_NID 0x00000020 + FAULT_ORPHAN 0x00000040 + FAULT_BLOCK 0x00000080 + FAULT_DIR_DEPTH 0x00000100 + FAULT_EVICT_INODE 0x00000200 + FAULT_TRUNCATE 0x00000400 + FAULT_READ_IO 0x00000800 + FAULT_CHECKPOINT 0x00001000 + FAULT_DISCARD 0x00002000 + FAULT_WRITE_IO 0x00004000 + FAULT_SLAB_ALLOC 0x00008000 + FAULT_DQUOT_INIT 0x00010000 + FAULT_LOCK_OP 0x00020000 + FAULT_BLKADDR_VALIDITY 0x00040000 + FAULT_BLKADDR_CONSISTENCE 0x00080000 + FAULT_NO_SEGMENT 0x00100000 + FAULT_INCONSISTENT_FOOTER 0x00200000 + FAULT_TIMEOUT 0x00400000 (1000ms) + FAULT_VMALLOC 0x00800000 + =========================== ========== What: /sys/fs/f2fs//discard_io_aware_gran Date: January 2023 @@ -846,3 +848,16 @@ Description: For several zoned storage devices, vendors will provide extra space reserved_blocks. However, it is not enough, since this extra space should not be shown to users. So, with this new sysfs node, we can hide the space by substracting reserved_blocks from total bytes. + +What: /sys/fs/f2fs//encoding_flags +Date: April 2025 +Contact: "Chao Yu" +Description: This is a read-only entry to show the value of sb.s_encoding_flags, the + value is hexadecimal. + + ============================ ========== + Flag_Name Flag_Value + ============================ ========== + SB_ENC_STRICT_MODE_FL 0x00000001 + SB_ENC_NO_COMPAT_FALLBACK_FL 0x00000002 + ============================ ========== diff --git a/Documentation/ABI/testing/sysfs-kernel-hardlockup_count b/Documentation/ABI/testing/sysfs-kernel-hardlockup_count new file mode 100644 index 0000000000000..dfdd4078b0775 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-kernel-hardlockup_count @@ -0,0 +1,7 @@ +What: /sys/kernel/hardlockup_count +Date: May 2025 +KernelVersion: 6.16 +Contact: Linux kernel mailing list +Description: + Shows how many times the system has detected a hard lockup since last boot. + Available only if CONFIG_HARDLOCKUP_DETECTOR is enabled. diff --git a/Documentation/ABI/testing/sysfs-kernel-mm-damon b/Documentation/ABI/testing/sysfs-kernel-mm-damon index 293197f180ade..5697ab154c1f1 100644 --- a/Documentation/ABI/testing/sysfs-kernel-mm-damon +++ b/Documentation/ABI/testing/sysfs-kernel-mm-damon @@ -283,6 +283,12 @@ Contact: SeongJae Park Description: Writing to and reading from this file sets and gets the current value of the goal metric. +What: /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//quotas/goals//nid +Date: Apr 2025 +Contact: SeongJae Park +Description: Writing to and reading from this file sets and gets the nid + parameter of the goal. + What: /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//quotas/weights/sz_permil Date: Mar 2022 Contact: SeongJae Park diff --git a/Documentation/ABI/testing/sysfs-kernel-mm-mempolicy-weighted-interleave b/Documentation/ABI/testing/sysfs-kernel-mm-mempolicy-weighted-interleave index 0b7972de04e93..649c0e9b895c4 100644 --- a/Documentation/ABI/testing/sysfs-kernel-mm-mempolicy-weighted-interleave +++ b/Documentation/ABI/testing/sysfs-kernel-mm-mempolicy-weighted-interleave @@ -20,6 +20,35 @@ Description: Weight configuration interface for nodeN Minimum weight: 1 Maximum weight: 255 - Writing an empty string or `0` will reset the weight to the - system default. The system default may be set by the kernel - or drivers at boot or during hotplug events. + Writing invalid values (i.e. any values not in [1,255], + empty string, ...) will return -EINVAL. + + Changing the weight to a valid value will automatically + switch the system to manual mode as well. + +What: /sys/kernel/mm/mempolicy/weighted_interleave/auto +Date: May 2025 +Contact: Linux memory management mailing list +Description: Auto-weighting configuration interface + + Configuration mode for weighted interleave. 'true' indicates + that the system is in auto mode, and a 'false' indicates that + the system is in manual mode. + + In auto mode, all node weights are re-calculated and overwritten + (visible via the nodeN interfaces) whenever new bandwidth data + is made available during either boot or hotplug events. + + In manual mode, node weights can only be updated by the user. + Note that nodes that are onlined with previously set weights + will reuse those weights. If they were not previously set or + are onlined with missing bandwidth data, the weights will use + a default weight of 1. + + Writing any true value string (e.g. Y or 1) will enable auto + mode, while writing any false value string (e.g. N or 0) will + enable manual mode. All other strings are ignored and will + return -EINVAL. + + Writing a new weight to a node directly via the nodeN interface + will also automatically switch the system to manual mode. diff --git a/Documentation/ABI/testing/sysfs-kernel-mm-numa b/Documentation/ABI/testing/sysfs-kernel-mm-numa index 77e559d4ed800..90e375ff54cbb 100644 --- a/Documentation/ABI/testing/sysfs-kernel-mm-numa +++ b/Documentation/ABI/testing/sysfs-kernel-mm-numa @@ -16,9 +16,13 @@ Description: Enable/disable demoting pages during reclaim Allowing page migration during reclaim enables these systems to migrate pages from fast tiers to slow tiers when the fast tier is under pressure. This migration - is performed before swap. It may move data to a NUMA - node that does not fall into the cpuset of the - allocating process which might be construed to violate - the guarantees of cpusets. This should not be enabled - on systems which need strict cpuset location - guarantees. + is performed before swap if an eligible numa node is + present in cpuset.mems for the cgroup (or if cpuset v1 + is being used). If cpusets.mems changes at runtime, it + may move data to a NUMA node that does not fall into the + cpuset of the new cpusets.mems, which might be construed + to violate the guarantees of cpusets. Shared memory, + such as libraries, owned by another cgroup may still be + demoted and result in memory use on a node not present + in cpusets.mem. This should not be enabled on systems + which need strict cpuset location guarantees. diff --git a/Documentation/ABI/testing/sysfs-kernel-rcu_stall_count b/Documentation/ABI/testing/sysfs-kernel-rcu_stall_count new file mode 100644 index 0000000000000..a4a97a7f4a4db --- /dev/null +++ b/Documentation/ABI/testing/sysfs-kernel-rcu_stall_count @@ -0,0 +1,6 @@ +What: /sys/kernel/rcu_stall_count +Date: May 2025 +KernelVersion: 6.16 +Contact: Linux kernel mailing list +Description: + Shows how many times the system has detected an RCU stall since last boot. diff --git a/Documentation/ABI/testing/sysfs-kernel-slab b/Documentation/ABI/testing/sysfs-kernel-slab index cd5fb8fa3ddfb..658999be5164c 100644 --- a/Documentation/ABI/testing/sysfs-kernel-slab +++ b/Documentation/ABI/testing/sysfs-kernel-slab @@ -2,7 +2,7 @@ What: /sys/kernel/slab Date: May 2007 KernelVersion: 2.6.22 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The /sys/kernel/slab directory contains a snapshot of the internal state of the SLUB allocator for each cache. Certain @@ -14,7 +14,7 @@ What: /sys/kernel/slab//aliases Date: May 2007 KernelVersion: 2.6.22 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The aliases file is read-only and specifies how many caches have merged into this cache. @@ -23,7 +23,7 @@ What: /sys/kernel/slab//align Date: May 2007 KernelVersion: 2.6.22 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The align file is read-only and specifies the cache's object alignment in bytes. @@ -32,7 +32,7 @@ What: /sys/kernel/slab//alloc_calls Date: May 2007 KernelVersion: 2.6.22 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The alloc_calls file is read-only and lists the kernel code locations from which allocations for this cache were performed. @@ -43,7 +43,7 @@ What: /sys/kernel/slab//alloc_fastpath Date: February 2008 KernelVersion: 2.6.25 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The alloc_fastpath file shows how many objects have been allocated using the fast path. It can be written to clear the @@ -54,7 +54,7 @@ What: /sys/kernel/slab//alloc_from_partial Date: February 2008 KernelVersion: 2.6.25 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The alloc_from_partial file shows how many times a cpu slab has been full and it has been refilled by using a slab from the list @@ -66,7 +66,7 @@ What: /sys/kernel/slab//alloc_refill Date: February 2008 KernelVersion: 2.6.25 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The alloc_refill file shows how many times the per-cpu freelist was empty but there were objects available as the result of @@ -77,7 +77,7 @@ What: /sys/kernel/slab//alloc_slab Date: February 2008 KernelVersion: 2.6.25 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The alloc_slab file is shows how many times a new slab had to be allocated from the page allocator. It can be written to @@ -88,7 +88,7 @@ What: /sys/kernel/slab//alloc_slowpath Date: February 2008 KernelVersion: 2.6.25 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The alloc_slowpath file shows how many objects have been allocated using the slow path because of a refill or @@ -100,7 +100,7 @@ What: /sys/kernel/slab//cache_dma Date: May 2007 KernelVersion: 2.6.22 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The cache_dma file is read-only and specifies whether objects are from ZONE_DMA. @@ -110,7 +110,7 @@ What: /sys/kernel/slab//cpu_slabs Date: May 2007 KernelVersion: 2.6.22 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The cpu_slabs file is read-only and displays how many cpu slabs are active and their NUMA locality. @@ -119,7 +119,7 @@ What: /sys/kernel/slab//cpuslab_flush Date: April 2009 KernelVersion: 2.6.31 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The file cpuslab_flush shows how many times a cache's cpu slabs have been flushed as the result of destroying or shrinking a @@ -132,7 +132,7 @@ What: /sys/kernel/slab//ctor Date: May 2007 KernelVersion: 2.6.22 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The ctor file is read-only and specifies the cache's object constructor function, which is invoked for each object when a @@ -142,7 +142,7 @@ What: /sys/kernel/slab//deactivate_empty Date: February 2008 KernelVersion: 2.6.25 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The deactivate_empty file shows how many times an empty cpu slab was deactivated. It can be written to clear the current count. @@ -152,7 +152,7 @@ What: /sys/kernel/slab//deactivate_full Date: February 2008 KernelVersion: 2.6.25 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The deactivate_full file shows how many times a full cpu slab was deactivated. It can be written to clear the current count. @@ -162,7 +162,7 @@ What: /sys/kernel/slab//deactivate_remote_frees Date: February 2008 KernelVersion: 2.6.25 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The deactivate_remote_frees file shows how many times a cpu slab has been deactivated and contained free objects that were freed @@ -173,7 +173,7 @@ What: /sys/kernel/slab//deactivate_to_head Date: February 2008 KernelVersion: 2.6.25 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The deactivate_to_head file shows how many times a partial cpu slab was deactivated and added to the head of its node's partial @@ -184,7 +184,7 @@ What: /sys/kernel/slab//deactivate_to_tail Date: February 2008 KernelVersion: 2.6.25 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The deactivate_to_tail file shows how many times a partial cpu slab was deactivated and added to the tail of its node's partial @@ -195,7 +195,7 @@ What: /sys/kernel/slab//destroy_by_rcu Date: May 2007 KernelVersion: 2.6.22 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The destroy_by_rcu file is read-only and specifies whether slabs (not objects) are freed by rcu. @@ -204,7 +204,7 @@ What: /sys/kernel/slab//free_add_partial Date: February 2008 KernelVersion: 2.6.25 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The free_add_partial file shows how many times an object has been freed in a full slab so that it had to added to its node's @@ -215,7 +215,7 @@ What: /sys/kernel/slab//free_calls Date: May 2007 KernelVersion: 2.6.22 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The free_calls file is read-only and lists the locations of object frees if slab debugging is enabled (see @@ -225,7 +225,7 @@ What: /sys/kernel/slab//free_fastpath Date: February 2008 KernelVersion: 2.6.25 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The free_fastpath file shows how many objects have been freed using the fast path because it was an object from the cpu slab. @@ -236,7 +236,7 @@ What: /sys/kernel/slab//free_frozen Date: February 2008 KernelVersion: 2.6.25 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The free_frozen file shows how many objects have been freed to a frozen slab (i.e. a remote cpu slab). It can be written to @@ -247,7 +247,7 @@ What: /sys/kernel/slab//free_remove_partial Date: February 2008 KernelVersion: 2.6.25 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The free_remove_partial file shows how many times an object has been freed to a now-empty slab so that it had to be removed from @@ -259,7 +259,7 @@ What: /sys/kernel/slab//free_slab Date: February 2008 KernelVersion: 2.6.25 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The free_slab file shows how many times an empty slab has been freed back to the page allocator. It can be written to clear @@ -270,7 +270,7 @@ What: /sys/kernel/slab//free_slowpath Date: February 2008 KernelVersion: 2.6.25 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The free_slowpath file shows how many objects have been freed using the slow path (i.e. to a full or partial slab). It can @@ -281,7 +281,7 @@ What: /sys/kernel/slab//hwcache_align Date: May 2007 KernelVersion: 2.6.22 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The hwcache_align file is read-only and specifies whether objects are aligned on cachelines. @@ -301,7 +301,7 @@ What: /sys/kernel/slab//object_size Date: May 2007 KernelVersion: 2.6.22 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The object_size file is read-only and specifies the cache's object size. @@ -310,7 +310,7 @@ What: /sys/kernel/slab//objects Date: May 2007 KernelVersion: 2.6.22 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The objects file is read-only and displays how many objects are active and from which nodes they are from. @@ -319,7 +319,7 @@ What: /sys/kernel/slab//objects_partial Date: April 2008 KernelVersion: 2.6.26 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The objects_partial file is read-only and displays how many objects are on partial slabs and from which nodes they are @@ -329,7 +329,7 @@ What: /sys/kernel/slab//objs_per_slab Date: May 2007 KernelVersion: 2.6.22 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The file objs_per_slab is read-only and specifies how many objects may be allocated from a single slab of the order @@ -339,7 +339,7 @@ What: /sys/kernel/slab//order Date: May 2007 KernelVersion: 2.6.22 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The order file specifies the page order at which new slabs are allocated. It is writable and can be changed to increase the @@ -356,7 +356,7 @@ What: /sys/kernel/slab//order_fallback Date: April 2008 KernelVersion: 2.6.26 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The order_fallback file shows how many times an allocation of a new slab has not been possible at the cache's order and instead @@ -369,7 +369,7 @@ What: /sys/kernel/slab//partial Date: May 2007 KernelVersion: 2.6.22 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The partial file is read-only and displays how long many partial slabs there are and how long each node's list is. @@ -378,7 +378,7 @@ What: /sys/kernel/slab//poison Date: May 2007 KernelVersion: 2.6.22 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The poison file specifies whether objects should be poisoned when a new slab is allocated. @@ -387,7 +387,7 @@ What: /sys/kernel/slab//reclaim_account Date: May 2007 KernelVersion: 2.6.22 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The reclaim_account file specifies whether the cache's objects are reclaimable (and grouped by their mobility). @@ -396,7 +396,7 @@ What: /sys/kernel/slab//red_zone Date: May 2007 KernelVersion: 2.6.22 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The red_zone file specifies whether the cache's objects are red zoned. @@ -405,7 +405,7 @@ What: /sys/kernel/slab//remote_node_defrag_ratio Date: January 2008 KernelVersion: 2.6.25 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The file remote_node_defrag_ratio specifies the percentage of times SLUB will attempt to refill the cpu slab with a partial @@ -419,7 +419,7 @@ What: /sys/kernel/slab//sanity_checks Date: May 2007 KernelVersion: 2.6.22 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The sanity_checks file specifies whether expensive checks should be performed on free and, at minimum, enables double free @@ -430,7 +430,7 @@ What: /sys/kernel/slab//shrink Date: May 2007 KernelVersion: 2.6.22 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The shrink file is used to reclaim unused slab cache memory from a cache. Empty per-cpu or partial slabs @@ -446,7 +446,7 @@ What: /sys/kernel/slab//slab_size Date: May 2007 KernelVersion: 2.6.22 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The slab_size file is read-only and specifies the object size with metadata (debugging information and alignment) in bytes. @@ -455,7 +455,7 @@ What: /sys/kernel/slab//slabs Date: May 2007 KernelVersion: 2.6.22 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The slabs file is read-only and displays how long many slabs there are (both cpu and partial) and from which nodes they are @@ -465,7 +465,7 @@ What: /sys/kernel/slab//store_user Date: May 2007 KernelVersion: 2.6.22 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The store_user file specifies whether the location of allocation or free should be tracked for a cache. @@ -474,7 +474,7 @@ What: /sys/kernel/slab//total_objects Date: April 2008 KernelVersion: 2.6.26 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The total_objects file is read-only and displays how many total objects a cache has and from which nodes they are from. @@ -483,7 +483,7 @@ What: /sys/kernel/slab//trace Date: May 2007 KernelVersion: 2.6.22 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: The trace file specifies whether object allocations and frees should be traced. @@ -492,7 +492,7 @@ What: /sys/kernel/slab//validate Date: May 2007 KernelVersion: 2.6.22 Contact: Pekka Enberg , - Christoph Lameter + Christoph Lameter Description: Writing to the validate file causes SLUB to traverse all of its cache's objects and check the validity of metadata. @@ -506,14 +506,14 @@ Description: What: /sys/kernel/slab//slabs_cpu_partial Date: Aug 2011 -Contact: Christoph Lameter +Contact: Christoph Lameter Description: This read-only file shows the number of partialli allocated frozen slabs. What: /sys/kernel/slab//cpu_partial Date: Aug 2011 -Contact: Christoph Lameter +Contact: Christoph Lameter Description: This read-only file shows the number of per cpu partial pages to keep around. diff --git a/Documentation/ABI/testing/sysfs-kernel-softlockup_count b/Documentation/ABI/testing/sysfs-kernel-softlockup_count new file mode 100644 index 0000000000000..337ff5531b5fe --- /dev/null +++ b/Documentation/ABI/testing/sysfs-kernel-softlockup_count @@ -0,0 +1,7 @@ +What: /sys/kernel/softlockup_count +Date: May 2025 +KernelVersion: 6.16 +Contact: Linux kernel mailing list +Description: + Shows how many times the system has detected a soft lockup since last boot. + Available only if CONFIG_SOFTLOCKUP_DETECTOR is enabled. diff --git a/Documentation/ABI/testing/sysfs-platform-alienware-wmi b/Documentation/ABI/testing/sysfs-platform-alienware-wmi new file mode 100644 index 0000000000000..4877b3745f4e5 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-platform-alienware-wmi @@ -0,0 +1,14 @@ +What: /sys/class/hwmon/hwmonX/fanY_boost +Date: March 2025 +KernelVersion: 6.15 +Contact: Kurt Borja +Description: + This file exposes fan boost control for Dell gaming laptops with + the AWCC WMI interface. + + See Documentation/admin-guide/laptops/alienware-wmi.rst for + details. + + Integer value in the range 0 to 255 + + RW diff --git a/Documentation/ABI/testing/sysfs-platform-oxp b/Documentation/ABI/testing/sysfs-platform-oxp new file mode 100644 index 0000000000000..b3f39fc21dfa8 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-platform-oxp @@ -0,0 +1,25 @@ +What: /sys/devices/platform//tt_toggle +Date: Jun 2023 +KernelVersion: 6.5 +Contact: "Antheas Kapenekakis" +Description: + Takeover TDP controls from the device. OneXPlayer devices have a + turbo button that can be used to switch between two TDP modes + (usually 15W and 25W). By setting this attribute to 1, this + functionality is disabled, handing TDP control over to (Windows) + userspace software and the Turbo button turns into a keyboard + shortcut over the AT keyboard of the device. In addition, + using this setting is a prerequisite for PWM control for most + newer models (otherwise it NOOPs). + +What: /sys/devices/platform//tt_led +Date: April 2025 +KernelVersion: 6.16 +Contact: "Antheas Kapenekakis" +Description: + Some OneXPlayer devices (e.g., X1 series) feature a little LED + nested in the Turbo button. This LED is illuminated when the + device is in the higher TDP mode (e.g., 25W). Once tt_toggle + is engaged, this LED is left dangling to its last state. This + attribute allows userspace to control the LED state manually + (either with 1 or 0). Only a subset of devices contain this LED. diff --git a/Documentation/Makefile b/Documentation/Makefile index 63094646df289..d30d66ddf1ada 100644 --- a/Documentation/Makefile +++ b/Documentation/Makefile @@ -60,9 +60,8 @@ endif #HAVE_LATEXMK # Internal variables. PAPEROPT_a4 = -D latex_paper_size=a4 PAPEROPT_letter = -D latex_paper_size=letter -KERNELDOC = $(srctree)/scripts/kernel-doc -KERNELDOC_CONF = -D kerneldoc_srctree=$(srctree) -D kerneldoc_bin=$(KERNELDOC) -ALLSPHINXOPTS = $(KERNELDOC_CONF) $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) +ALLSPHINXOPTS = -D kerneldoc_srctree=$(srctree) -D kerneldoc_bin=$(KERNELDOC) +ALLSPHINXOPTS += $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) ifneq ($(wildcard $(srctree)/.config),) ifeq ($(CONFIG_RUST),y) # Let Sphinx know we will include rustdoc @@ -83,9 +82,11 @@ loop_cmd = $(echo-cmd) $(cmd_$(1)) || exit; # $5 reST source folder relative to $(src), # e.g. "userspace-api/media" for the linux-tv book-set at ./Documentation/userspace-api/media +PYTHONPYCACHEPREFIX ?= $(abspath $(BUILDDIR)/__pycache__) + quiet_cmd_sphinx = SPHINX $@ --> file://$(abspath $(BUILDDIR)/$3/$4) cmd_sphinx = $(MAKE) BUILDDIR=$(abspath $(BUILDDIR)) $(build)=Documentation/userspace-api/media $2 && \ - PYTHONDONTWRITEBYTECODE=1 \ + PYTHONPYCACHEPREFIX="$(PYTHONPYCACHEPREFIX)" \ BUILDDIR=$(abspath $(BUILDDIR)) SPHINX_CONF=$(abspath $(src)/$5/$(SPHINX_CONF)) \ $(PYTHON3) $(srctree)/scripts/jobserver-exec \ $(CONFIG_SHELL) $(srctree)/Documentation/sphinx/parallel-wrapper.sh \ diff --git a/Documentation/admin-guide/LSM/ipe.rst b/Documentation/admin-guide/LSM/ipe.rst index f93a467db628d..dc7088451f9d9 100644 --- a/Documentation/admin-guide/LSM/ipe.rst +++ b/Documentation/admin-guide/LSM/ipe.rst @@ -423,7 +423,7 @@ Field descriptions: Event Example:: - type=1422 audit(1653425529.927:53): policy_name="boot_verified" policy_version=0.0.0 policy_digest=sha256:820EEA5B40CA42B51F68962354BA083122A20BB846F26765076DD8EED7B8F4DB auid=4294967295 ses=4294967295 lsm=ipe res=1 + type=1422 audit(1653425529.927:53): policy_name="boot_verified" policy_version=0.0.0 policy_digest=sha256:820EEA5B40CA42B51F68962354BA083122A20BB846F26765076DD8EED7B8F4DB auid=4294967295 ses=4294967295 lsm=ipe res=1 errno=0 type=1300 audit(1653425529.927:53): arch=c000003e syscall=1 success=yes exit=2567 a0=3 a1=5596fcae1fb0 a2=a07 a3=2 items=0 ppid=184 pid=229 auid=4294967295 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=pts0 ses=4294967295 comm="python3" exe="/usr/bin/python3.10" key=(null) type=1327 audit(1653425529.927:53): PROCTITLE proctitle=707974686F6E3300746573742F6D61696E2E7079002D66002E2E @@ -433,24 +433,55 @@ This record will always be emitted in conjunction with a ``AUDITSYSCALL`` record Field descriptions: -+----------------+------------+-----------+---------------------------------------------------+ -| Field | Value Type | Optional? | Description of Value | -+================+============+===========+===================================================+ -| policy_name | string | No | The policy_name | -+----------------+------------+-----------+---------------------------------------------------+ -| policy_version | string | No | The policy_version | -+----------------+------------+-----------+---------------------------------------------------+ -| policy_digest | string | No | The policy hash | -+----------------+------------+-----------+---------------------------------------------------+ -| auid | integer | No | The login user ID | -+----------------+------------+-----------+---------------------------------------------------+ -| ses | integer | No | The login session ID | -+----------------+------------+-----------+---------------------------------------------------+ -| lsm | string | No | The lsm name associated with the event | -+----------------+------------+-----------+---------------------------------------------------+ -| res | integer | No | The result of the audited operation(success/fail) | -+----------------+------------+-----------+---------------------------------------------------+ - ++----------------+------------+-----------+-------------------------------------------------------------+ +| Field | Value Type | Optional? | Description of Value | ++================+============+===========+=============================================================+ +| policy_name | string | Yes | The policy_name | ++----------------+------------+-----------+-------------------------------------------------------------+ +| policy_version | string | Yes | The policy_version | ++----------------+------------+-----------+-------------------------------------------------------------+ +| policy_digest | string | Yes | The policy hash | ++----------------+------------+-----------+-------------------------------------------------------------+ +| auid | integer | No | The login user ID | ++----------------+------------+-----------+-------------------------------------------------------------+ +| ses | integer | No | The login session ID | ++----------------+------------+-----------+-------------------------------------------------------------+ +| lsm | string | No | The lsm name associated with the event | ++----------------+------------+-----------+-------------------------------------------------------------+ +| res | integer | No | The result of the audited operation(success/fail) | ++----------------+------------+-----------+-------------------------------------------------------------+ +| errno | integer | No | Error code from policy loading operations (see table below) | ++----------------+------------+-----------+-------------------------------------------------------------+ + +Policy error codes (errno): + +The following table lists the error codes that may appear in the errno field while loading or updating the policy: + ++----------------+--------------------------------------------------------+ +| Error Code | Description | ++================+========================================================+ +| 0 | Success | ++----------------+--------------------------------------------------------+ +| -EPERM | Insufficient permission | ++----------------+--------------------------------------------------------+ +| -EEXIST | Same name policy already deployed | ++----------------+--------------------------------------------------------+ +| -EBADMSG | Policy is invalid | ++----------------+--------------------------------------------------------+ +| -ENOMEM | Out of memory (OOM) | ++----------------+--------------------------------------------------------+ +| -ERANGE | Policy version number overflow | ++----------------+--------------------------------------------------------+ +| -EINVAL | Policy version parsing error | ++----------------+--------------------------------------------------------+ +| -ENOKEY | Key used to sign the IPE policy not found in keyring | ++----------------+--------------------------------------------------------+ +| -EKEYREJECTED | Policy signature verification failed | ++----------------+--------------------------------------------------------+ +| -ESTALE | Attempting to update an IPE policy with older version | ++----------------+--------------------------------------------------------+ +| -ENOENT | Policy was deleted while updating | ++----------------+--------------------------------------------------------+ 1404 AUDIT_MAC_STATUS ^^^^^^^^^^^^^^^^^^^^^ diff --git a/Documentation/admin-guide/README.rst b/Documentation/admin-guide/README.rst index 70b02f30013a8..05301f03b717d 100644 --- a/Documentation/admin-guide/README.rst +++ b/Documentation/admin-guide/README.rst @@ -259,7 +259,7 @@ Configuring the kernel Compiling the kernel -------------------- - - Make sure you have at least gcc 5.1 available. + - Make sure you have at least gcc 8.1 available. For more information, refer to :ref:`Documentation/process/changes.rst `. - Do a ``make`` to create a compressed kernel image. It is also possible to do diff --git a/Documentation/admin-guide/blockdev/zram.rst b/Documentation/admin-guide/blockdev/zram.rst index 9bdb30901a930..3e273c1bb749d 100644 --- a/Documentation/admin-guide/blockdev/zram.rst +++ b/Documentation/admin-guide/blockdev/zram.rst @@ -317,6 +317,26 @@ a single line of text and contains the following stats separated by whitespace: Optional Feature ================ +IDLE pages tracking +------------------- + +zram has built-in support for idle pages tracking (that is, allocated but +not used pages). This feature is useful for e.g. zram writeback and +recompression. In order to mark pages as idle, execute the following command:: + + echo all > /sys/block/zramX/idle + +This will mark all allocated zram pages as idle. The idle mark will be +removed only when the page (block) is accessed (e.g. overwritten or freed). +Additionally, when CONFIG_ZRAM_TRACK_ENTRY_ACTIME is enabled, pages can be +marked as idle based on how many seconds have passed since the last access to +a particular zram page:: + + echo 86400 > /sys/block/zramX/idle + +In this example, all pages which haven't been accessed in more than 86400 +seconds (one day) will be marked idle. + writeback --------- @@ -331,24 +351,7 @@ If admin wants to use incompressible page writeback, they could do it via:: echo huge > /sys/block/zramX/writeback -To use idle page writeback, first, user need to declare zram pages -as idle:: - - echo all > /sys/block/zramX/idle - -From now on, any pages on zram are idle pages. The idle mark -will be removed until someone requests access of the block. -IOW, unless there is access request, those pages are still idle pages. -Additionally, when CONFIG_ZRAM_TRACK_ENTRY_ACTIME is enabled pages can be -marked as idle based on how long (in seconds) it's been since they were -last accessed:: - - echo 86400 > /sys/block/zramX/idle - -In this example all pages which haven't been accessed in more than 86400 -seconds (one day) will be marked idle. - -Admin can request writeback of those idle pages at right timing via:: +Admin can request writeback of idle pages at right timing via:: echo idle > /sys/block/zramX/writeback @@ -369,6 +372,23 @@ they could write a page index into the interface:: echo "page_index=1251" > /sys/block/zramX/writeback +In Linux 6.16 this interface underwent some rework. First, the interface +now supports `key=value` format for all of its parameters (`type=huge_idle`, +etc.) Second, the support for `page_indexes` was introduced, which specify +`LOW-HIGH` range (or ranges) of pages to be written-back. This reduces the +number of syscalls, but more importantly this enables optimal post-processing +target selection strategy. Usage example:: + + echo "type=idle" > /sys/block/zramX/writeback + echo "page_indexes=1-100 page_indexes=200-300" > \ + /sys/block/zramX/writeback + +We also now permit multiple page_index params per call and a mix of +single pages and page ranges:: + + echo page_index=42 page_index=99 page_indexes=100-200 \ + page_indexes=500-700 > /sys/block/zramX/writeback + If there are lots of write IO with flash device, potentially, it has flash wearout problem so that admin needs to design write limitation to guarantee storage health for entire product life. @@ -482,8 +502,6 @@ attempt to recompress::: echo "type=huge_idle max_pages=42" > /sys/block/zramX/recompress -Recompression of idle pages requires memory tracking. - During re-compression for every page, that matches re-compression criteria, ZRAM iterates the list of registered alternative compression algorithms in order of their priorities. ZRAM stops either when re-compression was diff --git a/Documentation/admin-guide/bug-hunting.rst b/Documentation/admin-guide/bug-hunting.rst index ce6f4e8ca4876..30858757c9f20 100644 --- a/Documentation/admin-guide/bug-hunting.rst +++ b/Documentation/admin-guide/bug-hunting.rst @@ -196,7 +196,7 @@ will see the assembler code for the routine shown, but if your kernel has debug symbols the C code will also be available. (Debug symbols can be enabled in the kernel hacking menu of the menu configuration.) For example:: - $ objdump -r -S -l --disassemble net/dccp/ipv4.o + $ objdump -r -S -l --disassemble net/ipv4/tcp.o .. note:: diff --git a/Documentation/admin-guide/cgroup-v1/cgroups.rst b/Documentation/admin-guide/cgroup-v1/cgroups.rst index a3e2edb3d2745..463f984533230 100644 --- a/Documentation/admin-guide/cgroup-v1/cgroups.rst +++ b/Documentation/admin-guide/cgroup-v1/cgroups.rst @@ -13,7 +13,7 @@ Portions Copyright (c) 2004-2006 Silicon Graphics, Inc. Modified by Paul Jackson -Modified by Christoph Lameter +Modified by Christoph Lameter .. CONTENTS: diff --git a/Documentation/admin-guide/cgroup-v1/cpusets.rst b/Documentation/admin-guide/cgroup-v1/cpusets.rst index f401af5e2f09a..c7909e5ac1361 100644 --- a/Documentation/admin-guide/cgroup-v1/cpusets.rst +++ b/Documentation/admin-guide/cgroup-v1/cpusets.rst @@ -10,7 +10,7 @@ Written by Simon.Derr@bull.net - Portions Copyright (c) 2004-2006 Silicon Graphics, Inc. - Modified by Paul Jackson -- Modified by Christoph Lameter +- Modified by Christoph Lameter - Modified by Paul Menage - Modified by Hidetoshi Seto diff --git a/Documentation/admin-guide/cgroup-v2.rst b/Documentation/admin-guide/cgroup-v2.rst index 9e7de8e700481..bd98ea3175ec1 100644 --- a/Documentation/admin-guide/cgroup-v2.rst +++ b/Documentation/admin-guide/cgroup-v2.rst @@ -1076,7 +1076,7 @@ cpufreq governor about the minimum desired frequency which should always be provided by a CPU, as well as the maximum desired frequency, which should not be exceeded by a CPU. -WARNING: cgroup2 cpu controller doesn't yet fully support the control of +WARNING: cgroup2 cpu controller doesn't yet support the (bandwidth) control of realtime processes. For a kernel built with the CONFIG_RT_GROUP_SCHED option enabled for group scheduling of realtime processes, the cpu controller can only be enabled when all RT processes are in the root cgroup. Be aware that system @@ -1095,19 +1095,34 @@ realtime processes irrespective of CONFIG_RT_GROUP_SCHED. CPU Interface Files ~~~~~~~~~~~~~~~~~~~ -All time durations are in microseconds. +The interaction of a process with the cpu controller depends on its scheduling +policy and the underlying scheduler. From the point of view of the cpu controller, +processes can be categorized as follows: + +* Processes under the fair-class scheduler +* Processes under a BPF scheduler with the ``cgroup_set_weight`` callback +* Everything else: ``SCHED_{FIFO,RR,DEADLINE}`` and processes under a BPF scheduler + without the ``cgroup_set_weight`` callback + +For details on when a process is under the fair-class scheduler or a BPF scheduler, +check out :ref:`Documentation/scheduler/sched-ext.rst `. + +For each of the following interface files, the above categories +will be referred to. All time durations are in microseconds. cpu.stat A read-only flat-keyed file. This file exists whether the controller is enabled or not. - It always reports the following three stats: + It always reports the following three stats, which account for all the + processes in the cgroup: - usage_usec - user_usec - system_usec - and the following five when the controller is enabled: + and the following five when the controller is enabled, which account for + only the processes under the fair-class scheduler: - nr_periods - nr_throttled @@ -1125,6 +1140,10 @@ All time durations are in microseconds. If the cgroup has been configured to be SCHED_IDLE (cpu.idle = 1), then the weight will show as a 0. + This file affects only processes under the fair-class scheduler and a BPF + scheduler with the ``cgroup_set_weight`` callback depending on what the + callback actually does. + cpu.weight.nice A read-write single value file which exists on non-root cgroups. The default is "0". @@ -1137,6 +1156,10 @@ All time durations are in microseconds. granularity is coarser for the nice values, the read value is the closest approximation of the current weight. + This file affects only processes under the fair-class scheduler and a BPF + scheduler with the ``cgroup_set_weight`` callback depending on what the + callback actually does. + cpu.max A read-write two value file which exists on non-root cgroups. The default is "max 100000". @@ -1149,43 +1172,55 @@ All time durations are in microseconds. $PERIOD duration. "max" for $MAX indicates no limit. If only one number is written, $MAX is updated. + This file affects only processes under the fair-class scheduler. + cpu.max.burst A read-write single value file which exists on non-root cgroups. The default is "0". The burst in the range [0, $MAX]. + This file affects only processes under the fair-class scheduler. + cpu.pressure A read-write nested-keyed file. Shows pressure stall information for CPU. See :ref:`Documentation/accounting/psi.rst ` for details. + This file accounts for all the processes in the cgroup. + cpu.uclamp.min - A read-write single value file which exists on non-root cgroups. - The default is "0", i.e. no utilization boosting. + A read-write single value file which exists on non-root cgroups. + The default is "0", i.e. no utilization boosting. - The requested minimum utilization (protection) as a percentage - rational number, e.g. 12.34 for 12.34%. + The requested minimum utilization (protection) as a percentage + rational number, e.g. 12.34 for 12.34%. - This interface allows reading and setting minimum utilization clamp - values similar to the sched_setattr(2). This minimum utilization - value is used to clamp the task specific minimum utilization clamp. + This interface allows reading and setting minimum utilization clamp + values similar to the sched_setattr(2). This minimum utilization + value is used to clamp the task specific minimum utilization clamp, + including those of realtime processes. - The requested minimum utilization (protection) is always capped by - the current value for the maximum utilization (limit), i.e. - `cpu.uclamp.max`. + The requested minimum utilization (protection) is always capped by + the current value for the maximum utilization (limit), i.e. + `cpu.uclamp.max`. + + This file affects all the processes in the cgroup. cpu.uclamp.max - A read-write single value file which exists on non-root cgroups. - The default is "max". i.e. no utilization capping + A read-write single value file which exists on non-root cgroups. + The default is "max". i.e. no utilization capping + + The requested maximum utilization (limit) as a percentage rational + number, e.g. 98.76 for 98.76%. - The requested maximum utilization (limit) as a percentage rational - number, e.g. 98.76 for 98.76%. + This interface allows reading and setting maximum utilization clamp + values similar to the sched_setattr(2). This maximum utilization + value is used to clamp the task specific maximum utilization clamp, + including those of realtime processes. - This interface allows reading and setting maximum utilization clamp - values similar to the sched_setattr(2). This maximum utilization - value is used to clamp the task specific maximum utilization clamp. + This file affects all the processes in the cgroup. cpu.idle A read-write single value file which exists on non-root cgroups. @@ -1197,7 +1232,7 @@ All time durations are in microseconds. own relative priorities, but the cgroup itself will be treated as very low priority relative to its peers. - + This file affects only processes under the fair-class scheduler. Memory ------ @@ -1299,6 +1334,18 @@ PAGE_SIZE multiple when read back. monitors the limited cgroup to alleviate heavy reclaim pressure. + If memory.high is opened with O_NONBLOCK then the synchronous + reclaim is bypassed. This is useful for admin processes that + need to dynamically adjust the job's memory limits without + expending their own CPU resources on memory reclamation. The + job will trigger the reclaim and/or get throttled on its + next charge request. + + Please note that with O_NONBLOCK, there is a chance that the + target memory cgroup may take indefinite amount of time to + reduce usage below the limit due to delayed charge request or + busy-hitting its memory to slow down reclaim. + memory.max A read-write single value file which exists on non-root cgroups. The default is "max". @@ -1316,6 +1363,18 @@ PAGE_SIZE multiple when read back. Caller could retry them differently, return into userspace as -ENOMEM or silently ignore in cases like disk readahead. + If memory.max is opened with O_NONBLOCK, then the synchronous + reclaim and oom-kill are bypassed. This is useful for admin + processes that need to dynamically adjust the job's memory limits + without expending their own CPU resources on memory reclamation. + The job will trigger the reclaim and/or oom-kill on its next + charge request. + + Please note that with O_NONBLOCK, there is a chance that the + target memory cgroup may take indefinite amount of time to + reduce usage below the limit due to delayed charge request or + busy-hitting its memory to slow down reclaim. + memory.reclaim A write-only nested-keyed file which exists for all cgroups. @@ -1348,6 +1407,9 @@ The following nested keys are defined. same semantics as vm.swappiness applied to memcg reclaim with all the existing limitations and potential future extensions. + The valid range for swappiness is [0-200, max], setting + swappiness=max exclusively reclaims anonymous memory. + memory.peak A read-write single value file which exists on non-root cgroups. diff --git a/Documentation/admin-guide/gpio/gpio-aggregator.rst b/Documentation/admin-guide/gpio/gpio-aggregator.rst index 5cd1e72217565..8374a9df9105d 100644 --- a/Documentation/admin-guide/gpio/gpio-aggregator.rst +++ b/Documentation/admin-guide/gpio/gpio-aggregator.rst @@ -69,6 +69,113 @@ write-only attribute files in sysfs. $ echo gpio-aggregator.0 > delete_device +Aggregating GPIOs using Configfs +-------------------------------- + +**Group:** ``/config/gpio-aggregator`` + + This is the root directory of the gpio-aggregator configfs tree. + +**Group:** ``/config/gpio-aggregator/`` + + This directory represents a GPIO aggregator device. You can assign any + name to ```` (e.g. ``agg0``), except names starting with + ``_sysfs`` prefix, which are reserved for auto-generated configfs + entries corresponding to devices created via Sysfs. + +**Attribute:** ``/config/gpio-aggregator//live`` + + The ``live`` attribute allows to trigger the actual creation of the device + once it's fully configured. Accepted values are: + + * ``1``, ``yes``, ``true`` : enable the virtual device + * ``0``, ``no``, ``false`` : disable the virtual device + +**Attribute:** ``/config/gpio-aggregator//dev_name`` + + The read-only ``dev_name`` attribute exposes the name of the device as it + will appear in the system on the platform bus (e.g. ``gpio-aggregator.0``). + This is useful for identifying a character device for the newly created + aggregator. If it's ``gpio-aggregator.0``, + ``/sys/devices/platform/gpio-aggregator.0/gpiochipX`` path tells you that the + GPIO device id is ``X``. + +You must create subdirectories for each virtual line you want to +instantiate, named exactly as ``line0``, ``line1``, ..., ``lineY``, when +you want to instantiate ``Y+1`` (Y >= 0) lines. Configure all lines before +activating the device by setting ``live`` to 1. + +**Group:** ``/config/gpio-aggregator///`` + + This directory represents a GPIO line to include in the aggregator. + +**Attribute:** ``/config/gpio-aggregator///key`` + +**Attribute:** ``/config/gpio-aggregator///offset`` + + The default values after creating the ```` directory are: + + * ``key`` : + * ``offset`` : -1 + + ``key`` must always be explicitly configured, while ``offset`` depends. + Two configuration patterns exist for each ````: + + (a). For lookup by GPIO line name: + + * Set ``key`` to the line name. + * Ensure ``offset`` remains -1 (the default). + + (b). For lookup by GPIO chip name and the line offset within the chip: + + * Set ``key`` to the chip name. + * Set ``offset`` to the line offset (0 <= ``offset`` < 65535). + +**Attribute:** ``/config/gpio-aggregator///name`` + + The ``name`` attribute sets a custom name for lineY. If left unset, the + line will remain unnamed. + +Once the configuration is done, the ``'live'`` attribute must be set to 1 +in order to instantiate the aggregator device. It can be set back to 0 to +destroy the virtual device. The module will synchronously wait for the new +aggregator device to be successfully probed and if this doesn't happen, writing +to ``'live'`` will result in an error. This is a different behaviour from the +case when you create it using sysfs ``new_device`` interface. + +.. note:: + + For aggregators created via Sysfs, the configfs entries are + auto-generated and appear as ``/config/gpio-aggregator/_sysfs./``. You + cannot add or remove line directories with mkdir(2)/rmdir(2). To modify + lines, you must use the "delete_device" interface to tear down the + existing device and reconfigure it from scratch. However, you can still + toggle the aggregator with the ``live`` attribute and adjust the + ``key``, ``offset``, and ``name`` attributes for each line when ``live`` + is set to 0 by hand (i.e. it's not waiting for deferred probe). + +Sample configuration commands +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. code-block:: sh + + # Create a directory for an aggregator device + $ mkdir /sys/kernel/config/gpio-aggregator/agg0 + + # Configure each line + $ mkdir /sys/kernel/config/gpio-aggregator/agg0/line0 + $ echo gpiochip0 > /sys/kernel/config/gpio-aggregator/agg0/line0/key + $ echo 6 > /sys/kernel/config/gpio-aggregator/agg0/line0/offset + $ echo test0 > /sys/kernel/config/gpio-aggregator/agg0/line0/name + $ mkdir /sys/kernel/config/gpio-aggregator/agg0/line1 + $ echo gpiochip0 > /sys/kernel/config/gpio-aggregator/agg0/line1/key + $ echo 7 > /sys/kernel/config/gpio-aggregator/agg0/line1/offset + $ echo test1 > /sys/kernel/config/gpio-aggregator/agg0/line1/name + + # Activate the aggregator device + $ echo 1 > /sys/kernel/config/gpio-aggregator/agg0/live + + Generic GPIO Driver ------------------- diff --git a/Documentation/admin-guide/kdump/kdump.rst b/Documentation/admin-guide/kdump/kdump.rst index 1f7f14c6e184c..20fabdf6567e1 100644 --- a/Documentation/admin-guide/kdump/kdump.rst +++ b/Documentation/admin-guide/kdump/kdump.rst @@ -547,6 +547,38 @@ from within add_taint() whenever the value set in this bitmask matches with the bit flag being set by add_taint(). This will cause a kdump to occur at the add_taint()->panic() call. +Write the dump file to encrypted disk volume +============================================ + +CONFIG_CRASH_DM_CRYPT can be enabled to support saving the dump file to an +encrypted disk volume (only x86_64 supported for now). User space can interact +with /sys/kernel/config/crash_dm_crypt_keys for setup, + +1. Tell the first kernel what logon keys are needed to unlock the disk volumes, + # Add key #1 + mkdir /sys/kernel/config/crash_dm_crypt_keys/7d26b7b4-e342-4d2d-b660-7426b0996720 + # Add key #1's description + echo cryptsetup:7d26b7b4-e342-4d2d-b660-7426b0996720 > /sys/kernel/config/crash_dm_crypt_keys/description + + # how many keys do we have now? + cat /sys/kernel/config/crash_dm_crypt_keys/count + 1 + + # Add key #2 in the same way + + # how many keys do we have now? + cat /sys/kernel/config/crash_dm_crypt_keys/count + 2 + + # To support CPU/memory hot-plugging, re-use keys already saved to reserved + # memory + echo true > /sys/kernel/config/crash_dm_crypt_key/reuse + +2. Load the dump-capture kernel + +3. After the dump-capture kerne get booted, restore the keys to user keyring + echo yes > /sys/kernel/crash_dm_crypt_keys/restore + Contact ======= diff --git a/Documentation/admin-guide/kdump/vmcoreinfo.rst b/Documentation/admin-guide/kdump/vmcoreinfo.rst index 0f714fc945acf..8cf4614385b7e 100644 --- a/Documentation/admin-guide/kdump/vmcoreinfo.rst +++ b/Documentation/admin-guide/kdump/vmcoreinfo.rst @@ -331,8 +331,8 @@ PG_lru|PG_private|PG_swapcache|PG_swapbacked|PG_slab|PG_hwpoision|PG_head_mask|P Page attributes. These flags are used to filter various unnecessary for dumping pages. -PAGE_BUDDY_MAPCOUNT_VALUE(~PG_buddy)|PAGE_OFFLINE_MAPCOUNT_VALUE(~PG_offline) ------------------------------------------------------------------------------ +PAGE_BUDDY_MAPCOUNT_VALUE(~PG_buddy)|PAGE_OFFLINE_MAPCOUNT_VALUE(~PG_offline)|PAGE_OFFLINE_MAPCOUNT_VALUE(~PG_unaccepted) +------------------------------------------------------------------------------------------------------------------------- More page attributes. These flags are used to filter various unnecessary for dumping pages. diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 1d6d39f4c68d2..a3ea40b22fb9a 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1828,6 +1828,13 @@ lz4: Select LZ4 compression algorithm to compress/decompress hibernation image. + hibernate.pm_test_delay= + [HIBERNATION] + Sets the number of seconds to remain in a hibernation test + mode before resuming the system (see + /sys/power/pm_test). Only available when CONFIG_PM_DEBUG + is set. Default value is 5. + highmem=nn[KMG] [KNL,BOOT,EARLY] forces the highmem zone to have an exact size of . This works even on boxes that have no highmem otherwise. This also works to reduce highmem @@ -2742,6 +2749,31 @@ kgdbwait [KGDB,EARLY] Stop kernel execution and enter the kernel debugger at the earliest opportunity. + kho= [KEXEC,EARLY] + Format: { "0" | "1" | "off" | "on" | "y" | "n" } + Enables or disables Kexec HandOver. + "0" | "off" | "n" - kexec handover is disabled + "1" | "on" | "y" - kexec handover is enabled + + kho_scratch= [KEXEC,EARLY] + Format: ll[KMG],mm[KMG],nn[KMG] | nn% + Defines the size of the KHO scratch region. The KHO + scratch regions are physically contiguous memory + ranges that can only be used for non-kernel + allocations. That way, even when memory is heavily + fragmented with handed over memory, the kexeced + kernel will always have enough contiguous ranges to + bootstrap itself. + + It is possible to specify the exact amount of + memory in the form of "ll[KMG],mm[KMG],nn[KMG]" + where the first parameter defines the size of a low + memory scratch area, the second parameter defines + the size of a global scratch area and the third + parameter defines the size of additional per-node + scratch areas. The form "nn%" defines scale factor + (in percents) of memory that was used during boot. + kmac= [MIPS] Korina ethernet MAC address. Configure the RouterBoard 532 series on-chip Ethernet adapter MAC address. diff --git a/Documentation/admin-guide/laptops/alienware-wmi.rst b/Documentation/admin-guide/laptops/alienware-wmi.rst new file mode 100644 index 0000000000000..27a32a8057da8 --- /dev/null +++ b/Documentation/admin-guide/laptops/alienware-wmi.rst @@ -0,0 +1,127 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +==================== +Alienware WMI Driver +==================== + +Kurt Borja + +This is a driver for the "WMAX" WMI device, which is found in most Dell gaming +laptops and controls various special features. + +Before the launch of M-Series laptops (~2018), the "WMAX" device controlled +basic RGB lighting, deep sleep mode, HDMI mode and amplifier status. + +Later, this device was completely repurpused. Now it mostly deals with thermal +profiles, sensor monitoring and overclocking. This interface is named "AWCC" and +is known to be used by the AWCC OEM application to control these features. + +The alienware-wmi driver controls both interfaces. + +AWCC Interface +============== + +WMI device documentation: Documentation/wmi/devices/alienware-wmi.rst + +Supported devices +----------------- + +- Alienware M-Series laptops +- Alienware X-Series laptops +- Alienware Aurora Desktops +- Dell G-Series laptops + +If you believe your device supports the AWCC interface and you don't have any of +the features described in this document, try the following alienware-wmi module +parameters: + +- ``force_platform_profile=1``: Forces probing for platform profile support +- ``force_hwmon=1``: Forces probing for HWMON support + +If the module loads successfully with these parameters, consider submitting a +patch adding your model to the ``awcc_dmi_table`` located in +``drivers/platform/x86/dell/alienware-wmi-wmax.c`` or contacting the maintainer +for further guidance. + +Status +------ + +The following features are currently supported: + +- :ref:`Platform Profile `: + + - Thermal profile control + + - G-Mode toggling + +- :ref:`HWMON `: + + - Sensor monitoring + + - Manual fan control + +.. _platform-profile: + +Platform Profile +---------------- + +The AWCC interface exposes various firmware defined thermal profiles. These are +exposed to user-space through the Platform Profile class interface. Refer to +:ref:`sysfs-class-platform-profile ` +for more information. + +The name of the platform-profile class device exported by this driver is +"alienware-wmi" and it's path can be found with: + +:: + + grep -l "alienware-wmi" /sys/class/platform-profile/platform-profile-*/name | sed 's|/[^/]*$||' + +If the device supports G-Mode, it is also toggled when selecting the +``performance`` profile. + +.. note:: + You may set the ``force_gmode`` module parameter to always try to toggle this + feature, without checking if your model supports it. + +.. _hwmon: + +HWMON +----- + +The AWCC interface also supports sensor monitoring and manual fan control. Both +of these features are exposed to user-space through the HWMON interface. + +The name of the hwmon class device exported by this driver is "alienware_wmi" +and it's path can be found with: + +:: + + grep -l "alienware_wmi" /sys/class/hwmon/hwmon*/name | sed 's|/[^/]*$||' + +Sensor monitoring is done through the standard HWMON interface. Refer to +:ref:`sysfs-class-hwmon ` for more +information. + +Manual fan control on the other hand, is not exposed directly by the AWCC +interface. Instead it let's us control a fan `boost` value. This `boost` value +has the following aproximate behavior over the fan pwm: + +:: + + pwm = pwm_base + (fan_boost / 255) * (pwm_max - pwm_base) + +Due to the above behavior, the fan `boost` control is exposed to user-space +through the following, custom hwmon sysfs attribute: + +=============================== ======= ======================================= +Name Perm Description +=============================== ======= ======================================= +fan[1-4]_boost RW Fan boost value. + + Integer value between 0 and 255 +=============================== ======= ======================================= + +.. note:: + In some devices, manual fan control only works reliably if the ``custom`` + platform profile is selected. diff --git a/Documentation/admin-guide/laptops/index.rst b/Documentation/admin-guide/laptops/index.rst index e71c8984c23e4..db842b629303c 100644 --- a/Documentation/admin-guide/laptops/index.rst +++ b/Documentation/admin-guide/laptops/index.rst @@ -7,6 +7,7 @@ Laptop Drivers .. toctree:: :maxdepth: 1 + alienware-wmi asus-laptop disk-shock-protection laptop-mode diff --git a/Documentation/admin-guide/media/c3-isp.dot b/Documentation/admin-guide/media/c3-isp.dot new file mode 100644 index 0000000000000..42dc931ee84a7 --- /dev/null +++ b/Documentation/admin-guide/media/c3-isp.dot @@ -0,0 +1,26 @@ +digraph board { + rankdir=TB + n00000001 [label="{{ 0 | 1} | c3-isp-core\n/dev/v4l-subdev0 | { 2 | 3 | 4 | 5}}", shape=Mrecord, style=filled, fillcolor=green] + n00000001:port3 -> n00000008:port0 + n00000001:port4 -> n0000000b:port0 + n00000001:port5 -> n0000000e:port0 + n00000001:port2 -> n00000027 + n00000008 [label="{{ 0} | c3-isp-resizer0\n/dev/v4l-subdev1 | { 1}}", shape=Mrecord, style=filled, fillcolor=green] + n00000008:port1 -> n00000016 [style=bold] + n0000000b [label="{{ 0} | c3-isp-resizer1\n/dev/v4l-subdev2 | { 1}}", shape=Mrecord, style=filled, fillcolor=green] + n0000000b:port1 -> n0000001a [style=bold] + n0000000e [label="{{ 0} | c3-isp-resizer2\n/dev/v4l-subdev3 | { 1}}", shape=Mrecord, style=filled, fillcolor=green] + n0000000e:port1 -> n00000023 [style=bold] + n00000011 [label="{{ 0} | c3-mipi-adapter\n/dev/v4l-subdev4 | { 1}}", shape=Mrecord, style=filled, fillcolor=green] + n00000011:port1 -> n00000001:port0 [style=bold] + n00000016 [label="c3-isp-cap0\n/dev/video0", shape=box, style=filled, fillcolor=yellow] + n0000001a [label="c3-isp-cap1\n/dev/video1", shape=box, style=filled, fillcolor=yellow] + n0000001e [label="{{ 0} | c3-mipi-csi2\n/dev/v4l-subdev5 | { 1}}", shape=Mrecord, style=filled, fillcolor=green] + n0000001e:port1 -> n00000011:port0 [style=bold] + n00000023 [label="c3-isp-cap2\n/dev/video2", shape=box, style=filled, fillcolor=yellow] + n00000027 [label="c3-isp-stats\n/dev/video3", shape=box, style=filled, fillcolor=yellow] + n0000002b [label="c3-isp-params\n/dev/video4", shape=box, style=filled, fillcolor=yellow] + n0000002b -> n00000001:port1 + n0000003f [label="{{} | imx290 2-001a\n/dev/v4l-subdev6 | { 0}}", shape=Mrecord, style=filled, fillcolor=green] + n0000003f:port0 -> n0000001e:port0 [style=bold] +} diff --git a/Documentation/admin-guide/media/c3-isp.rst b/Documentation/admin-guide/media/c3-isp.rst new file mode 100644 index 0000000000000..ac508b8c68319 --- /dev/null +++ b/Documentation/admin-guide/media/c3-isp.rst @@ -0,0 +1,101 @@ +.. SPDX-License-Identifier: (GPL-2.0-only OR MIT) + +.. include:: + +================================================= +Amlogic C3 Image Signal Processing (C3ISP) driver +================================================= + +Introduction +============ + +This file documents the Amlogic C3ISP driver located under +drivers/media/platform/amlogic/c3/isp. + +The current version of the driver supports the C3ISP found on +Amlogic C308L processor. + +The driver implements V4L2, Media controller and V4L2 subdev interfaces. +Camera sensor using V4L2 subdev interface in the kernel is supported. + +The driver has been tested on AW419-C308L-Socket platform. + +Amlogic C3 ISP +============== + +The Camera hardware found on C308L processors and supported by +the driver consists of: + +- 1 MIPI-CSI-2 module: handles the physical layer of the MIPI CSI-2 receiver and + receives data from the connected camera sensor. +- 1 MIPI-ADAPTER module: organizes MIPI data to meet ISP input requirements and + send MIPI data to ISP. +- 1 ISP (Image Signal Processing) module: contains a pipeline of image processing + hardware blocks. The ISP pipeline contains three resizers at the end each of + them connected to a DMA interface which writes the output data to memory. + +A high-level functional view of the C3 ISP is presented below.:: + + +----------+ +-------+ + | Resizer |--->| WRMIF | + +---------+ +------------+ +--------------+ +-------+ |----------+ +-------+ + | Sensor |--->| MIPI CSI-2 |--->| MIPI ADAPTER |--->| ISP |---|----------+ +-------+ + +---------+ +------------+ +--------------+ +-------+ | Resizer |--->| WRMIF | + +----------+ +-------+ + |----------+ +-------+ + | Resizer |--->| WRMIF | + +----------+ +-------+ + +Driver architecture and design +============================== + +With the goal to model the hardware links between the modules and to expose a +clean, logical and usable interface, the driver registers the following V4L2 +sub-devices: + +- 1 `c3-mipi-csi2` sub-device - the MIPI CSI-2 receiver +- 1 `c3-mipi-adapter` sub-device - the MIPI adapter +- 1 `c3-isp-core` sub-device - the ISP core +- 3 `c3-isp-resizer` sub-devices - the ISP resizers + +The `c3-isp-core` sub-device is linked to 2 video device nodes for statistics +capture and parameters programming: + +- the `c3-isp-stats` capture video device node for statistics capture +- the `c3-isp-params` output video device for parameters programming + +Each `c3-isp-resizer` sub-device is linked to a capture video device node where +frames are captured from: + +- `c3-isp-resizer0` is linked to the `c3-isp-cap0` capture video device +- `c3-isp-resizer1` is linked to the `c3-isp-cap1` capture video device +- `c3-isp-resizer2` is linked to the `c3-isp-cap2` capture video device + +The media controller pipeline graph is as follows (with connected a +IMX290 camera sensor): + +.. _isp_topology_graph: + +.. kernel-figure:: c3-isp.dot + :alt: c3-isp.dot + :align: center + + Media pipeline topology + +Implementation +============== + +Runtime configuration of the ISP hardware is performed on the `c3-isp-params` +video device node using the :ref:`V4L2_META_FMT_C3ISP_PARAMS +` as data format. The buffer structure is defined by +:c:type:`c3_isp_params_cfg`. + +Statistics are captured from the `c3-isp-stats` video device node using the +:ref:`V4L2_META_FMT_C3ISP_STATS ` data format. + +The final picture size and format is configured using the V4L2 video +capture interface on the `c3-isp-cap[0, 2]` video device nodes. + +The Amlogic C3 ISP is supported by `libcamera `_ with a +dedicated pipeline handler and algorithms that perform run-time image correction +and enhancement. diff --git a/Documentation/admin-guide/media/mgb4.rst b/Documentation/admin-guide/media/mgb4.rst index f69d331e3cb15..5ac69b833a7a7 100644 --- a/Documentation/admin-guide/media/mgb4.rst +++ b/Documentation/admin-guide/media/mgb4.rst @@ -1,8 +1,17 @@ .. SPDX-License-Identifier: GPL-2.0 +.. include:: + The mgb4 driver =============== +Copyright |copy| 2023 - 2025 Digiteq Automotive + author: Martin Tůma + +This is a v4l2 device driver for the Digiteq Automotive FrameGrabber 4, a PCIe +card capable of capturing and generating FPD-Link III and GMSL2/3 video streams +as used in the automotive industry. + sysfs interface --------------- diff --git a/Documentation/admin-guide/media/pci-cardlist.rst b/Documentation/admin-guide/media/pci-cardlist.rst index 7d8e3c8987dba..239879634ea52 100644 --- a/Documentation/admin-guide/media/pci-cardlist.rst +++ b/Documentation/admin-guide/media/pci-cardlist.rst @@ -86,7 +86,6 @@ saa7134 Philips SAA7134 saa7164 NXP SAA7164 smipcie SMI PCIe DVBSky cards solo6x10 Bluecherry / Softlogic 6x10 capture cards (MPEG-4/H.264) -sta2x11_vip STA2X11 VIP Video For Linux tw5864 Techwell TW5864 video/audio grabber and encoder tw686x Intersil/Techwell TW686x tw68 Techwell tw68x Video For Linux diff --git a/Documentation/admin-guide/media/v4l-drivers.rst b/Documentation/admin-guide/media/v4l-drivers.rst index e8761561b2fe7..3bac5165b1341 100644 --- a/Documentation/admin-guide/media/v4l-drivers.rst +++ b/Documentation/admin-guide/media/v4l-drivers.rst @@ -10,6 +10,7 @@ Video4Linux (V4L) driver-specific documentation :maxdepth: 2 bttv + c3-isp cafe_ccic cx88 fimc diff --git a/Documentation/admin-guide/mm/damon/index.rst b/Documentation/admin-guide/mm/damon/index.rst index 33d37bb2fb4e5..bc7e976120e0b 100644 --- a/Documentation/admin-guide/mm/damon/index.rst +++ b/Documentation/admin-guide/mm/damon/index.rst @@ -1,12 +1,11 @@ .. SPDX-License-Identifier: GPL-2.0 -========================== -DAMON: Data Access MONitor -========================== +================================================================ +DAMON: Data Access MONitoring and Access-aware System Operations +================================================================ -:doc:`DAMON ` allows light-weight data access monitoring. -Using DAMON, users can analyze the memory access patterns of their systems and -optimize those. +:doc:`DAMON ` is a Linux kernel subsystem for efficient data +access monitoring and access-aware system operations. .. toctree:: :maxdepth: 2 diff --git a/Documentation/admin-guide/mm/damon/usage.rst b/Documentation/admin-guide/mm/damon/usage.rst index ced2013db3df5..d960aba72b82f 100644 --- a/Documentation/admin-guide/mm/damon/usage.rst +++ b/Documentation/admin-guide/mm/damon/usage.rst @@ -81,7 +81,7 @@ comma (","). │ │ │ │ │ │ │ :ref:`quotas `/ms,bytes,reset_interval_ms,effective_bytes │ │ │ │ │ │ │ │ weights/sz_permil,nr_accesses_permil,age_permil │ │ │ │ │ │ │ │ :ref:`goals `/nr_goals - │ │ │ │ │ │ │ │ │ 0/target_metric,target_value,current_value + │ │ │ │ │ │ │ │ │ 0/target_metric,target_value,current_value,nid │ │ │ │ │ │ │ :ref:`watermarks `/metric,interval_us,high,mid,low │ │ │ │ │ │ │ :ref:`{core_,ops_,}filters `/nr_filters │ │ │ │ │ │ │ │ 0/type,matching,allow,memcg_path,addr_start,addr_end,target_idx,min,max @@ -390,11 +390,11 @@ number (``N``) to the file creates the number of child directories named ``0`` to ``N-1``. Each directory represents each goal and current achievement. Among the multiple feedback, the best one is used. -Each goal directory contains three files, namely ``target_metric``, -``target_value`` and ``current_value``. Users can set and get the three -parameters for the quota auto-tuning goals that specified on the :ref:`design -doc ` by writing to and reading from each -of the files. Note that users should further write +Each goal directory contains four files, namely ``target_metric``, +``target_value``, ``current_value`` and ``nid``. Users can set and get the +four parameters for the quota auto-tuning goals that specified on the +:ref:`design doc ` by writing to and +reading from each of the files. Note that users should further write ``commit_schemes_quota_goals`` to the ``state`` file of the :ref:`kdamond directory ` to pass the feedback to DAMON. diff --git a/Documentation/admin-guide/mm/index.rst b/Documentation/admin-guide/mm/index.rst index 8b35795b664be..2d2f6c222308f 100644 --- a/Documentation/admin-guide/mm/index.rst +++ b/Documentation/admin-guide/mm/index.rst @@ -42,3 +42,4 @@ the Linux memory management. transhuge userfaultfd zswap + kho diff --git a/Documentation/admin-guide/mm/kho.rst b/Documentation/admin-guide/mm/kho.rst new file mode 100644 index 0000000000000..6dc18ed4b8861 --- /dev/null +++ b/Documentation/admin-guide/mm/kho.rst @@ -0,0 +1,115 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +==================== +Kexec Handover Usage +==================== + +Kexec HandOver (KHO) is a mechanism that allows Linux to preserve memory +regions, which could contain serialized system states, across kexec. + +This document expects that you are familiar with the base KHO +:ref:`concepts `. If you have not read +them yet, please do so now. + +Prerequisites +============= + +KHO is available when the kernel is compiled with ``CONFIG_KEXEC_HANDOVER`` +set to y. Every KHO producer may have its own config option that you +need to enable if you would like to preserve their respective state across +kexec. + +To use KHO, please boot the kernel with the ``kho=on`` command line +parameter. You may use ``kho_scratch`` parameter to define size of the +scratch regions. For example ``kho_scratch=16M,512M,256M`` will reserve a +16 MiB low memory scratch area, a 512 MiB global scratch region, and 256 MiB +per NUMA node scratch regions on boot. + +Perform a KHO kexec +=================== + +First, before you perform a KHO kexec, you need to move the system into +the :ref:`KHO finalization phase ` :: + + $ echo 1 > /sys/kernel/debug/kho/out/finalize + +After this command, the KHO FDT is available in +``/sys/kernel/debug/kho/out/fdt``. Other subsystems may also register +their own preserved sub FDTs under +``/sys/kernel/debug/kho/out/sub_fdts/``. + +Next, load the target payload and kexec into it. It is important that you +use the ``-s`` parameter to use the in-kernel kexec file loader, as user +space kexec tooling currently has no support for KHO with the user space +based file loader :: + + # kexec -l /path/to/bzImage --initrd /path/to/initrd -s + # kexec -e + +The new kernel will boot up and contain some of the previous kernel's state. + +For example, if you used ``reserve_mem`` command line parameter to create +an early memory reservation, the new kernel will have that memory at the +same physical address as the old kernel. + +Abort a KHO exec +================ + +You can move the system out of KHO finalization phase again by calling :: + + $ echo 0 > /sys/kernel/debug/kho/out/active + +After this command, the KHO FDT is no longer available in +``/sys/kernel/debug/kho/out/fdt``. + +debugfs Interfaces +================== + +Currently KHO creates the following debugfs interfaces. Notice that these +interfaces may change in the future. They will be moved to sysfs once KHO is +stabilized. + +``/sys/kernel/debug/kho/out/finalize`` + Kexec HandOver (KHO) allows Linux to transition the state of + compatible drivers into the next kexec'ed kernel. To do so, + device drivers will instruct KHO to preserve memory regions, + which could contain serialized kernel state. + While the state is serialized, they are unable to perform + any modifications to state that was serialized, such as + handed over memory allocations. + + When this file contains "1", the system is in the transition + state. When contains "0", it is not. To switch between the + two states, echo the respective number into this file. + +``/sys/kernel/debug/kho/out/fdt`` + When KHO state tree is finalized, the kernel exposes the + flattened device tree blob that carries its current KHO + state in this file. Kexec user space tooling can use this + as input file for the KHO payload image. + +``/sys/kernel/debug/kho/out/scratch_len`` + Lengths of KHO scratch regions, which are physically contiguous + memory regions that will always stay available for future kexec + allocations. Kexec user space tools can use this file to determine + where it should place its payload images. + +``/sys/kernel/debug/kho/out/scratch_phys`` + Physical locations of KHO scratch regions. Kexec user space tools + can use this file in conjunction to scratch_phys to determine where + it should place its payload images. + +``/sys/kernel/debug/kho/out/sub_fdts/`` + In the KHO finalization phase, KHO producers register their own + FDT blob under this directory. + +``/sys/kernel/debug/kho/in/fdt`` + When the kernel was booted with Kexec HandOver (KHO), + the state tree that carries metadata about the previous + kernel's state is in this file in the format of flattened + device tree. This file may disappear when all consumers of + it finished to interpret their metadata. + +``/sys/kernel/debug/kho/in/sub_fdts/`` + Similar to ``kho/out/sub_fdts/``, but contains sub FDT blobs + of KHO producers passed from the old kernel. diff --git a/Documentation/admin-guide/mm/multigen_lru.rst b/Documentation/admin-guide/mm/multigen_lru.rst index 33e068830497e..9cb54b4ff5d9d 100644 --- a/Documentation/admin-guide/mm/multigen_lru.rst +++ b/Documentation/admin-guide/mm/multigen_lru.rst @@ -151,8 +151,9 @@ generations less than or equal to ``min_gen_nr``. ``min_gen_nr`` should be less than ``max_gen_nr-1``, since ``max_gen_nr`` and ``max_gen_nr-1`` are not fully aged (equivalent to the active list) and therefore cannot be evicted. ``swappiness`` -overrides the default value in ``/proc/sys/vm/swappiness``. -``nr_to_reclaim`` limits the number of pages to evict. +overrides the default value in ``/proc/sys/vm/swappiness`` and the valid +range is [0-200, max], with max being exclusively used for the reclamation +of anonymous memory. ``nr_to_reclaim`` limits the number of pages to evict. A typical use case is that a job scheduler runs this command before it tries to land a new job on a server. If it fails to materialize enough diff --git a/Documentation/admin-guide/mm/pagemap.rst b/Documentation/admin-guide/mm/pagemap.rst index afce291649dd6..e60e9211fd9b2 100644 --- a/Documentation/admin-guide/mm/pagemap.rst +++ b/Documentation/admin-guide/mm/pagemap.rst @@ -250,6 +250,7 @@ Following flags about pages are currently supported: - ``PAGE_IS_PFNZERO`` - Page has zero PFN - ``PAGE_IS_HUGE`` - Page is PMD-mapped THP or Hugetlb backed - ``PAGE_IS_SOFT_DIRTY`` - Page is soft-dirty +- ``PAGE_IS_GUARD`` - Page is a part of a guard region The ``struct pm_scan_arg`` is used as the argument of the IOCTL. diff --git a/Documentation/admin-guide/namespaces/resource-control.rst b/Documentation/admin-guide/namespaces/resource-control.rst index 369556e00f0cb..553a448032313 100644 --- a/Documentation/admin-guide/namespaces/resource-control.rst +++ b/Documentation/admin-guide/namespaces/resource-control.rst @@ -1,17 +1,17 @@ -=========================== -Namespaces research control -=========================== +==================================== +User namespaces and resource control +==================================== -There are a lot of kinds of objects in the kernel that don't have -individual limits or that have limits that are ineffective when a set -of processes is allowed to switch user ids. With user namespaces -enabled in a kernel for people who don't trust their users or their -users programs to play nice this problems becomes more acute. +The kernel contains many kinds of objects that either don't have +individual limits or that have limits which are ineffective when +a set of processes is allowed to switch their UID. On a system +where the admins don't trust their users or their users' programs, +user namespaces expose the system to potential misuse of resources. -Therefore it is recommended that memory control groups be enabled in -kernels that enable user namespaces, and it is further recommended -that userspace configure memory control groups to limit how much -memory user's they don't trust to play nice can use. +In order to mitigate this, we recommend that admins enable memory +control groups on any system that enables user namespaces. +Furthermore, we recommend that admins configure the memory control +groups to limit the maximum memory usable by any untrusted user. Memory control groups can be configured by installing the libcgroup package present on most distros editing /etc/cgrules.conf, diff --git a/Documentation/admin-guide/pm/cpufreq.rst b/Documentation/admin-guide/pm/cpufreq.rst index 3950583f2b154..2d74af7f0efe1 100644 --- a/Documentation/admin-guide/pm/cpufreq.rst +++ b/Documentation/admin-guide/pm/cpufreq.rst @@ -231,7 +231,7 @@ are the following: present). The existence of the limit may be a result of some (often unintentional) - BIOS settings, restrictions coming from a service processor or another + BIOS settings, restrictions coming from a service processor or other BIOS/HW-based mechanisms. This does not cover ACPI thermal limitations which can be discovered @@ -258,8 +258,8 @@ are the following: extension on ARM). If one cannot be determined, this attribute should not be present. - Note, that failed attempt to retrieve current frequency for a given - CPU(s) will result in an appropriate error, i.e: EAGAIN for CPU that + Note that failed attempt to retrieve current frequency for a given + CPU(s) will result in an appropriate error, i.e.: EAGAIN for CPU that remains idle (raised on ARM). ``cpuinfo_max_freq`` @@ -499,7 +499,7 @@ This governor exposes the following tunables: represented by it to be 1.5 times as high as the transition latency (the default):: - # echo `$(($(cat cpuinfo_transition_latency) * 3 / 2)) > ondemand/sampling_rate + # echo `$(($(cat cpuinfo_transition_latency) * 3 / 2))` > ondemand/sampling_rate ``up_threshold`` If the estimated CPU load is above this value (in percent), the governor diff --git a/Documentation/admin-guide/pm/intel_idle.rst b/Documentation/admin-guide/pm/intel_idle.rst index 5940528146eb0..ed6f055d4b148 100644 --- a/Documentation/admin-guide/pm/intel_idle.rst +++ b/Documentation/admin-guide/pm/intel_idle.rst @@ -38,6 +38,27 @@ instruction at all. only way to pass early-configuration-time parameters to it is via the kernel command line. +Sysfs Interface +=============== + +The ``intel_idle`` driver exposes the following ``sysfs`` attributes in +``/sys/devices/system/cpu/cpuidle/``: + +``intel_c1_demotion`` + Enable or disable C1 demotion for all CPUs in the system. This file is + only exposed on platforms that support the C1 demotion feature and where + it was tested. Value 0 means that C1 demotion is disabled, value 1 means + that it is enabled. Write 0 or 1 to disable or enable C1 demotion for + all CPUs. + + The C1 demotion feature involves the platform firmware demoting deep + C-state requests from the OS (e.g., C6 requests) to C1. The idea is that + firmware monitors CPU wake-up rate, and if it is higher than a + platform-specific threshold, the firmware demotes deep C-state requests + to C1. For example, Linux requests C6, but firmware noticed too many + wake-ups per second, and it keeps the CPU in C1. When the CPU stays in + C1 long enough, the platform promotes it back to C6. This may improve + some workloads' performance, but it may also increase power consumption. .. _intel-idle-enumeration-of-states: diff --git a/Documentation/admin-guide/pm/intel_pstate.rst b/Documentation/admin-guide/pm/intel_pstate.rst index 78fc83ed2a7ef..26e702c7016e5 100644 --- a/Documentation/admin-guide/pm/intel_pstate.rst +++ b/Documentation/admin-guide/pm/intel_pstate.rst @@ -329,6 +329,106 @@ information listed above is the same for all of the processors supporting the HWP feature, which is why ``intel_pstate`` works with all of them.] +Support for Hybrid Processors +============================= + +Some processors supported by ``intel_pstate`` contain two or more types of CPU +cores differing by the maximum turbo P-state, performance vs power characteristics, +cache sizes, and possibly other properties. They are commonly referred to as +hybrid processors. To support them, ``intel_pstate`` requires HWP to be enabled +and it assumes the HWP performance units to be the same for all CPUs in the +system, so a given HWP performance level always represents approximately the +same physical performance regardless of the core (CPU) type. + +Hybrid Processors with SMT +-------------------------- + +On systems where SMT (Simultaneous Multithreading), also referred to as +HyperThreading (HT) in the context of Intel processors, is enabled on at least +one core, ``intel_pstate`` assigns performance-based priorities to CPUs. Namely, +the priority of a given CPU reflects its highest HWP performance level which +causes the CPU scheduler to generally prefer more performant CPUs, so the less +performant CPUs are used when the other ones are fully loaded. However, SMT +siblings (that is, logical CPUs sharing one physical core) are treated in a +special way such that if one of them is in use, the effective priority of the +other ones is lowered below the priorities of the CPUs located in the other +physical cores. + +This approach maximizes performance in the majority of cases, but unfortunately +it also leads to excessive energy usage in some important scenarios, like video +playback, which is not generally desirable. While there is no other viable +choice with SMT enabled because the effective capacity and utilization of SMT +siblings are hard to determine, hybrid processors without SMT can be handled in +more energy-efficient ways. + +.. _CAS: + +Capacity-Aware Scheduling Support +--------------------------------- + +The capacity-aware scheduling (CAS) support in the CPU scheduler is enabled by +``intel_pstate`` by default on hybrid processors without SMT. CAS generally +causes the scheduler to put tasks on a CPU so long as there is a sufficient +amount of spare capacity on it, and if the utilization of a given task is too +high for it, the task will need to go somewhere else. + +Since CAS takes CPU capacities into account, it does not require CPU +prioritization and it allows tasks to be distributed more symmetrically among +the more performant and less performant CPUs. Once placed on a CPU with enough +capacity to accommodate it, a task may just continue to run there regardless of +whether or not the other CPUs are fully loaded, so on average CAS reduces the +utilization of the more performant CPUs which causes the energy usage to be more +balanced because the more performant CPUs are generally less energy-efficient +than the less performant ones. + +In order to use CAS, the scheduler needs to know the capacity of each CPU in +the system and it needs to be able to compute scale-invariant utilization of +CPUs, so ``intel_pstate`` provides it with the requisite information. + +First of all, the capacity of each CPU is represented by the ratio of its highest +HWP performance level, multiplied by 1024, to the highest HWP performance level +of the most performant CPU in the system, which works because the HWP performance +units are the same for all CPUs. Second, the frequency-invariance computations, +carried out by the scheduler to always express CPU utilization in the same units +regardless of the frequency it is currently running at, are adjusted to take the +CPU capacity into account. All of this happens when ``intel_pstate`` has +registered itself with the ``CPUFreq`` core and it has figured out that it is +running on a hybrid processor without SMT. + +Energy-Aware Scheduling Support +------------------------------- + +If ``CONFIG_ENERGY_MODEL`` has been set during kernel configuration and +``intel_pstate`` runs on a hybrid processor without SMT, in addition to enabling +`CAS `_ it registers an Energy Model for the processor. This allows the +Energy-Aware Scheduling (EAS) support to be enabled in the CPU scheduler if +``schedutil`` is used as the ``CPUFreq`` governor which requires ``intel_pstate`` +to operate in the `passive mode `_. + +The Energy Model registered by ``intel_pstate`` is artificial (that is, it is +based on abstract cost values and it does not include any real power numbers) +and it is relatively simple to avoid unnecessary computations in the scheduler. +There is a performance domain in it for every CPU in the system and the cost +values for these performance domains have been chosen so that running a task on +a less performant (small) CPU appears to be always cheaper than running that +task on a more performant (big) CPU. However, for two CPUs of the same type, +the cost difference depends on their current utilization, and the CPU whose +current utilization is higher generally appears to be a more expensive +destination for a given task. This helps to balance the load among CPUs of the +same type. + +Since EAS works on top of CAS, high-utilization tasks are always migrated to +CPUs with enough capacity to accommodate them, but thanks to EAS, low-utilization +tasks tend to be placed on the CPUs that look less expensive to the scheduler. +Effectively, this causes the less performant and less loaded CPUs to be +preferred as long as they have enough spare capacity to run the given task +which generally leads to reduced energy usage. + +The Energy Model created by ``intel_pstate`` can be inspected by looking at +the ``energy_model`` directory in ``debugfs`` (typlically mounted on +``/sys/kernel/debug/``). + + User Space Interface in ``sysfs`` ================================= @@ -697,8 +797,8 @@ of them have to be prepended with the ``intel_pstate=`` prefix. Limits`_ for details). ``no_cas`` - Do not enable capacity-aware scheduling (CAS) which is enabled by - default on hybrid systems. + Do not enable `capacity-aware scheduling `_ which is enabled by + default on hybrid systems without SMT. Diagnostics and Tuning ====================== diff --git a/Documentation/admin-guide/pm/intel_uncore_frequency_scaling.rst b/Documentation/admin-guide/pm/intel_uncore_frequency_scaling.rst index 5151ec312dc04..d367ba4d744af 100644 --- a/Documentation/admin-guide/pm/intel_uncore_frequency_scaling.rst +++ b/Documentation/admin-guide/pm/intel_uncore_frequency_scaling.rst @@ -91,12 +91,22 @@ Attributes in each directory: ``domain_id`` This attribute is used to get the power domain id of this instance. +``die_id`` + This attribute is used to get the Linux die id of this instance. + This attribute is only present for domains with core agents and + when the CPUID leaf 0x1f presents die ID. + ``fabric_cluster_id`` This attribute is used to get the fabric cluster id of this instance. ``package_id`` This attribute is used to get the package id of this instance. +``agent_types`` + This attribute displays all the hardware agents present within the + domain. Each agent has the capability to control one or more hardware + subsystems, which include: core, cache, memory, and I/O. + The other attributes are same as presented at package_*_die_* level. In most of current use cases, the "max_freq_khz" and "min_freq_khz" diff --git a/Documentation/admin-guide/quickly-build-trimmed-linux.rst b/Documentation/admin-guide/quickly-build-trimmed-linux.rst index 07cfd8863b46e..4a5ffb0996a35 100644 --- a/Documentation/admin-guide/quickly-build-trimmed-linux.rst +++ b/Documentation/admin-guide/quickly-build-trimmed-linux.rst @@ -347,7 +347,7 @@ again. [:ref:`details`] -.. _submit_improvements: +.. _submit_improvements_qbtl: Did you run into trouble following any of the above steps that is not cleared up by the reference section below? Or do you have ideas how to improve the text? @@ -1070,7 +1070,7 @@ complicated, and harder to follow. That being said: this of course is a balancing act. Hence, if you think an additional use-case is worth describing, suggest it to the maintainers of this -document, as :ref:`described above `. +document, as :ref:`described above `. .. diff --git a/Documentation/admin-guide/reporting-issues.rst b/Documentation/admin-guide/reporting-issues.rst index 2fd5a030235ad..9a847506f6ec6 100644 --- a/Documentation/admin-guide/reporting-issues.rst +++ b/Documentation/admin-guide/reporting-issues.rst @@ -41,7 +41,7 @@ If you are facing multiple issues with the Linux kernel at once, report each separately. While writing your report, include all information relevant to the issue, like the kernel and the distro used. In case of a regression, CC the regressions mailing list (regressions@lists.linux.dev) to your report. Also try -to pin-point the culprit with a bisection; if you succeed, include its +to pinpoint the culprit with a bisection; if you succeed, include its commit-id and CC everyone in the sign-off-by chain. Once the report is out, answer any questions that come up and help where you @@ -206,7 +206,7 @@ Reporting issues only occurring in older kernel version lines This subsection is for you, if you tried the latest mainline kernel as outlined above, but failed to reproduce your issue there; at the same time you want to see the issue fixed in a still supported stable or longterm series or vendor -kernels regularly rebased on those. If that the case, follow these steps: +kernels regularly rebased on those. If that is the case, follow these steps: * Prepare yourself for the possibility that going through the next few steps might not get the issue solved in older releases: the fix might be too big @@ -312,7 +312,7 @@ small modifications to a kernel based on a recent Linux version; that for example often holds true for the mainline kernels shipped by Debian GNU/Linux Sid or Fedora Rawhide. Some developers will also accept reports about issues with kernels from distributions shipping the latest stable kernel, as long as -its only slightly modified; that for example is often the case for Arch Linux, +it's only slightly modified; that for example is often the case for Arch Linux, regular Fedora releases, and openSUSE Tumbleweed. But keep in mind, you better want to use a mainline Linux and avoid using a stable kernel for this process, as outlined in the section 'Install a fresh kernel for testing' in more diff --git a/Documentation/admin-guide/sysctl/vm.rst b/Documentation/admin-guide/sysctl/vm.rst index d385985b305f8..9bef46151d53c 100644 --- a/Documentation/admin-guide/sysctl/vm.rst +++ b/Documentation/admin-guide/sysctl/vm.rst @@ -132,6 +132,12 @@ to latency spikes in unsuspecting applications. The kernel employs various heuristics to avoid wasting CPU cycles if it detects that proactive compaction is not being effective. +Setting the value above 80 will, in addition to lowering the acceptable level +of fragmentation, make the compaction code more sensitive to increases in +fragmentation, i.e. compaction will trigger more often, but reduce +fragmentation by a smaller amount. +This makes the fragmentation level more stable over time. + Be careful when setting it to extreme values like 100, as that may cause excessive background compaction activity. diff --git a/Documentation/admin-guide/verify-bugs-and-bisect-regressions.rst b/Documentation/admin-guide/verify-bugs-and-bisect-regressions.rst index 03c55151346c3..d8946b084b1ec 100644 --- a/Documentation/admin-guide/verify-bugs-and-bisect-regressions.rst +++ b/Documentation/admin-guide/verify-bugs-and-bisect-regressions.rst @@ -267,7 +267,7 @@ culprit might be known already. For further details on what actually qualifies as a regression check out Documentation/admin-guide/reporting-regressions.rst. If you run into any problems while following this guide or have ideas how to -improve it, :ref:`please let the kernel developers know `. +improve it, :ref:`please let the kernel developers know `. .. _introprep_bissbs: @@ -1055,7 +1055,7 @@ follow these instructions. [:ref:`details `] -.. _submit_improvements: +.. _submit_improvements_vbbr: Conclusion ---------- diff --git a/Documentation/arch/arm64/cpu-feature-registers.rst b/Documentation/arch/arm64/cpu-feature-registers.rst index 253e9743de2f9..add66afc7b032 100644 --- a/Documentation/arch/arm64/cpu-feature-registers.rst +++ b/Documentation/arch/arm64/cpu-feature-registers.rst @@ -72,14 +72,15 @@ there are some issues with their usage. process could be migrated to another CPU by the time it uses the register value, unless the CPU affinity is set. Hence, there is no guarantee that the value reflects the processor that it is - currently executing on. The REVIDR is not exposed due to this - constraint, as REVIDR makes sense only in conjunction with the - MIDR. Alternately, MIDR_EL1 and REVIDR_EL1 are exposed via sysfs - at:: + currently executing on. REVIDR and AIDR are not exposed due to this + constraint, as these registers only make sense in conjunction with + the MIDR. Alternately, MIDR_EL1, REVIDR_EL1, and AIDR_EL1 are exposed + via sysfs at:: /sys/devices/system/cpu/cpu$ID/regs/identification/ - \- midr - \- revidr + \- midr_el1 + \- revidr_el1 + \- aidr_el1 3. Implementation -------------------- diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst index f968c13b46a78..b18ef4064bc04 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -57,6 +57,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | Ampere | AmpereOne AC04 | AC04_CPU_10 | AMPERE_ERRATUM_AC03_CPU_38 | +----------------+-----------------+-----------------+-----------------------------+ +| Ampere | AmpereOne AC04 | AC04_CPU_23 | AMPERE_ERRATUM_AC04_CPU_23 | ++----------------+-----------------+-----------------+-----------------------------+ +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A510 | #2457168 | ARM64_ERRATUM_2457168 | +----------------+-----------------+-----------------+-----------------------------+ diff --git a/Documentation/arch/arm64/sme.rst b/Documentation/arch/arm64/sme.rst index b2fa01f85cb5e..4cb38330e7046 100644 --- a/Documentation/arch/arm64/sme.rst +++ b/Documentation/arch/arm64/sme.rst @@ -69,8 +69,8 @@ model features for SME is included in Appendix A. vectors from 0 to VL/8-1 stored in the same endianness invariant format as is used for SVE vectors. -* On thread creation TPIDR2_EL0 is preserved unless CLONE_SETTLS is specified, - in which case it is set to 0. +* On thread creation PSTATE.ZA and TPIDR2_EL0 are preserved unless CLONE_VM + is specified, in which case PSTATE.ZA is set to 0 and TPIDR2_EL0 is set to 0. 2. Vector lengths ------------------ @@ -115,7 +115,7 @@ be zeroed. 5. Signal handling ------------------- -* Signal handlers are invoked with streaming mode and ZA disabled. +* Signal handlers are invoked with PSTATE.SM=0, PSTATE.ZA=0, and TPIDR2_EL0=0. * A new signal frame record TPIDR2_MAGIC is added formatted as a struct tpidr2_context to allow access to TPIDR2_EL0 from signal handlers. @@ -241,7 +241,7 @@ prctl(PR_SME_SET_VL, unsigned long arg) length, or calling PR_SME_SET_VL with the PR_SME_SET_VL_ONEXEC flag, does not constitute a change to the vector length for this purpose. - * Changing the vector length causes PSTATE.ZA and PSTATE.SM to be cleared. + * Changing the vector length causes PSTATE.ZA to be cleared. Calling PR_SME_SET_VL with vl equal to the thread's current vector length, or calling PR_SME_SET_VL with the PR_SME_SET_VL_ONEXEC flag, does not constitute a change to the vector length for this purpose. diff --git a/Documentation/arch/openrisc/openrisc_port.rst b/Documentation/arch/openrisc/openrisc_port.rst index a8f307a3b499c..60b0a9e51d706 100644 --- a/Documentation/arch/openrisc/openrisc_port.rst +++ b/Documentation/arch/openrisc/openrisc_port.rst @@ -40,6 +40,12 @@ Build the Linux kernel as usual:: make ARCH=openrisc CROSS_COMPILE="or1k-linux-" defconfig make ARCH=openrisc CROSS_COMPILE="or1k-linux-" +If you want to embed initramfs in the kernel, also pass ``CONFIG_INITRAMFS_SOURCE``. For example:: + + make ARCH=openrisc CROSS_COMPILE="or1k-linux-" CONFIG_INITRAMFS_SOURCE="path/to/rootfs path/to/devnodes" + +For more information on this, please check Documentation/filesystems/ramfs-rootfs-initramfs.rst. + 3) Running on FPGA (optional) The OpenRISC community typically uses FuseSoC to manage building and programming diff --git a/Documentation/arch/x86/amd_hsmp.rst b/Documentation/arch/x86/amd_hsmp.rst index 2fd917638e426..a094f55c10b0e 100644 --- a/Documentation/arch/x86/amd_hsmp.rst +++ b/Documentation/arch/x86/amd_hsmp.rst @@ -71,6 +71,28 @@ Note: lseek() is not supported as entire metrics table is read. Metrics table definitions will be documented as part of Public PPR. The same is defined in the amd_hsmp.h header. +2. HSMP telemetry sysfs files + +Following sysfs files are available at /sys/devices/platform/AMDI0097:0X/. + +* c0_residency_input: Percentage of cores in C0 state. +* prochot_status: Reports 1 if the processor is at thermal threshold value, + 0 otherwise. +* smu_fw_version: SMU firmware version. +* protocol_version: HSMP interface version. +* ddr_max_bw: Theoretical maximum DDR bandwidth in GB/s. +* ddr_utilised_bw_input: Current utilized DDR bandwidth in GB/s. +* ddr_utilised_bw_perc_input(%): Percentage of current utilized DDR bandwidth. +* mclk_input: Memory clock in MHz. +* fclk_input: Fabric clock in MHz. +* clk_fmax: Maximum frequency of socket in MHz. +* clk_fmin: Minimum frequency of socket in MHz. +* cclk_freq_limit_input: Core clock frequency limit per socket in MHz. +* pwr_current_active_freq_limit: Current active frequency limit of socket + in MHz. +* pwr_current_active_freq_limit_source: Source of current active frequency + limit. + ACPI device object format ========================= The ACPI object format expected from the amd_hsmp driver @@ -116,6 +138,14 @@ for socket with ID00 is given below:: }) } +HSMP HWMON interface +==================== +HSMP power sensors are registered with the hwmon interface. A separate hwmon +directory is created for each socket and the following files are generated +within the hwmon directory. +- power1_input (read only) +- power1_cap_max (read only) +- power1_cap (read, write) An example ========== diff --git a/Documentation/arch/x86/index.rst b/Documentation/arch/x86/index.rst index 58a006525ae81..8ea762494bccf 100644 --- a/Documentation/arch/x86/index.rst +++ b/Documentation/arch/x86/index.rst @@ -32,7 +32,6 @@ x86-specific Documentation pti mds microcode - resctrl tsx_async_abort buslock usb-legacy-support diff --git a/Documentation/arch/x86/x86_64/fsgs.rst b/Documentation/arch/x86/x86_64/fsgs.rst index d07e445dac5cf..6bda4d16d3f74 100644 --- a/Documentation/arch/x86/x86_64/fsgs.rst +++ b/Documentation/arch/x86/x86_64/fsgs.rst @@ -130,7 +130,7 @@ instructions. Clang 5 supports them as well. =================== =========================== _readfsbase_u64() Read the FS base register - _readfsbase_u64() Read the GS base register + _readgsbase_u64() Read the GS base register _writefsbase_u64() Write the FS base register _writegsbase_u64() Write the GS base register =================== =========================== diff --git a/Documentation/bpf/bpf_iterators.rst b/Documentation/bpf/bpf_iterators.rst index 7f514cb6b0525..189e3ec1c6c8e 100644 --- a/Documentation/bpf/bpf_iterators.rst +++ b/Documentation/bpf/bpf_iterators.rst @@ -2,10 +2,117 @@ BPF Iterators ============= +-------- +Overview +-------- + +BPF supports two separate entities collectively known as "BPF iterators": BPF +iterator *program type* and *open-coded* BPF iterators. The former is +a stand-alone BPF program type which, when attached and activated by user, +will be called once for each entity (task_struct, cgroup, etc) that is being +iterated. The latter is a set of BPF-side APIs implementing iterator +functionality and available across multiple BPF program types. Open-coded +iterators provide similar functionality to BPF iterator programs, but gives +more flexibility and control to all other BPF program types. BPF iterator +programs, on the other hand, can be used to implement anonymous or BPF +FS-mounted special files, whose contents are generated by attached BPF iterator +program, backed by seq_file functionality. Both are useful depending on +specific needs. + +When adding a new BPF iterator program, it is expected that similar +functionality will be added as open-coded iterator for maximum flexibility. +It's also expected that iteration logic and code will be maximally shared and +reused between two iterator API surfaces. ----------- -Motivation ----------- +------------------------ +Open-coded BPF Iterators +------------------------ + +Open-coded BPF iterators are implemented as tightly-coupled trios of kfuncs +(constructor, next element fetch, destructor) and iterator-specific type +describing on-the-stack iterator state, which is guaranteed by the BPF +verifier to not be tampered with outside of the corresponding +constructor/destructor/next APIs. + +Each kind of open-coded BPF iterator has its own associated +struct bpf_iter_, where denotes a specific type of iterator. +bpf_iter_ state needs to live on BPF program stack, so make sure it's +small enough to fit on BPF stack. For performance reasons its best to avoid +dynamic memory allocation for iterator state and size the state struct big +enough to fit everything necessary. But if necessary, dynamic memory +allocation is a way to bypass BPF stack limitations. Note, state struct size +is part of iterator's user-visible API, so changing it will break backwards +compatibility, so be deliberate about designing it. + +All kfuncs (constructor, next, destructor) have to be named consistently as +bpf_iter__{new,next,destroy}(), respectively. represents iterator +type, and iterator state should be represented as a matching +`struct bpf_iter_` state type. Also, all iter kfuncs should have +a pointer to this `struct bpf_iter_` as the very first argument. + +Additionally: + - Constructor, i.e., `bpf_iter__new()`, can have arbitrary extra + number of arguments. Return type is not enforced either. + - Next method, i.e., `bpf_iter__next()`, has to return a pointer + type and should have exactly one argument: `struct bpf_iter_ *` + (const/volatile/restrict and typedefs are ignored). + - Destructor, i.e., `bpf_iter__destroy()`, should return void and + should have exactly one argument, similar to the next method. + - `struct bpf_iter_` size is enforced to be positive and + a multiple of 8 bytes (to fit stack slots correctly). + +Such strictness and consistency allows to build generic helpers abstracting +important, but boilerplate, details to be able to use open-coded iterators +effectively and ergonomically (see libbpf's bpf_for_each() macro). This is +enforced at kfunc registration point by the kernel. + +Constructor/next/destructor implementation contract is as follows: + - constructor, `bpf_iter__new()`, always initializes iterator state on + the stack. If any of the input arguments are invalid, constructor should + make sure to still initialize it such that subsequent next() calls will + return NULL. I.e., on error, *return error and construct empty iterator*. + Constructor kfunc is marked with KF_ITER_NEW flag. + + - next method, `bpf_iter__next()`, accepts pointer to iterator state + and produces an element. Next method should always return a pointer. The + contract between BPF verifier is that next method *guarantees* that it + will eventually return NULL when elements are exhausted. Once NULL is + returned, subsequent next calls *should keep returning NULL*. Next method + is marked with KF_ITER_NEXT (and should also have KF_RET_NULL as + NULL-returning kfunc, of course). + + - destructor, `bpf_iter__destroy()`, is always called once. Even if + constructor failed or next returned nothing. Destructor frees up any + resources and marks stack space used by `struct bpf_iter_` as usable + for something else. Destructor is marked with KF_ITER_DESTROY flag. + +Any open-coded BPF iterator implementation has to implement at least these +three methods. It is enforced that for any given type of iterator only +applicable constructor/destructor/next are callable. I.e., verifier ensures +you can't pass number iterator state into, say, cgroup iterator's next method. + +From a 10,000-feet BPF verification point of view, next methods are the points +of forking a verification state, which are conceptually similar to what +verifier is doing when validating conditional jumps. Verifier is branching out +`call bpf_iter__next` instruction and simulates two outcomes: NULL +(iteration is done) and non-NULL (new element is returned). NULL is simulated +first and is supposed to reach exit without looping. After that non-NULL case +is validated and it either reaches exit (for trivial examples with no real +loop), or reaches another `call bpf_iter__next` instruction with the +state equivalent to already (partially) validated one. State equivalency at +that point means we technically are going to be looping forever without +"breaking out" out of established "state envelope" (i.e., subsequent +iterations don't add any new knowledge or constraints to the verifier state, +so running 1, 2, 10, or a million of them doesn't matter). But taking into +account the contract stating that iterator next method *has to* return NULL +eventually, we can conclude that loop body is safe and will eventually +terminate. Given we validated logic outside of the loop (NULL case), and +concluded that loop body is safe (though potentially looping many times), +verifier can claim safety of the overall program logic. + +------------------------ +BPF Iterators Motivation +------------------------ There are a few existing ways to dump kernel data into user space. The most popular one is the ``/proc`` system. For example, ``cat /proc/net/tcp6`` dumps @@ -323,8 +430,8 @@ Now, in the userspace program, pass the pointer of struct to the :: - link = bpf_program__attach_iter(prog, &opts); iter_fd = - bpf_iter_create(bpf_link__fd(link)); + link = bpf_program__attach_iter(prog, &opts); + iter_fd = bpf_iter_create(bpf_link__fd(link)); If both *tid* and *pid* are zero, an iterator created from this struct ``bpf_iter_attach_opts`` will include every opened file of every task in the diff --git a/Documentation/bpf/kfuncs.rst b/Documentation/bpf/kfuncs.rst index a8f5782bd8331..ae468b781d311 100644 --- a/Documentation/bpf/kfuncs.rst +++ b/Documentation/bpf/kfuncs.rst @@ -160,6 +160,23 @@ Or:: ... } +2.2.6 __prog Annotation +--------------------------- +This annotation is used to indicate that the argument needs to be fixed up to +the bpf_prog_aux of the caller BPF program. Any value passed into this argument +is ignored, and rewritten by the verifier. + +An example is given below:: + + __bpf_kfunc int bpf_wq_set_callback_impl(struct bpf_wq *wq, + int (callback_fn)(void *map, int *key, void *value), + unsigned int flags, + void *aux__prog) + { + struct bpf_prog_aux *aux = aux__prog; + ... + } + .. _BPF_kfunc_nodef: 2.3 Using an existing kernel function diff --git a/Documentation/conf.py b/Documentation/conf.py index 3dad1f90b098b..12de52a2b17e7 100644 --- a/Documentation/conf.py +++ b/Documentation/conf.py @@ -28,16 +28,6 @@ def have_command(cmd): """ return shutil.which(cmd) is not None -# Get Sphinx version -major, minor, patch = sphinx.version_info[:3] - -# -# Warn about older versions that we don't want to support for much -# longer. -# -if (major < 2) or (major == 2 and minor < 4): - print('WARNING: support for Sphinx < 2.4 will be removed soon.') - # If extensions (or modules to document with autodoc) are in another directory, # add these directories to sys.path here. If the directory is relative to the # documentation root, use os.path.abspath to make it absolute, like shown here. @@ -57,76 +47,71 @@ def have_command(cmd): 'maintainers_include', 'sphinx.ext.autosectionlabel', 'kernel_abi', 'kernel_feat', 'translations'] -if major >= 3: - if (major > 3) or (minor > 0 or patch >= 2): - # Sphinx c function parser is more pedantic with regards to type - # checking. Due to that, having macros at c:function cause problems. - # Those needed to be scaped by using c_id_attributes[] array - c_id_attributes = [ - # GCC Compiler types not parsed by Sphinx: - "__restrict__", - - # include/linux/compiler_types.h: - "__iomem", - "__kernel", - "noinstr", - "notrace", - "__percpu", - "__rcu", - "__user", - "__force", - "__counted_by_le", - "__counted_by_be", - - # include/linux/compiler_attributes.h: - "__alias", - "__aligned", - "__aligned_largest", - "__always_inline", - "__assume_aligned", - "__cold", - "__attribute_const__", - "__copy", - "__pure", - "__designated_init", - "__visible", - "__printf", - "__scanf", - "__gnu_inline", - "__malloc", - "__mode", - "__no_caller_saved_registers", - "__noclone", - "__nonstring", - "__noreturn", - "__packed", - "__pure", - "__section", - "__always_unused", - "__maybe_unused", - "__used", - "__weak", - "noinline", - "__fix_address", - "__counted_by", - - # include/linux/memblock.h: - "__init_memblock", - "__meminit", - - # include/linux/init.h: - "__init", - "__ref", - - # include/linux/linkage.h: - "asmlinkage", - - # include/linux/btf.h - "__bpf_kfunc", - ] - -else: - extensions.append('cdomain') +# Since Sphinx version 3, the C function parser is more pedantic with regards +# to type checking. Due to that, having macros at c:function cause problems. +# Those needed to be escaped by using c_id_attributes[] array +c_id_attributes = [ + # GCC Compiler types not parsed by Sphinx: + "__restrict__", + + # include/linux/compiler_types.h: + "__iomem", + "__kernel", + "noinstr", + "notrace", + "__percpu", + "__rcu", + "__user", + "__force", + "__counted_by_le", + "__counted_by_be", + + # include/linux/compiler_attributes.h: + "__alias", + "__aligned", + "__aligned_largest", + "__always_inline", + "__assume_aligned", + "__cold", + "__attribute_const__", + "__copy", + "__pure", + "__designated_init", + "__visible", + "__printf", + "__scanf", + "__gnu_inline", + "__malloc", + "__mode", + "__no_caller_saved_registers", + "__noclone", + "__nonstring", + "__noreturn", + "__packed", + "__pure", + "__section", + "__always_unused", + "__maybe_unused", + "__used", + "__weak", + "noinline", + "__fix_address", + "__counted_by", + + # include/linux/memblock.h: + "__init_memblock", + "__meminit", + + # include/linux/init.h: + "__init", + "__ref", + + # include/linux/linkage.h: + "asmlinkage", + + # include/linux/btf.h + "__bpf_kfunc", +] # Ensure that autosectionlabel will produce unique names autosectionlabel_prefix_document = True @@ -149,10 +134,6 @@ def have_command(cmd): else: sys.stderr.write("Unknown env SPHINX_IMGMATH=%s ignored.\n" % env_sphinx_imgmath) -# Always load imgmath for Sphinx <1.8 or for epub docs -load_imgmath = (load_imgmath or (major == 1 and minor < 8) - or 'epub' in sys.argv) - if load_imgmath: extensions.append("sphinx.ext.imgmath") math_renderer = 'imgmath' @@ -322,14 +303,6 @@ def get_cline_version(): for l in css: html_css_files.append(l) -if major <= 1 and minor < 8: - html_context = { - 'css_files': [], - } - - for l in html_css_files: - html_context['css_files'].append('_static/' + l) - if html_theme == 'alabaster': html_theme_options = { 'description': get_cline_version(), @@ -409,11 +382,6 @@ def get_cline_version(): ''', } -# Fix reference escape troubles with Sphinx 1.4.x -if major == 1: - latex_elements['preamble'] += '\\renewcommand*{\\DUrole}[2]{ #2 }\n' - - # Load kerneldoc specific LaTeX settings latex_elements['preamble'] += ''' % Load kerneldoc specific LaTeX settings @@ -540,7 +508,7 @@ def get_cline_version(): # kernel-doc extension configuration for running Sphinx directly (e.g. by Read # the Docs). In a normal build, these are supplied from the Makefile via command # line arguments. -kerneldoc_bin = '../scripts/kernel-doc' +kerneldoc_bin = '../scripts/kernel-doc.py' kerneldoc_srctree = '..' # ------------------------------------------------------------------------------ diff --git a/Documentation/core-api/dma-api.rst b/Documentation/core-api/dma-api.rst index 8e3cce3d0a230..2ad08517e626e 100644 --- a/Documentation/core-api/dma-api.rst +++ b/Documentation/core-api/dma-api.rst @@ -530,6 +530,77 @@ routines, e.g.::: .... } +Part Ie - IOVA-based DMA mappings +--------------------------------- + +These APIs allow a very efficient mapping when using an IOMMU. They are an +optional path that requires extra code and are only recommended for drivers +where DMA mapping performance, or the space usage for storing the DMA addresses +matter. All the considerations from the previous section apply here as well. + +:: + + bool dma_iova_try_alloc(struct device *dev, struct dma_iova_state *state, + phys_addr_t phys, size_t size); + +Is used to try to allocate IOVA space for mapping operation. If it returns +false this API can't be used for the given device and the normal streaming +DMA mapping API should be used. The ``struct dma_iova_state`` is allocated +by the driver and must be kept around until unmap time. + +:: + + static inline bool dma_use_iova(struct dma_iova_state *state) + +Can be used by the driver to check if the IOVA-based API is used after a +call to dma_iova_try_alloc. This can be useful in the unmap path. + +:: + + int dma_iova_link(struct device *dev, struct dma_iova_state *state, + phys_addr_t phys, size_t offset, size_t size, + enum dma_data_direction dir, unsigned long attrs); + +Is used to link ranges to the IOVA previously allocated. The start of all +but the first call to dma_iova_link for a given state must be aligned +to the DMA merge boundary returned by ``dma_get_merge_boundary())``, and +the size of all but the last range must be aligned to the DMA merge boundary +as well. + +:: + + int dma_iova_sync(struct device *dev, struct dma_iova_state *state, + size_t offset, size_t size); + +Must be called to sync the IOMMU page tables for IOVA-range mapped by one or +more calls to ``dma_iova_link()``. + +For drivers that use a one-shot mapping, all ranges can be unmapped and the +IOVA freed by calling: + +:: + + void dma_iova_destroy(struct device *dev, struct dma_iova_state *state, + size_t mapped_len, enum dma_data_direction dir, + unsigned long attrs); + +Alternatively drivers can dynamically manage the IOVA space by unmapping +and mapping individual regions. In that case + +:: + + void dma_iova_unlink(struct device *dev, struct dma_iova_state *state, + size_t offset, size_t size, enum dma_data_direction dir, + unsigned long attrs); + +is used to unmap a range previously mapped, and + +:: + + void dma_iova_free(struct device *dev, struct dma_iova_state *state); + +is used to free the IOVA space. All regions must have been unmapped using +``dma_iova_unlink()`` before calling ``dma_iova_free()``. Part II - Non-coherent DMA allocations -------------------------------------- diff --git a/Documentation/core-api/genericirq.rst b/Documentation/core-api/genericirq.rst index 25f94dfd66fad..582bde9bf5a92 100644 --- a/Documentation/core-api/genericirq.rst +++ b/Documentation/core-api/genericirq.rst @@ -410,8 +410,6 @@ which are used in the generic IRQ layer. .. kernel-doc:: include/linux/interrupt.h :internal: -.. kernel-doc:: include/linux/irqdomain.h - Public Functions Provided ========================= diff --git a/Documentation/core-api/index.rst b/Documentation/core-api/index.rst index e9789bd381d80..7a4ca18ca6e2d 100644 --- a/Documentation/core-api/index.rst +++ b/Documentation/core-api/index.rst @@ -115,6 +115,7 @@ more memory-management documentation in Documentation/mm/index.rst. pin_user_pages boot-time-mm gfp_mask-from-fs-io + kho/index Interfaces for kernel debugging =============================== diff --git a/Documentation/core-api/irq/concepts.rst b/Documentation/core-api/irq/concepts.rst index 4273806a606bb..7c4564f3cbdfd 100644 --- a/Documentation/core-api/irq/concepts.rst +++ b/Documentation/core-api/irq/concepts.rst @@ -2,23 +2,24 @@ What is an IRQ? =============== -An IRQ is an interrupt request from a device. -Currently they can come in over a pin, or over a packet. -Several devices may be connected to the same pin thus -sharing an IRQ. +An IRQ is an interrupt request from a device. Currently, they can come +in over a pin, or over a packet. Several devices may be connected to +the same pin thus sharing an IRQ. Such as on legacy PCI bus: All devices +typically share 4 lanes/pins. Note that each device can request an +interrupt on each of the lanes. An IRQ number is a kernel identifier used to talk about a hardware -interrupt source. Typically this is an index into the global irq_desc -array, but except for what linux/interrupt.h implements the details -are architecture specific. +interrupt source. Typically, this is an index into the global irq_desc +array or sparse_irqs tree. But except for what linux/interrupt.h +implements, the details are architecture specific. An IRQ number is an enumeration of the possible interrupt sources on a -machine. Typically what is enumerated is the number of input pins on -all of the interrupt controller in the system. In the case of ISA -what is enumerated are the 16 input pins on the two i8259 interrupt -controllers. +machine. Typically, what is enumerated is the number of input pins on +all of the interrupt controllers in the system. In the case of ISA, +what is enumerated are the 8 input pins on each of the two i8259 +interrupt controllers. Architectures can assign additional meaning to the IRQ numbers, and -are encouraged to in the case where there is any manual configuration -of the hardware involved. The ISA IRQs are a classic example of +are encouraged to in the case where there is any manual configuration +of the hardware involved. The ISA IRQs are a classic example of assigning this kind of additional meaning. diff --git a/Documentation/core-api/irq/irq-domain.rst b/Documentation/core-api/irq/irq-domain.rst index f88a6ee67a350..a01c6ead1bc04 100644 --- a/Documentation/core-api/irq/irq-domain.rst +++ b/Documentation/core-api/irq/irq-domain.rst @@ -1,59 +1,77 @@ =============================================== -The irq_domain interrupt number mapping library +The irq_domain Interrupt Number Mapping Library =============================================== The current design of the Linux kernel uses a single large number -space where each separate IRQ source is assigned a different number. -This is simple when there is only one interrupt controller, but in -systems with multiple interrupt controllers the kernel must ensure +space where each separate IRQ source is assigned a unique number. +This is simple when there is only one interrupt controller. But in +systems with multiple interrupt controllers, the kernel must ensure that each one gets assigned non-overlapping allocations of Linux IRQ numbers. The number of interrupt controllers registered as unique irqchips -show a rising tendency: for example subdrivers of different kinds +shows a rising tendency. For example, subdrivers of different kinds such as GPIO controllers avoid reimplementing identical callback mechanisms as the IRQ core system by modelling their interrupt -handlers as irqchips, i.e. in effect cascading interrupt controllers. +handlers as irqchips. I.e. in effect cascading interrupt controllers. -Here the interrupt number loose all kind of correspondence to -hardware interrupt numbers: whereas in the past, IRQ numbers could -be chosen so they matched the hardware IRQ line into the root -interrupt controller (i.e. the component actually fireing the -interrupt line to the CPU) nowadays this number is just a number. +So in the past, IRQ numbers could be chosen so that they match the +hardware IRQ line into the root interrupt controller (i.e. the +component actually firing the interrupt line to the CPU). Nowadays, +this number is just a number and the number loose all kind of +correspondence to hardware interrupt numbers. -For this reason we need a mechanism to separate controller-local -interrupt numbers, called hardware irq's, from Linux IRQ numbers. +For this reason, we need a mechanism to separate controller-local +interrupt numbers, called hardware IRQs, from Linux IRQ numbers. The irq_alloc_desc*() and irq_free_desc*() APIs provide allocation of -irq numbers, but they don't provide any support for reverse mapping of +IRQ numbers, but they don't provide any support for reverse mapping of the controller-local IRQ (hwirq) number into the Linux IRQ number space. -The irq_domain library adds mapping between hwirq and IRQ numbers on -top of the irq_alloc_desc*() API. An irq_domain to manage mapping is -preferred over interrupt controller drivers open coding their own +The irq_domain library adds a mapping between hwirq and IRQ numbers on +top of the irq_alloc_desc*() API. An irq_domain to manage the mapping +is preferred over interrupt controller drivers open coding their own reverse mapping scheme. -irq_domain also implements translation from an abstract irq_fwspec -structure to hwirq numbers (Device Tree and ACPI GSI so far), and can -be easily extended to support other IRQ topology data sources. +irq_domain also implements a translation from an abstract struct +irq_fwspec to hwirq numbers (Device Tree, non-DT firmware node, ACPI +GSI, and software node so far), and can be easily extended to support +other IRQ topology data sources. The implementation is performed +without any extra platform support code. -irq_domain usage +irq_domain Usage ================ - -An interrupt controller driver creates and registers an irq_domain by -calling one of the irq_domain_add_*() or irq_domain_create_*() functions -(each mapping method has a different allocator function, more on that later). -The function will return a pointer to the irq_domain on success. The caller -must provide the allocator function with an irq_domain_ops structure. +struct irq_domain could be defined as an irq domain controller. That +is, it handles the mapping between hardware and virtual interrupt +numbers for a given interrupt domain. The domain structure is +generally created by the PIC code for a given PIC instance (though a +domain can cover more than one PIC if they have a flat number model). +It is the domain callbacks that are responsible for setting the +irq_chip on a given irq_desc after it has been mapped. + +The host code and data structures use a fwnode_handle pointer to +identify the domain. In some cases, and in order to preserve source +code compatibility, this fwnode pointer is "upgraded" to a DT +device_node. For those firmware infrastructures that do not provide a +unique identifier for an interrupt controller, the irq_domain code +offers a fwnode allocator. + +An interrupt controller driver creates and registers a struct irq_domain +by calling one of the irq_domain_create_*() functions (each mapping +method has a different allocator function, more on that later). The +function will return a pointer to the struct irq_domain on success. The +caller must provide the allocator function with a struct irq_domain_ops +pointer. In most cases, the irq_domain will begin empty without any mappings between hwirq and IRQ numbers. Mappings are added to the irq_domain by calling irq_create_mapping() which accepts the irq_domain and a -hwirq number as arguments. If a mapping for the hwirq doesn't already -exist then it will allocate a new Linux irq_desc, associate it with -the hwirq, and call the .map() callback so the driver can perform any -required hardware setup. +hwirq number as arguments. If a mapping for the hwirq doesn't already +exist, irq_create_mapping() allocates a new Linux irq_desc, associates +it with the hwirq, and calls the :c:member:`irq_domain_ops.map()` +callback. In there, the driver can perform any required hardware +setup. Once a mapping has been established, it can be retrieved or used via a variety of methods: @@ -63,8 +81,6 @@ variety of methods: mapping. - irq_find_mapping() returns a Linux IRQ number for a given domain and hwirq number, and 0 if there was no mapping -- irq_linear_revmap() is now identical to irq_find_mapping(), and is - deprecated - generic_handle_domain_irq() handles an interrupt described by a domain and a hwirq number @@ -77,9 +93,10 @@ be allocated. If the driver has the Linux IRQ number or the irq_data pointer, and needs to know the associated hwirq number (such as in the irq_chip -callbacks) then it can be directly obtained from irq_data->hwirq. +callbacks) then it can be directly obtained from +:c:member:`irq_data.hwirq`. -Types of irq_domain mappings +Types of irq_domain Mappings ============================ There are several mechanisms available for reverse mapping from hwirq @@ -92,7 +109,6 @@ Linear :: - irq_domain_add_linear() irq_domain_create_linear() The linear reverse map maintains a fixed size table indexed by the @@ -105,19 +121,13 @@ map are fixed time lookup for IRQ numbers, and irq_descs are only allocated for in-use IRQs. The disadvantage is that the table must be as large as the largest possible hwirq number. -irq_domain_add_linear() and irq_domain_create_linear() are functionally -equivalent, except for the first argument is different - the former -accepts an Open Firmware specific 'struct device_node', while the latter -accepts a more general abstraction 'struct fwnode_handle'. - -The majority of drivers should use the linear map. +The majority of drivers should use the Linear map. Tree ---- :: - irq_domain_add_tree() irq_domain_create_tree() The irq_domain maintains a radix tree map from hwirq numbers to Linux @@ -129,11 +139,6 @@ since it doesn't need to allocate a table as large as the largest hwirq number. The disadvantage is that hwirq to IRQ number lookup is dependent on how many entries are in the table. -irq_domain_add_tree() and irq_domain_create_tree() are functionally -equivalent, except for the first argument is different - the former -accepts an Open Firmware specific 'struct device_node', while the latter -accepts a more general abstraction 'struct fwnode_handle'. - Very few drivers should need this mapping. No Map @@ -141,7 +146,7 @@ No Map :: - irq_domain_add_nomap() + irq_domain_create_nomap() The No Map mapping is to be used when the hwirq number is programmable in the hardware. In this case it is best to program the @@ -159,8 +164,6 @@ Legacy :: - irq_domain_add_simple() - irq_domain_add_legacy() irq_domain_create_simple() irq_domain_create_legacy() @@ -189,13 +192,13 @@ supported. For example, ISA controllers would use the legacy map for mapping Linux IRQs 0-15 so that existing ISA drivers get the correct IRQ numbers. -Most users of legacy mappings should use irq_domain_add_simple() or -irq_domain_create_simple() which will use a legacy domain only if an IRQ range -is supplied by the system and will otherwise use a linear domain mapping. -The semantics of this call are such that if an IRQ range is specified then -descriptors will be allocated on-the-fly for it, and if no range is -specified it will fall through to irq_domain_add_linear() or -irq_domain_create_linear() which means *no* irq descriptors will be allocated. +Most users of legacy mappings should use irq_domain_create_simple() +which will use a legacy domain only if an IRQ range is supplied by the +system and will otherwise use a linear domain mapping. The semantics of +this call are such that if an IRQ range is specified then descriptors +will be allocated on-the-fly for it, and if no range is specified it +will fall through to irq_domain_create_linear() which means *no* irq +descriptors will be allocated. A typical use case for simple domains is where an irqchip provider is supporting both dynamic and static IRQ assignments. @@ -206,13 +209,7 @@ that the driver using the simple domain call irq_create_mapping() before any irq_find_mapping() since the latter will actually work for the static IRQ assignment case. -irq_domain_add_simple() and irq_domain_create_simple() as well as -irq_domain_add_legacy() and irq_domain_create_legacy() are functionally -equivalent, except for the first argument is different - the former -accepts an Open Firmware specific 'struct device_node', while the latter -accepts a more general abstraction 'struct fwnode_handle'. - -Hierarchy IRQ domain +Hierarchy IRQ Domain -------------------- On some architectures, there may be multiple interrupt controllers @@ -253,20 +250,40 @@ There are four major interfaces to use hierarchy irq_domain: 4) irq_domain_deactivate_irq(): deactivate interrupt controller hardware to stop delivering the interrupt. -Following changes are needed to support hierarchy irq_domain: +The following is needed to support hierarchy irq_domain: -1) a new field 'parent' is added to struct irq_domain; it's used to +1) The :c:member:`parent` field in struct irq_domain is used to maintain irq_domain hierarchy information. -2) a new field 'parent_data' is added to struct irq_data; it's used to - build hierarchy irq_data to match hierarchy irq_domains. The irq_data - is used to store irq_domain pointer and hardware irq number. -3) new callbacks are added to struct irq_domain_ops to support hierarchy - irq_domain operations. - -With support of hierarchy irq_domain and hierarchy irq_data ready, an -irq_domain structure is built for each interrupt controller, and an +2) The :c:member:`parent_data` field in struct irq_data is used to + build hierarchy irq_data to match hierarchy irq_domains. The + irq_data is used to store irq_domain pointer and hardware irq + number. +3) The :c:member:`alloc()`, :c:member:`free()`, and other callbacks in + struct irq_domain_ops to support hierarchy irq_domain operations. + +With the support of hierarchy irq_domain and hierarchy irq_data ready, +an irq_domain structure is built for each interrupt controller, and an irq_data structure is allocated for each irq_domain associated with an -IRQ. Now we could go one step further to support stacked(hierarchy) +IRQ. + +For an interrupt controller driver to support hierarchy irq_domain, it +needs to: + +1) Implement irq_domain_ops.alloc() and irq_domain_ops.free() +2) Optionally, implement irq_domain_ops.activate() and + irq_domain_ops.deactivate(). +3) Optionally, implement an irq_chip to manage the interrupt controller + hardware. +4) There is no need to implement irq_domain_ops.map() and + irq_domain_ops.unmap(). They are unused with hierarchy irq_domain. + +Note the hierarchy irq_domain is in no way x86-specific, and is +heavily used to support other architectures, such as ARM, ARM64 etc. + +Stacked irq_chip +~~~~~~~~~~~~~~~~ + +Now, we could go one step further to support stacked (hierarchy) irq_chip. That is, an irq_chip is associated with each irq_data along the hierarchy. A child irq_chip may implement a required action by itself or by cooperating with its parent irq_chip. @@ -276,22 +293,28 @@ with the hardware managed by itself and may ask for services from its parent irq_chip when needed. So we could achieve a much cleaner software architecture. -For an interrupt controller driver to support hierarchy irq_domain, it -needs to: - -1) Implement irq_domain_ops.alloc and irq_domain_ops.free -2) Optionally implement irq_domain_ops.activate and - irq_domain_ops.deactivate. -3) Optionally implement an irq_chip to manage the interrupt controller - hardware. -4) No need to implement irq_domain_ops.map and irq_domain_ops.unmap, - they are unused with hierarchy irq_domain. - -Hierarchy irq_domain is in no way x86 specific, and is heavily used to -support other architectures, such as ARM, ARM64 etc. - Debugging ========= Most of the internals of the IRQ subsystem are exposed in debugfs by turning CONFIG_GENERIC_IRQ_DEBUGFS on. + +Structures and Public Functions Provided +======================================== + +This chapter contains the autogenerated documentation of the structures +and exported kernel API functions which are used for IRQ domains. + +.. kernel-doc:: include/linux/irqdomain.h + +.. kernel-doc:: kernel/irq/irqdomain.c + :export: + +Internal Functions Provided +=========================== + +This chapter contains the autogenerated documentation of the internal +functions. + +.. kernel-doc:: kernel/irq/irqdomain.c + :internal: diff --git a/Documentation/core-api/kho/bindings/kho.yaml b/Documentation/core-api/kho/bindings/kho.yaml new file mode 100644 index 0000000000000..11e8ab7b219d9 --- /dev/null +++ b/Documentation/core-api/kho/bindings/kho.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +title: Kexec HandOver (KHO) root tree + +maintainers: + - Mike Rapoport + - Changyuan Lyu + +description: | + System memory preserved by KHO across kexec. + +properties: + compatible: + enum: + - kho-v1 + + preserved-memory-map: + description: | + physical address (u64) of an in-memory structure describing all preserved + folios and memory ranges. + +patternProperties: + "$[0-9a-f_]+^": + $ref: sub-fdt.yaml# + description: physical address of a KHO user's own FDT. + +required: + - compatible + - preserved-memory-map + +additionalProperties: false + +examples: + - | + kho { + compatible = "kho-v1"; + preserved-memory-map = <0xf0be16 0x1000000>; + + memblock { + fdt = <0x80cc16 0x1000000>; + }; + }; diff --git a/Documentation/core-api/kho/bindings/memblock/memblock.yaml b/Documentation/core-api/kho/bindings/memblock/memblock.yaml new file mode 100644 index 0000000000000..d388c28eb91d1 --- /dev/null +++ b/Documentation/core-api/kho/bindings/memblock/memblock.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +title: Memblock reserved memory + +maintainers: + - Mike Rapoport + +description: | + Memblock can serialize its current memory reservations created with + reserve_mem command line option across kexec through KHO. + The post-KHO kernel can then consume these reservations and they are + guaranteed to have the same physical address. + +properties: + compatible: + enum: + - reserve-mem-v1 + +patternProperties: + "$[0-9a-f_]+^": + $ref: reserve-mem.yaml# + description: reserved memory regions + +required: + - compatible + +additionalProperties: false + +examples: + - | + memblock { + compatible = "memblock-v1"; + n1 { + compatible = "reserve-mem-v1"; + start = <0xc06b 0x4000000>; + size = <0x04 0x00>; + }; + }; diff --git a/Documentation/core-api/kho/bindings/memblock/reserve-mem.yaml b/Documentation/core-api/kho/bindings/memblock/reserve-mem.yaml new file mode 100644 index 0000000000000..10282d3d1bcdc --- /dev/null +++ b/Documentation/core-api/kho/bindings/memblock/reserve-mem.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +title: Memblock reserved memory regions + +maintainers: + - Mike Rapoport + +description: | + Memblock can serialize its current memory reservations created with + reserve_mem command line option across kexec through KHO. + This object describes each such region. + +properties: + compatible: + enum: + - reserve-mem-v1 + + start: + description: | + physical address (u64) of the reserved memory region. + + size: + description: | + size (u64) of the reserved memory region. + +required: + - compatible + - start + - size + +additionalProperties: false + +examples: + - | + n1 { + compatible = "reserve-mem-v1"; + start = <0xc06b 0x4000000>; + size = <0x04 0x00>; + }; diff --git a/Documentation/core-api/kho/bindings/sub-fdt.yaml b/Documentation/core-api/kho/bindings/sub-fdt.yaml new file mode 100644 index 0000000000000..b9a3d2d248501 --- /dev/null +++ b/Documentation/core-api/kho/bindings/sub-fdt.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +title: KHO users' FDT address + +maintainers: + - Mike Rapoport + - Changyuan Lyu + +description: | + Physical address of an FDT blob registered by a KHO user. + +properties: + fdt: + description: | + physical address (u64) of an FDT blob. + +required: + - fdt + +additionalProperties: false + +examples: + - | + memblock { + fdt = <0x80cc16 0x1000000>; + }; diff --git a/Documentation/core-api/kho/concepts.rst b/Documentation/core-api/kho/concepts.rst new file mode 100644 index 0000000000000..36d5c05cfb307 --- /dev/null +++ b/Documentation/core-api/kho/concepts.rst @@ -0,0 +1,74 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later +.. _kho-concepts: + +======================= +Kexec Handover Concepts +======================= + +Kexec HandOver (KHO) is a mechanism that allows Linux to preserve memory +regions, which could contain serialized system states, across kexec. + +It introduces multiple concepts: + +KHO FDT +======= + +Every KHO kexec carries a KHO specific flattened device tree (FDT) blob +that describes preserved memory regions. These regions contain either +serialized subsystem states, or in-memory data that shall not be touched +across kexec. After KHO, subsystems can retrieve and restore preserved +memory regions from KHO FDT. + +KHO only uses the FDT container format and libfdt library, but does not +adhere to the same property semantics that normal device trees do: Properties +are passed in native endianness and standardized properties like ``regs`` and +``ranges`` do not exist, hence there are no ``#...-cells`` properties. + +KHO is still under development. The FDT schema is unstable and would change +in the future. + +Scratch Regions +=============== + +To boot into kexec, we need to have a physically contiguous memory range that +contains no handed over memory. Kexec then places the target kernel and initrd +into that region. The new kernel exclusively uses this region for memory +allocations before during boot up to the initialization of the page allocator. + +We guarantee that we always have such regions through the scratch regions: On +first boot KHO allocates several physically contiguous memory regions. Since +after kexec these regions will be used by early memory allocations, there is a +scratch region per NUMA node plus a scratch region to satisfy allocations +requests that do not require particular NUMA node assignment. +By default, size of the scratch region is calculated based on amount of memory +allocated during boot. The ``kho_scratch`` kernel command line option may be +used to explicitly define size of the scratch regions. +The scratch regions are declared as CMA when page allocator is initialized so +that their memory can be used during system lifetime. CMA gives us the +guarantee that no handover pages land in that region, because handover pages +must be at a static physical memory location and CMA enforces that only +movable pages can be located inside. + +After KHO kexec, we ignore the ``kho_scratch`` kernel command line option and +instead reuse the exact same region that was originally allocated. This allows +us to recursively execute any amount of KHO kexecs. Because we used this region +for boot memory allocations and as target memory for kexec blobs, some parts +of that memory region may be reserved. These reservations are irrelevant for +the next KHO, because kexec can overwrite even the original kernel. + +.. _kho-finalization-phase: + +KHO finalization phase +====================== + +To enable user space based kexec file loader, the kernel needs to be able to +provide the FDT that describes the current kernel's state before +performing the actual kexec. The process of generating that FDT is +called serialization. When the FDT is generated, some properties +of the system may become immutable because they are already written down +in the FDT. That state is called the KHO finalization phase. + +Public API +========== +.. kernel-doc:: kernel/kexec_handover.c + :export: diff --git a/Documentation/core-api/kho/fdt.rst b/Documentation/core-api/kho/fdt.rst new file mode 100644 index 0000000000000..62505285d60d6 --- /dev/null +++ b/Documentation/core-api/kho/fdt.rst @@ -0,0 +1,80 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +======= +KHO FDT +======= + +KHO uses the flattened device tree (FDT) container format and libfdt +library to create and parse the data that is passed between the +kernels. The properties in KHO FDT are stored in native format. +It includes the physical address of an in-memory structure describing +all preserved memory regions, as well as physical addresses of KHO users' +own FDTs. Interpreting those sub FDTs is the responsibility of KHO users. + +KHO nodes and properties +======================== + +Property ``preserved-memory-map`` +--------------------------------- + +KHO saves a special property named ``preserved-memory-map`` under the root node. +This node contains the physical address of an in-memory structure for KHO to +preserve memory regions across kexec. + +Property ``compatible`` +----------------------- + +The ``compatible`` property determines compatibility between the kernel +that created the KHO FDT and the kernel that attempts to load it. +If the kernel that loads the KHO FDT is not compatible with it, the entire +KHO process will be bypassed. + +Property ``fdt`` +---------------- + +Generally, a KHO user serialize its state into its own FDT and instructs +KHO to preserve the underlying memory, such that after kexec, the new kernel +can recover its state from the preserved FDT. + +A KHO user thus can create a node in KHO root tree and save the physical address +of its own FDT in that node's property ``fdt`` . + +Examples +======== + +The following example demonstrates KHO FDT that preserves two memory +regions created with ``reserve_mem`` kernel command line parameter:: + + /dts-v1/; + + / { + compatible = "kho-v1"; + + preserved-memory-map = <0x40be16 0x1000000>; + + memblock { + fdt = <0x1517 0x1000000>; + }; + }; + +where the ``memblock`` node contains an FDT that is requested by the +subsystem memblock for preservation. The FDT contains the following +serialized data:: + + /dts-v1/; + + / { + compatible = "memblock-v1"; + + n1 { + compatible = "reserve-mem-v1"; + start = <0xc06b 0x4000000>; + size = <0x04 0x00>; + }; + + n2 { + compatible = "reserve-mem-v1"; + start = <0xc067 0x4000000>; + size = <0x04 0x00>; + }; + }; diff --git a/Documentation/core-api/kho/index.rst b/Documentation/core-api/kho/index.rst new file mode 100644 index 0000000000000..0c63b0c5c1436 --- /dev/null +++ b/Documentation/core-api/kho/index.rst @@ -0,0 +1,13 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +======================== +Kexec Handover Subsystem +======================== + +.. toctree:: + :maxdepth: 1 + + concepts + fdt + +.. only:: subproject and html diff --git a/Documentation/core-api/printk-formats.rst b/Documentation/core-api/printk-formats.rst index 4bdc394e86af4..4b7f3646ec6ce 100644 --- a/Documentation/core-api/printk-formats.rst +++ b/Documentation/core-api/printk-formats.rst @@ -571,9 +571,8 @@ struct clk :: %pC pll1 - %pCn pll1 -For printing struct clk structures. %pC and %pCn print the name of the clock +For printing struct clk structures. %pC prints the name of the clock (Common Clock Framework) or a unique 32-bit ID (legacy clock framework). Passed by reference. @@ -648,6 +647,38 @@ Examples:: %p4cc Y10 little-endian (0x20303159) %p4cc NV12 big-endian (0xb231564e) +Generic FourCC code +------------------- + +:: + %p4c[h[R]lb] gP00 (0x67503030) + +Print a generic FourCC code, as both ASCII characters and its numerical +value as hexadecimal. + +The generic FourCC code is always printed in the big-endian format, +the most significant byte first. This is the opposite of V4L/DRM FourCCs. + +The additional ``h``, ``hR``, ``l``, and ``b`` specifiers define what +endianness is used to load the stored bytes. The data might be interpreted +using the host, reversed host byte order, little-endian, or big-endian. + +Passed by reference. + +Examples for a little-endian machine, given &(u32)0x67503030:: + + %p4ch gP00 (0x67503030) + %p4chR 00Pg (0x30305067) + %p4cl gP00 (0x67503030) + %p4cb 00Pg (0x30305067) + +Examples for a big-endian machine, given &(u32)0x67503030:: + + %p4ch gP00 (0x67503030) + %p4chR 00Pg (0x30305067) + %p4cl 00Pg (0x30305067) + %p4cb gP00 (0x67503030) + Rust ---- diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 8c75754554224..30c44a0e64074 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -47,6 +47,7 @@ properties: - novtech,chameleon96 - samtec,vining - terasic,de0-atlas + - terasic,de10-nano - terasic,socfpga-cyclone5-sockit - const: altr,socfpga-cyclone5 - const: altr,socfpga diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml b/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml index 5723813066811..a758f4bb2bb31 100644 --- a/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml @@ -9,20 +9,120 @@ title: Altera SOCFPGA Clock Manager maintainers: - Dinh Nguyen -description: test +description: + This binding describes the Altera SOCFGPA Clock Manager and its associated + tree of clocks, pll's, and clock gates for the Cyclone5, Arria5 and Arria10 + chip families. properties: compatible: items: - const: altr,clk-mgr + reg: maxItems: 1 + clocks: + type: object + additionalProperties: false + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + "^osc[0-9]$": + type: object + + "^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$": + type: object + $ref: '#/$defs/clock-props' + unevaluatedProperties: false + + properties: + compatible: + enum: + - altr,socfpga-pll-clock + - altr,socfpga-perip-clk + - altr,socfpga-gate-clk + - altr,socfpga-a10-pll-clock + - altr,socfpga-a10-perip-clk + - altr,socfpga-a10-gate-clk + - fixed-clock + + clocks: + description: one or more phandles to input clock + minItems: 1 + maxItems: 5 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + "^[a-z0-9,_]+(clk|pll)(@[a-f0-9]+)?$": + type: object + $ref: '#/$defs/clock-props' + unevaluatedProperties: false + + properties: + compatible: + enum: + - altr,socfpga-perip-clk + - altr,socfpga-gate-clk + - altr,socfpga-a10-perip-clk + - altr,socfpga-a10-gate-clk + + clocks: + description: one or more phandles to input clock + minItems: 1 + maxItems: 4 + + required: + - compatible + - clocks + - "#clock-cells" + + required: + - compatible + - "#clock-cells" + required: - compatible + - reg additionalProperties: false +$defs: + clock-props: + properties: + reg: + maxItems: 1 + + "#clock-cells": + const: 0 + + clk-gate: + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: gating register offset + - description: bit index + + div-reg: + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: divider register offset + - description: bit shift + - description: bit width + + fixed-divider: + $ref: /schemas/types.yaml#/definitions/uint32 + examples: - | clkmgr@ffd04000 { diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 0647851ae1f55..05edf22e6c303 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -27,6 +27,7 @@ properties: items: - enum: - minix,neo-x8 + - tcu,fernsehfee3 - const: amlogic,meson8 - description: Boards with the Amlogic Meson8m2 SoC @@ -73,6 +74,13 @@ properties: - const: amlogic,s805x - const: amlogic,meson-gxl + - description: Boards with the Amlogic Meson GXL S805Y SoC + items: + - enum: + - xiaomi,aquaman + - const: amlogic,s805y + - const: amlogic,meson-gxl + - description: Boards with the Amlogic Meson GXL S905W SoC items: - enum: @@ -237,6 +245,24 @@ properties: - amlogic,aq222 - const: amlogic,s4 + - description: Boards with the Amlogic S6 S905X5 SoC + items: + - enum: + - amlogic,bl209 + - const: amlogic,s6 + + - description: Boards with the Amlogic S7 S805X3 SoC + items: + - enum: + - amlogic,bp201 + - const: amlogic,s7 + + - description: Boards with the Amlogic S7D S905X5M SoC + items: + - enum: + - amlogic,bm202 + - const: amlogic,s7d + - description: Boards with the Amlogic T7 A311D2 SoC items: - enum: diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml index e4ff71f006b8c..2729a542c4f35 100644 --- a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml @@ -52,6 +52,7 @@ properties: - description: BCM2837 based Boards items: - enum: + - raspberrypi,2-model-b-rev2 - raspberrypi,3-model-a-plus - raspberrypi,3-model-b - raspberrypi,3-model-b-plus diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 2e666b2a4dcda..2e9ab95830050 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -10,9 +10,9 @@ maintainers: - Lorenzo Pieralisi description: |+ - The device tree allows to describe the layout of CPUs in a system through - the "cpus" node, which in turn contains a number of subnodes (ie "cpu") - defining properties for every cpu. + The device tree allows to describe the layout of CPUs in a system through the + "cpus" node, which in turn contains a number of subnodes (ie "cpu") defining + properties for every cpu. Bindings for CPU nodes follow the Devicetree Specification, available from: @@ -41,45 +41,40 @@ description: |+ properties: reg: maxItems: 1 - description: | - Usage and definition depend on ARM architecture version and - configuration: + description: > + Usage and definition depend on ARM architecture version and configuration: - On uniprocessor ARM architectures previous to v7 - this property is required and must be set to 0. + On uniprocessor ARM architectures previous to v7 this property is required + and must be set to 0. - On ARM 11 MPcore based systems this property is - required and matches the CPUID[11:0] register bits. + On ARM 11 MPcore based systems this property is required and matches the + CPUID[11:0] register bits. - Bits [11:0] in the reg cell must be set to - bits [11:0] in CPU ID register. + Bits [11:0] in the reg cell must be set to bits [11:0] in CPU ID register. All other bits in the reg cell must be set to 0. - On 32-bit ARM v7 or later systems this property is - required and matches the CPU MPIDR[23:0] register - bits. + On 32-bit ARM v7 or later systems this property is required and matches + the CPU MPIDR[23:0] register bits. - Bits [23:0] in the reg cell must be set to - bits [23:0] in MPIDR. + Bits [23:0] in the reg cell must be set to bits [23:0] in MPIDR. All other bits in the reg cell must be set to 0. - On ARM v8 64-bit systems this property is required - and matches the MPIDR_EL1 register affinity bits. + On ARM v8 64-bit systems this property is required and matches the + MPIDR_EL1 register affinity bits. * If cpus node's #address-cells property is set to 2 - The first reg cell bits [7:0] must be set to - bits [39:32] of MPIDR_EL1. + The first reg cell bits [7:0] must be set to bits [39:32] of + MPIDR_EL1. - The second reg cell bits [23:0] must be set to - bits [23:0] of MPIDR_EL1. + The second reg cell bits [23:0] must be set to bits [23:0] of + MPIDR_EL1. * If cpus node's #address-cells property is set to 1 - The reg cell bits [23:0] must be set to bits [23:0] - of MPIDR_EL1. + The reg cell bits [23:0] must be set to bits [23:0] of MPIDR_EL1. All other bits in the reg cells must be set to 0. @@ -273,103 +268,122 @@ properties: description: The DT specification defines this as 64-bit always, but some 32-bit Arm systems have used a 32-bit value which must be supported. - Required for systems that have an "enable-method" - property value of "spin-table". cpu-idle-states: $ref: /schemas/types.yaml#/definitions/phandle-array items: maxItems: 1 - description: | - List of phandles to idle state nodes supported - by this cpu (see ./idle-states.yaml). + description: + List of phandles to idle state nodes supported by this cpu (see + ./idle-states.yaml). capacity-dmips-mhz: description: u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in - DMIPS/MHz, relative to highest capacity-dmips-mhz - in the system. + DMIPS/MHz, relative to highest capacity-dmips-mhz in the system. cci-control-port: true dynamic-power-coefficient: $ref: /schemas/types.yaml#/definitions/uint32 - description: - A u32 value that represents the running time dynamic - power coefficient in units of uW/MHz/V^2. The - coefficient can either be calculated from power + description: > + A u32 value that represents the running time dynamic power coefficient in + units of uW/MHz/V^2. The coefficient can either be calculated from power measurements or derived by analysis. - The dynamic power consumption of the CPU is - proportional to the square of the Voltage (V) and - the clock frequency (f). The coefficient is used to + The dynamic power consumption of the CPU is proportional to the square of + the Voltage (V) and the clock frequency (f). The coefficient is used to calculate the dynamic power as below - Pdyn = dynamic-power-coefficient * V^2 * f where voltage is in V, frequency is in MHz. + interconnects: + minItems: 1 + maxItems: 3 + + nvmem-cells: + maxItems: 1 + + nvmem-cell-names: + const: speed_grade + performance-domains: maxItems: 1 - description: - List of phandles and performance domain specifiers, as defined by - bindings of the performance domain provider. See also - dvfs/performance-domain.yaml. power-domains: - description: - List of phandles and PM domain specifiers, as defined by bindings of the - PM domain provider (see also ../power_domain.txt). + minItems: 1 + maxItems: 2 power-domain-names: description: - A list of power domain name strings sorted in the same order as the - power-domains property. - For PSCI based platforms, the name corresponding to the index of the PSCI PM domain provider, must be "psci". For SCMI based platforms, the name corresponding to the index of an SCMI performance domain provider, must be "perf". + minItems: 1 + maxItems: 2 + items: + enum: [ psci, perf, cpr ] - qcom,saw: - $ref: /schemas/types.yaml#/definitions/phandle - description: | - Specifies the SAW* node associated with this CPU. + resets: + maxItems: 1 - Required for systems that have an "enable-method" property - value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2" + arm-supply: + deprecated: true + description: Use 'cpu-supply' instead - * arm/msm/qcom,saw2.txt + cpu0-supply: + deprecated: true + description: Use 'cpu-supply' instead - qcom,acc: + mem-supply: true + + proc-supply: + deprecated: true + description: Use 'cpu-supply' instead + + sram-supply: + deprecated: true + description: Use 'mem-supply' instead + + mediatek,cci: $ref: /schemas/types.yaml#/definitions/phandle - description: | - Specifies the ACC* node associated with this CPU. + description: Link to Mediatek Cache Coherent Interconnect - Required for systems that have an "enable-method" property - value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or - "qcom,msm8916-smp". + qcom,saw: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Specifies the SAW node associated with this CPU. - * arm/msm/qcom,kpss-acc.txt + qcom,acc: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Specifies the ACC node associated with this CPU. + + qcom,freq-domain: + description: Specifies the QCom CPUFREQ HW associated with the CPU. + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 rockchip,pmu: $ref: /schemas/types.yaml#/definitions/phandle - description: | + description: > Specifies the syscon node controlling the cpu core power domains. - Optional for systems that have an "enable-method" - property value of "rockchip,rk3066-smp" - While optional, it is the preferred way to get access to - the cpu-core power-domains. + Optional for systems that have an "enable-method" property value of + "rockchip,rk3066-smp". While optional, it is the preferred way to get + access to the cpu-core power-domains. secondary-boot-reg: $ref: /schemas/types.yaml#/definitions/uint32 - description: | + description: > Required for systems that have an "enable-method" property value of "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp". - This includes the following SoCs: | - BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550 + This includes the following SoCs: + BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550, BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 The secondary-boot-reg property is a u32 value that specifies the @@ -378,22 +392,66 @@ properties: formed by encoding the target CPU id into the low bits of the physical start address it should jump to. -if: - # If the enable-method property contains one of those values - properties: - enable-method: - contains: - enum: - - brcm,bcm11351-cpu-method - - brcm,bcm23550 - - brcm,bcm-nsp-smp - # and if enable-method is present - required: - - enable-method - -then: - required: - - secondary-boot-reg + thermal-idle: + type: object + +allOf: + - $ref: /schemas/cpu.yaml# + - $ref: /schemas/opp/opp-v1.yaml# + - if: + # If the enable-method property contains one of those values + properties: + enable-method: + contains: + enum: + - brcm,bcm11351-cpu-method + - brcm,bcm23550 + - brcm,bcm-nsp-smp + # and if enable-method is present + required: + - enable-method + then: + required: + - secondary-boot-reg + - if: + properties: + enable-method: + enum: + - spin-table + - renesas,r9a06g032-smp + required: + - enable-method + then: + required: + - cpu-release-addr + - if: + properties: + enable-method: + enum: + - qcom,kpss-acc-v1 + - qcom,kpss-acc-v2 + - qcom,msm8226-smp + - qcom,msm8916-smp + required: + - enable-method + then: + required: + - qcom,acc + - qcom,saw + else: + if: + # 2 Qualcomm platforms bootloaders need qcom,acc and qcom,saw yet use + # "spin-table" or "psci" enable-methods. Disallowing the properties for + # all other CPUs is the best we can do as there's not any way to + # distinguish these Qualcomm platforms. + not: + properties: + compatible: + const: arm,cortex-a53 + then: + properties: + qcom,acc: false + qcom,saw: false required: - device_type @@ -403,7 +461,7 @@ required: dependencies: rockchip,pmu: [enable-method] -additionalProperties: true +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,imx51-m4if.yaml b/Documentation/devicetree/bindings/arm/freescale/fsl,imx51-m4if.yaml new file mode 100644 index 0000000000000..1f515bea39599 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,imx51-m4if.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/freescale/fsl,imx51-m4if.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Multi Master Multi Memory Interface (M4IF) and Tigerp module + +description: collect the imx devices, which only have compatible and reg property + +maintainers: + - Frank Li + +properties: + compatible: + oneOf: + - enum: + - fsl,imx51-m4if + - fsl,imx51-tigerp + - fsl,imx51-aipstz + - fsl,imx53-aipstz + - fsl,imx7d-pcie-phy + - items: + - const: fsl,imx53-tigerp + - const: fsl,imx51-tigerp + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + m4if@83fd8000 { + compatible = "fsl,imx51-m4if"; + reg = <0x83fd8000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/arm/freescale/m4if.txt b/Documentation/devicetree/bindings/arm/freescale/m4if.txt deleted file mode 100644 index 93bd7b867a536..0000000000000 --- a/Documentation/devicetree/bindings/arm/freescale/m4if.txt +++ /dev/null @@ -1,12 +0,0 @@ -* Freescale Multi Master Multi Memory Interface (M4IF) module - -Required properties: -- compatible : Should be "fsl,imx51-m4if" -- reg : Address and length of the register set for the device - -Example: - -m4if: m4if@83fd8000 { - compatible = "fsl,imx51-m4if"; - reg = <0x83fd8000 0x1000>; -}; diff --git a/Documentation/devicetree/bindings/arm/freescale/tigerp.txt b/Documentation/devicetree/bindings/arm/freescale/tigerp.txt deleted file mode 100644 index 19e2aad63d6ef..0000000000000 --- a/Documentation/devicetree/bindings/arm/freescale/tigerp.txt +++ /dev/null @@ -1,12 +0,0 @@ -* Freescale Tigerp platform module - -Required properties: -- compatible : Should be "fsl,imx51-tigerp" -- reg : Address and length of the register set for the device - -Example: - -tigerp: tigerp@83fa0000 { - compatible = "fsl,imx51-tigerp"; - reg = <0x83fa0000 0x28>; -}; diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 1b90870958a22..d3b5e6923e416 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1120,6 +1120,12 @@ properties: - const: avnet,sm2s-imx8mp # SM2S-IMX8PLUS SoM - const: fsl,imx8mp + - description: Boundary Devices Nitrogen8M Plus ENC Carrier Board + items: + - const: boundary,imx8mp-nitrogen-enc-carrier-board + - const: boundary,imx8mp-nitrogen-som + - const: fsl,imx8mp + - description: Boundary Device Nitrogen8MP Universal SMARC Carrier Board items: - const: boundary,imx8mp-nitrogen-smarc-universal-board @@ -1156,6 +1162,13 @@ properties: - const: kontron,imx8mp-osm-s # Kontron i.MX8MP OSM-S SoM - const: fsl,imx8mp + - description: PHYTEC phyCORE-i.MX8MP FPSC based boards + items: + - enum: + - phytec,imx8mp-libra-rdk-fpsc # i.MX 8M Plus Libra RDK + - const: phytec,imx8mp-phycore-fpsc # phyCORE-i.MX 8M Plus FPSC + - const: fsl,imx8mp + - description: PHYTEC phyCORE-i.MX8MP SoM based boards items: - const: phytec,imx8mp-phyboard-pollux-rdk # phyBOARD-Pollux RDK @@ -1176,6 +1189,12 @@ properties: - const: polyhex,imx8mp-debix-som-a # Polyhex Debix SOM A - const: fsl,imx8mp + - description: Toradex Boards with SMARC iMX8M Plus Modules + items: + - const: toradex,smarc-imx8mp-dev # Toradex SMARC iMX8M Plus on Toradex SMARC Development Board + - const: toradex,smarc-imx8mp # Toradex SMARC iMX8M Plus Module + - const: fsl,imx8mp + - description: Toradex Boards with Verdin iMX8M Plus Modules items: - enum: @@ -1333,6 +1352,22 @@ properties: - const: tq,imx8qxp-tqma8xqp # TQ-Systems GmbH TQMa8XQP SOM (with i.MX8QXP) - const: fsl,imx8qxp + - description: + TQMa8XxS is a series of SOM featuring NXP i.MX8X system-on-chip + variants. It has the SMARC-2.0 form factor and is designed to be placed on + different carrier boards. MB-SMARC-2 is a carrier reference design. + oneOf: + - items: + - enum: + - tq,imx8qxp-tqma8xqps-mb-smarc-2 # TQ-Systems GmbH TQMa8QXPS SOM on MB-SMARC-2 + - const: tq,imx8qxp-tqma8xqps # TQ-Systems GmbH TQMa8QXPS SOM + - const: fsl,imx8qxp + - items: + - enum: + - tq,imx8dxp-tqma8xdps-mb-smarc-2 # TQ-Systems GmbH TQMa8XDPS SOM on MB-SMARC-2 + - const: tq,imx8dxp-tqma8xdps # TQ-Systems GmbH TQMa8XDPS SOM + - const: fsl,imx8dxp + - description: i.MX8ULP based Boards items: - enum: @@ -1347,6 +1382,12 @@ properties: - fsl,imx93-14x14-evk # i.MX93 14x14 EVK Board - const: fsl,imx93 + - description: i.MX94 based Boards + items: + - enum: + - fsl,imx943-evk # i.MX943 EVK Board + - const: fsl,imx94 + - description: i.MX95 based Boards items: - enum: @@ -1374,12 +1415,16 @@ properties: All SOM and CPU variants use the same device tree hence only one compatible is needed. Bootloader disables all features not present in the assembled SOC. + MBa91xxCA mainboard can be used as starterkit for the SOM + soldered on an adapter board or for the connector variant + to evaluate RGB display support. MBa93xxCA mainboard can be used as starterkit for the SOM soldered on an adapter board or for the connector variant MBa93xxLA mainboard is a single board computer using the solderable SOM variant items: - enum: + - tq,imx93-tqma9352-mba91xxca # TQ-Systems GmbH i.MX93 TQMa93xxCA/LA SOM on MBa91xxCA - tq,imx93-tqma9352-mba93xxca # TQ-Systems GmbH i.MX93 TQMa93xxCA/LA SOM on MBa93xxCA - tq,imx93-tqma9352-mba93xxla # TQ-Systems GmbH i.MX93 TQMa93xxLA SOM on MBa93xxLA SBC - const: tq,imx93-tqma9352 # TQ-Systems GmbH i.MX93 TQMa93xxCA/LA SOM @@ -1387,8 +1432,10 @@ properties: - description: PHYTEC phyCORE-i.MX93 SoM based boards items: - - const: phytec,imx93-phyboard-segin # phyBOARD-Segin with i.MX93 - - const: phytec,imx93-phycore-som # phyCORE-i.MX93 SoM + - enum: + - phytec,imx93-phyboard-nash # phyBOARD-Nash-i.MX93 + - phytec,imx93-phyboard-segin # phyBOARD-Segin with i.MX93 + - const: phytec,imx93-phycore-som # phyCORE-i.MX93 SoM - const: fsl,imx93 - description: Variscite VAR-SOM-MX93 based boards @@ -1403,6 +1450,16 @@ properties: - const: kontron,imx93-osm-s # Kontron OSM-S i.MX93 SoM - const: fsl,imx93 + - description: + TQMa95xxSA is a series of SOM featuring NXP i.MX95 SoC variants. + It has the SMARC form factor and is designed to be placed on + different carrier boards. MB-SMARC-2 is a carrier reference design. + items: + - enum: + - tq,imx95-tqma9596sa-mb-smarc-2 # TQ-Systems GmbH i.MX95 TQMa95xxSA SOM on MB-SMARC-2 + - const: tq,imx95-tqma9596sa # TQ-Systems GmbH i.MX95 TQMa95xxSA SOM + - const: fsl,imx95 + - description: Freescale Vybrid Platform Device Tree Bindings diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml index 2ee0c740eb56d..c75cd7d29f1aa 100644 --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml @@ -25,6 +25,7 @@ properties: items: - enum: - intel,socfpga-agilex5-socdk + - intel,socfpga-agilex5-socdk-nand - const: intel,socfpga-agilex5 additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 108ae5e0185d9..a7e0a72f6e4cb 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -104,6 +104,10 @@ properties: - enum: - bananapi,bpi-r4 - const: mediatek,mt7988a + - items: + - const: bananapi,bpi-r4-2g5 + - const: bananapi,bpi-r4 + - const: mediatek,mt7988a - items: - enum: - mediatek,mt8127-moose @@ -285,6 +289,13 @@ properties: - const: google,steelix-sku393218 - const: google,steelix - const: mediatek,mt8186 + - description: Google Ponyta + items: + - enum: + - google,ponyta-sku0 + - google,ponyta-sku1 + - const: google,ponyta + - const: mediatek,mt8186 - description: Google Rusty (Lenovo 100e Chromebook Gen 4) items: - const: google,steelix-sku196609 diff --git a/Documentation/devicetree/bindings/arm/psci.yaml b/Documentation/devicetree/bindings/arm/psci.yaml index cbb012e217ab8..7360a2849b5bd 100644 --- a/Documentation/devicetree/bindings/arm/psci.yaml +++ b/Documentation/devicetree/bindings/arm/psci.yaml @@ -191,27 +191,27 @@ examples: #size-cells = <0>; #address-cells = <1>; - CPU0: cpu@0 { + cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; enable-method = "psci"; - power-domains = <&CPU_PD0>; + power-domains = <&cpu_pd0>; power-domain-names = "psci"; }; - CPU1: cpu@1 { + cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x100>; enable-method = "psci"; - power-domains = <&CPU_PD1>; + power-domains = <&cpu_pd1>; power-domain-names = "psci"; }; idle-states { - CPU_PWRDN: cpu-power-down { + cpu_pwrdn: cpu-power-down { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x0000001>; entry-latency-us = <10>; @@ -222,7 +222,7 @@ examples: domain-idle-states { - CLUSTER_RET: cluster-retention { + cluster_ret: cluster-retention { compatible = "domain-idle-state"; arm,psci-suspend-param = <0x1000011>; entry-latency-us = <500>; @@ -230,7 +230,7 @@ examples: min-residency-us = <2000>; }; - CLUSTER_PWRDN: cluster-power-down { + cluster_pwrdn: cluster-power-down { compatible = "domain-idle-state"; arm,psci-suspend-param = <0x1000031>; entry-latency-us = <2000>; @@ -244,21 +244,21 @@ examples: compatible = "arm,psci-1.0"; method = "smc"; - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells = <0>; - domain-idle-states = <&CPU_PWRDN>; - power-domains = <&CLUSTER_PD>; + domain-idle-states = <&cpu_pwrdn>; + power-domains = <&cluster_pd>; }; - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells = <0>; - domain-idle-states = <&CPU_PWRDN>; - power-domains = <&CLUSTER_PD>; + domain-idle-states = <&cpu_pwrdn>; + power-domains = <&cluster_pd>; }; - CLUSTER_PD: power-domain-cluster { + cluster_pd: power-domain-cluster { #power-domain-cells = <0>; - domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; + domain-idle-states = <&cluster_ret>, <&cluster_pwrdn>; }; }; ... diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 618a87693ac1d..56f78f0f3803f 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -90,6 +90,7 @@ description: | sm6350 sm6375 sm7125 + sm7150 sm7225 sm7325 sm8150 @@ -1020,6 +1021,7 @@ properties: - items: - enum: - sony,pdx201 + - xiaomi,ginkgo - xiaomi,laurel-sprout - const: qcom,sm6125 @@ -1039,6 +1041,11 @@ properties: - xiaomi,joyeuse - const: qcom,sm7125 + - items: + - enum: + - google,sunfish + - const: qcom,sm7150 + - items: - enum: - fairphone,fp4 @@ -1123,14 +1130,18 @@ properties: - items: - enum: - - lenovo,thinkpad-t14s + - lenovo,thinkpad-t14s-lcd + - lenovo,thinkpad-t14s-oled + - const: lenovo,thinkpad-t14s - const: qcom,x1e78100 - const: qcom,x1e80100 - items: - enum: - asus,vivobook-s15 + - asus,zenbook-a14-ux3407ra - dell,xps13-9345 + - hp,elitebook-ultra-g1q - hp,omnibook-x14 - lenovo,yoga-slim7x - microsoft,romulus13 @@ -1141,6 +1152,7 @@ properties: - items: - enum: + - asus,zenbook-a14-ux3407qa - qcom,x1p42100-crd - const: qcom,x1p42100 diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 650fb833d96ef..5772d905f390e 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -946,6 +946,11 @@ properties: - const: radxa,rock-5b - const: rockchip,rk3588 + - description: Radxa ROCK 5B+ + items: + - const: radxa,rock-5b-plus + - const: rockchip,rk3588 + - description: Radxa ROCK 5C items: - const: radxa,rock-5c @@ -1047,6 +1052,11 @@ properties: - const: rockchip,rk3399-evb - const: rockchip,rk3399 + - description: Rockchip RK3399 Industry Evaluation board + items: + - const: rockchip,rk3399-evb-ind + - const: rockchip,rk3399 + - description: Rockchip RK3399 Sapphire standalone items: - const: rockchip,rk3399-sapphire @@ -1057,6 +1067,11 @@ properties: - const: rockchip,rk3399-sapphire-excavator - const: rockchip,rk3399 + - description: Rockchip RK3562 Evaluation board 2 + items: + - const: rockchip,rk3562-evb2-v10 + - const: rockchip,rk3562 + - description: Rockchip RK3566 BOX Evaluation Demo board items: - const: rockchip,rk3566-box-demo @@ -1074,7 +1089,9 @@ properties: - description: Rockchip RK3588 Evaluation board items: - - const: rockchip,rk3588-evb1-v10 + - enum: + - rockchip,rk3588-evb1-v10 + - rockchip,rk3588-evb2-v10 - const: rockchip,rk3588 - description: Rockchip RK3588S Evaluation board @@ -1109,6 +1126,24 @@ properties: - rockchip,rv1126 - rockchip,rv1109 + - description: Theobroma Systems PX30-Cobra + items: + - enum: + - tsd,px30-cobra-ltk050h3146w + - tsd,px30-cobra-ltk050h3146w-a2 + - tsd,px30-cobra-ltk050h3148w + - tsd,px30-cobra-ltk500hd1829 + - const: tsd,px30-cobra + - const: rockchip,px30 + + - description: Theobroma Systems PX30-PP1516 + items: + - enum: + - tsd,px30-pp1516-ltk050h3146w-a2 + - tsd,px30-pp1516-ltk050h3148w + - const: tsd,px30-pp1516 + - const: rockchip,px30 + - description: Theobroma Systems PX30-uQ7 with Haikou baseboard items: - const: tsd,px30-ringneck-haikou diff --git a/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml b/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml index 52016a141227b..46c1af851be74 100644 --- a/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml @@ -25,6 +25,7 @@ select: - rockchip,rk3288-pmu - rockchip,rk3368-pmu - rockchip,rk3399-pmu + - rockchip,rk3562-pmu - rockchip,rk3568-pmu - rockchip,rk3576-pmu - rockchip,rk3588-pmu @@ -43,6 +44,7 @@ properties: - rockchip,rk3288-pmu - rockchip,rk3368-pmu - rockchip,rk3399-pmu + - rockchip,rk3562-pmu - rockchip,rk3568-pmu - rockchip,rk3576-pmu - rockchip,rk3588-pmu diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index fab29f95d8e62..b3be184c7e563 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -212,6 +212,14 @@ properties: - samsung,exynos7-espresso # Samsung Exynos7 Espresso - const: samsung,exynos7 + - description: Exynos7870 based boards + items: + - enum: + - samsung,a2corelte # Samsung Galaxy A2 Core + - samsung,j6lte # Samsung Galaxy J6 + - samsung,on7xelte # Samsung Galaxy J7 Prime + - const: samsung,exynos7870 + - description: Exynos7885 based boards items: - enum: diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 5fee2f38ff25d..408532504a24d 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -42,6 +42,10 @@ properties: - st,stm32h743i-disco - st,stm32h743i-eval - const: st,stm32h743 + - items: + - enum: + - st,stm32h747i-disco + - const: st,stm32h747 - items: - enum: - st,stm32h750i-art-pi @@ -184,6 +188,11 @@ properties: - const: phytec,phycore-stm32mp157c-som - const: st,stm32mp157 + - description: Ultratronik STM32MP1 SBC based Boards + items: + - const: ultratronik,stm32mp157c-ultra-fly-sbc + - const: st,stm32mp157 + - description: ST STM32MP257 based Boards items: - enum: diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index f536cdd2c1a65..7807ea6132589 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -492,6 +492,11 @@ properties: - const: lamobo,lamobo-r1 - const: allwinner,sun7i-a20 + - description: Liontron H-A133L + items: + - const: liontron,h-a133l + - const: allwinner,sun50i-a100 + - description: HAOYU Electronics Marsboard A10 items: - const: haoyu,a10-marsboard @@ -845,6 +850,11 @@ properties: - const: allwinner,r7-tv-dongle - const: allwinner,sun5i-a10s + - description: Radxa Cubie A5E + items: + - const: radxa,cubie-a5e + - const: allwinner,sun55i-a527 + - description: Remix Mini PC items: - const: jide,remix-mini-pc @@ -966,6 +976,11 @@ properties: - const: hechuang,x96-mate - const: allwinner,sun50i-h616 + - description: X96Q Pro+ + items: + - const: amediatech,x96q-pro-plus + - const: allwinner,sun55i-h728 + - description: Xunlong OrangePi items: - const: xunlong,orangepi @@ -1081,4 +1096,14 @@ properties: - const: xunlong,orangepi-zero3 - const: allwinner,sun50i-h618 + - description: YuzukiHD Avaota A1 + items: + - const: yuzukihd,avaota-a1 + - const: allwinner,sun55i-t527 + + - description: YuzukiHD Chameleon + items: + - const: yuzukihd,chameleon + - const: allwinner,sun50i-h618 + additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index 65e0ff1fdf1ec..9cae3268a8274 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -52,17 +52,14 @@ properties: - nvidia,cardhu-a04 - const: nvidia,cardhu - const: nvidia,tegra30 - - items: - - const: asus,tf201 - - const: nvidia,tegra30 - - items: - - const: asus,tf300t - - const: nvidia,tegra30 - - items: - - const: asus,tf300tg - - const: nvidia,tegra30 - - items: - - const: asus,tf700t + - description: ASUS Transformers Device family + items: + - enum: + - asus,tf201 + - asus,tf300t + - asus,tf300tg + - asus,tf300tl + - asus,tf700t - const: nvidia,tegra30 - description: LG Optimus 4X P880 items: diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index 18f155cd06c84..bf6003d8fb764 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -46,6 +46,7 @@ properties: - description: K3 AM625 SoC items: - enum: + - beagle,am62-pocketbeagle2 - beagle,am625-beagleplay - ti,am625-sk - ti,am62-lp-sk @@ -75,6 +76,30 @@ properties: - const: toradex,verdin-am62 # Verdin AM62 Module - const: ti,am625 + - description: K3 AM62P5 SoC Toradex Verdin Modules and Carrier Boards + items: + - enum: + - toradex,verdin-am62p-nonwifi-dahlia # Verdin AM62P Module on Dahlia + - toradex,verdin-am62p-nonwifi-dev # Verdin AM62P Module on Verdin Development Board + - toradex,verdin-am62p-nonwifi-ivy # Verdin AM62P Module on Ivy + - toradex,verdin-am62p-nonwifi-mallow # Verdin AM62P Module on Mallow + - toradex,verdin-am62p-nonwifi-yavia # Verdin AM62P Module on Yavia + - const: toradex,verdin-am62p-nonwifi # Verdin AM62P Module without Wi-Fi / BT + - const: toradex,verdin-am62p # Verdin AM62P Module + - const: ti,am62p5 + + - description: K3 AM62P5 SoC Toradex Verdin Modules and Carrier Boards with Wi-Fi / BT + items: + - enum: + - toradex,verdin-am62p-wifi-dahlia # Verdin AM62P Wi-Fi / BT Module on Dahlia + - toradex,verdin-am62p-wifi-dev # Verdin AM62P Wi-Fi / BT M. on Verdin Development B. + - toradex,verdin-am62p-wifi-ivy # Verdin AM62P Wi-Fi / BT Module on Ivy + - toradex,verdin-am62p-wifi-mallow # Verdin AM62P Wi-Fi / BT Module on Mallow + - toradex,verdin-am62p-wifi-yavia # Verdin AM62P Wi-Fi / BT Module on Yavia + - const: toradex,verdin-am62p-wifi # Verdin AM62P Wi-Fi / BT Module + - const: toradex,verdin-am62p # Verdin AM62P Module + - const: ti,am62p5 + - description: K3 AM642 SoC items: - enum: @@ -139,6 +164,13 @@ properties: - ti,j721s2-evm - const: ti,j721s2 + - description: K3 J721s2 SoC Phytec SoM based boards + items: + - enum: + - phytec,am68-phyboard-izar + - const: phytec,am68-phycore-som + - const: ti,j721s2 + - description: K3 J722S SoC and Boards items: - enum: diff --git a/Documentation/devicetree/bindings/arm/vt8500.yaml b/Documentation/devicetree/bindings/arm/vt8500.yaml index 5d5ad5a60451f..fa47b8989bbfb 100644 --- a/Documentation/devicetree/bindings/arm/vt8500.yaml +++ b/Documentation/devicetree/bindings/arm/vt8500.yaml @@ -7,14 +7,13 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: VIA/Wondermedia VT8500 Platforms maintainers: - - Tony Prisk -description: test + - Alexey Charkov properties: $nodename: const: '/' compatible: - items: + oneOf: - enum: - via,vt8500 - wm,wm8505 @@ -22,4 +21,9 @@ properties: - wm,wm8750 - wm,wm8850 + - description: VIA APC Rock and Paper boards + items: + - const: via,apc-rock + - const: wm,wm8950 + additionalProperties: true diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml b/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml index 26362c9006e27..81a65e9f93f1f 100644 --- a/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml +++ b/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml @@ -21,6 +21,7 @@ properties: - const: nvidia,tegra210-aconnect - items: - enum: + - nvidia,tegra264-aconnect - nvidia,tegra234-aconnect - nvidia,tegra186-aconnect - nvidia,tegra194-aconnect diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml index d2cbe49f4e15f..4de5bb2e5f246 100644 --- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml @@ -28,6 +28,9 @@ select: properties: compatible: items: + - enum: + - andestech,qilai-ax45mp-cache + - renesas,r9a07g043f-ax45mp-cache - const: andestech,ax45mp-cache - const: cache @@ -65,12 +68,27 @@ required: - cache-size - cache-unified +allOf: + - if: + properties: + compatible: + contains: + const: andestech,qilai-ax45mp-cache + + then: + properties: + cache-sets: + const: 2048 + cache-size: + const: 2097152 + examples: - | #include cache-controller@13400000 { - compatible = "andestech,ax45mp-cache", "cache"; + compatible = "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cache", + "cache"; reg = <0x13400000 0x100000>; interrupts = <508 IRQ_TYPE_LEVEL_HIGH>; cache-line-size = <64>; diff --git a/Documentation/devicetree/bindings/cache/marvell,feroceon-cache.txt b/Documentation/devicetree/bindings/cache/marvell,feroceon-cache.txt deleted file mode 100644 index 0d244b999d103..0000000000000 --- a/Documentation/devicetree/bindings/cache/marvell,feroceon-cache.txt +++ /dev/null @@ -1,16 +0,0 @@ -* Marvell Feroceon Cache - -Required properties: -- compatible : Should be either "marvell,feroceon-cache" or - "marvell,kirkwood-cache". - -Optional properties: -- reg : Address of the L2 cache control register. Mandatory for - "marvell,kirkwood-cache", not used by "marvell,feroceon-cache" - - -Example: - l2: l2-cache@20128 { - compatible = "marvell,kirkwood-cache"; - reg = <0x20128 0x4>; - }; diff --git a/Documentation/devicetree/bindings/cache/marvell,kirkwood-cache.yaml b/Documentation/devicetree/bindings/cache/marvell,kirkwood-cache.yaml new file mode 100644 index 0000000000000..2bfa3c29f6a68 --- /dev/null +++ b/Documentation/devicetree/bindings/cache/marvell,kirkwood-cache.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/marvell,kirkwood-cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Feroceon/Kirkwood Cache + +maintainers: + - Andrew Lunn + - Gregory Clement + +properties: + compatible: + enum: + - marvell,feroceon-cache + - marvell,kirkwood-cache + + reg: + maxItems: 1 + +allOf: + - if: + properties: + compatible: + contains: + const: marvell,kirkwood-cache + then: + required: + - reg + else: + properties: + reg: false + +required: + - compatible + +additionalProperties: false + +examples: + - | + l2-cache@20128 { + compatible = "marvell,kirkwood-cache"; + reg = <0x20128 0x4>; + }; diff --git a/Documentation/devicetree/bindings/cache/marvell,tauros2-cache.txt b/Documentation/devicetree/bindings/cache/marvell,tauros2-cache.txt deleted file mode 100644 index 31af1cbb60bde..0000000000000 --- a/Documentation/devicetree/bindings/cache/marvell,tauros2-cache.txt +++ /dev/null @@ -1,17 +0,0 @@ -* Marvell Tauros2 Cache - -Required properties: -- compatible : Should be "marvell,tauros2-cache". -- marvell,tauros2-cache-features : Specify the features supported for the - tauros2 cache. - The features including - CACHE_TAUROS2_PREFETCH_ON (1 << 0) - CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1) - The definition can be found at - arch/arm/include/asm/hardware/cache-tauros2.h - -Example: - L2: l2-cache { - compatible = "marvell,tauros2-cache"; - marvell,tauros2-cache-features = <0x3>; - }; diff --git a/Documentation/devicetree/bindings/cache/marvell,tauros2-cache.yaml b/Documentation/devicetree/bindings/cache/marvell,tauros2-cache.yaml new file mode 100644 index 0000000000000..9f7f0d0316319 --- /dev/null +++ b/Documentation/devicetree/bindings/cache/marvell,tauros2-cache.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/marvell,tauros2-cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Tauros2 Cache + +maintainers: + - Andrew Lunn + - Gregory Clement + +properties: + compatible: + const: marvell,tauros2-cache + + marvell,tauros2-cache-features: + description: > + Specify the features supported for the tauros2 cache. The features include: + + - CACHE_TAUROS2_PREFETCH_ON (1 << 0) + - CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1) + + The definition can be found at arch/arm/include/asm/hardware/cache-tauros2.h + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 0x3 + +required: + - compatible + - marvell,tauros2-cache-features + +additionalProperties: false + +examples: + - | + l2-cache { + compatible = "marvell,tauros2-cache"; + marvell,tauros2-cache-features = <0x3>; + }; diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml index e5effbb4a606b..37e3ebd554874 100644 --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml @@ -40,6 +40,7 @@ properties: - qcom,sm8450-llcc - qcom,sm8550-llcc - qcom,sm8650-llcc + - qcom,sm8750-llcc - qcom,x1e80100-llcc reg: @@ -274,6 +275,7 @@ allOf: - qcom,sm8450-llcc - qcom,sm8550-llcc - qcom,sm8650-llcc + - qcom,sm8750-llcc then: properties: reg: diff --git a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml index 7e8cebe215846..579bacb66f348 100644 --- a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml +++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml @@ -39,6 +39,7 @@ properties: - const: cache - items: - enum: + - eswin,eic7700-l3-cache - starfive,jh7100-ccache - starfive,jh7110-ccache - const: sifive,ccache0 @@ -55,10 +56,10 @@ properties: enum: [2, 3] cache-sets: - enum: [1024, 2048] + enum: [1024, 2048, 4096] cache-size: - const: 2097152 + enum: [2097152, 4194304] cache-unified: true @@ -89,6 +90,7 @@ allOf: compatible: contains: enum: + - eswin,eic7700-l3-cache - sifive,fu740-c000-ccache - starfive,jh7100-ccache - starfive,jh7110-ccache @@ -108,6 +110,22 @@ allOf: Must contain entries for DirError, DataError and DataFail signals. maxItems: 3 + - if: + properties: + compatible: + contains: + const: eswin,eic7700-l3-cache + + then: + properties: + cache-size: + const: 4194304 + + else: + properties: + cache-size: + const: 2097152 + - if: properties: compatible: @@ -122,11 +140,31 @@ allOf: cache-sets: const: 2048 - else: + - if: + properties: + compatible: + contains: + enum: + - microchip,mpfs-ccache + - sifive,fu540-c000-ccache + + then: properties: cache-sets: const: 1024 + - if: + properties: + compatible: + contains: + enum: + - eswin,eic7700-l3-cache + + then: + properties: + cache-sets: + const: 4096 + - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml index 70369bd633e40..7fcd55d468d49 100644 --- a/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml +++ b/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml @@ -25,6 +25,7 @@ properties: - const: allwinner,sun50i-a64-de2-clk - const: allwinner,sun50i-h5-de2-clk - const: allwinner,sun50i-h6-de3-clk + - const: allwinner,sun50i-h616-de33-clk - items: - const: allwinner,sun8i-r40-de2-clk - const: allwinner,sun8i-h3-de2-clk diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt deleted file mode 100644 index f72e80e0dade8..0000000000000 --- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt +++ /dev/null @@ -1,30 +0,0 @@ -Device Tree Clock bindings for Altera's SoCFPGA platform - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be one of the following: - "altr,socfpga-pll-clock" - for a PLL clock - "altr,socfpga-perip-clock" - The peripheral clock divided from the - PLL clock. - "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and - can get gated. - -- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock. -- clocks : shall be the input parent clock phandle for the clock. This is - either an oscillator or a pll output. -- #clock-cells : from common clock binding, shall be set to 0. - -Optional properties: -- fixed-divider : If clocks have a fixed divider value, use this property. -- clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register - and the bit index. -- div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains - the divider register, bit shift, and width. -- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls - the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second - value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct - hold/delay times that is needed for the SD/MMC CIU clock. The values of both - can be 0-315 degrees, in 45 degree increments. diff --git a/Documentation/devicetree/bindings/clock/brcm,bcm2835-aux-clock.txt b/Documentation/devicetree/bindings/clock/brcm,bcm2835-aux-clock.txt deleted file mode 100644 index 4acfc8f641b63..0000000000000 --- a/Documentation/devicetree/bindings/clock/brcm,bcm2835-aux-clock.txt +++ /dev/null @@ -1,31 +0,0 @@ -Broadcom BCM2835 auxiliary peripheral support - -This binding uses the common clock binding: - Documentation/devicetree/bindings/clock/clock-bindings.txt - -The auxiliary peripherals (UART, SPI1, and SPI2) have a small register -area controlling clock gating to the peripherals, and providing an IRQ -status register. - -Required properties: -- compatible: Should be "brcm,bcm2835-aux" -- #clock-cells: Should be <1>. The permitted clock-specifier values can be - found in include/dt-bindings/clock/bcm2835-aux.h -- reg: Specifies base physical address and size of the registers -- clocks: The parent clock phandle - -Example: - - clocks: cprman@7e101000 { - compatible = "brcm,bcm2835-cprman"; - #clock-cells = <1>; - reg = <0x7e101000 0x2000>; - clocks = <&clk_osc>; - }; - - aux: aux@7e215004 { - compatible = "brcm,bcm2835-aux"; - #clock-cells = <1>; - reg = <0x7e215000 0x8>; - clocks = <&clocks BCM2835_CLOCK_VPU>; - }; diff --git a/Documentation/devicetree/bindings/clock/brcm,bcm2835-aux-clock.yaml b/Documentation/devicetree/bindings/clock/brcm,bcm2835-aux-clock.yaml new file mode 100644 index 0000000000000..0f4050ffa41cc --- /dev/null +++ b/Documentation/devicetree/bindings/clock/brcm,bcm2835-aux-clock.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/brcm,bcm2835-aux-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM2835 auxiliary peripheral clock + +maintainers: + - Stefan Wahren + - Raspberry Pi Kernel Maintenance + +description: + The auxiliary peripherals (UART, SPI1, and SPI2) have a small register + area controlling clock gating to the peripherals, and providing an IRQ + status register. + +properties: + compatible: + const: brcm,bcm2835-aux + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - "#clock-cells" + - clocks + +additionalProperties: false + +examples: + - | + #include + clock@7e215000 { + compatible = "brcm,bcm2835-aux"; + reg = <0x7e215000 0x8>; + #clock-cells = <1>; + clocks = <&clocks BCM2835_CLOCK_VPU>; + }; diff --git a/Documentation/devicetree/bindings/clock/fsl,vf610-ccm.yaml b/Documentation/devicetree/bindings/clock/fsl,vf610-ccm.yaml new file mode 100644 index 0000000000000..29ae5be51acf8 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fsl,vf610-ccm.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fsl,vf610-ccm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Clock for Freescale Vybrid VF610 SOC + +description: + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h + for the full list of VF610 clock IDs + +maintainers: + - Frank Li + +properties: + compatible: + const: fsl,vf610-ccm + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clocks: + items: + - description: external crystal oscillator 32KHz, recommended + - description: external crystal oscillator 24MHz, recommended + - description: audio + - description: enet + minItems: 2 + + clock-names: + items: + - const: sxosc + - const: fxosc + - const: enet_ext + - const: audio_ext + minItems: 2 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + clock-controller@4006b000 { + compatible = "fsl,vf610-ccm"; + reg = <0x4006b000 0x1000>; + #clock-cells = <1>; + clocks = <&sxosc>, <&fxosc>; + clock-names = "sxosc", "fxosc"; + }; + diff --git a/Documentation/devicetree/bindings/clock/maxim,max77686.txt b/Documentation/devicetree/bindings/clock/maxim,max77686.txt deleted file mode 100644 index c10849efb4440..0000000000000 --- a/Documentation/devicetree/bindings/clock/maxim,max77686.txt +++ /dev/null @@ -1,114 +0,0 @@ -Binding for Maxim MAX77686/MAX77802/MAX77620 32k clock generator block - -This is a part of device tree bindings of MAX77686/MAX77802/MAX77620 -multi-function device. More information can be found in MFD DT binding -doc as follows: - bindings/mfd/max77686.txt for MAX77686 and - bindings/mfd/max77802.txt for MAX77802 and - bindings/mfd/max77620.txt for MAX77620. - -The MAX77686 contains three 32.768khz clock outputs that can be controlled -(gated/ungated) over I2C. Clocks are defined as preprocessor macros in -dt-bindings/clock/maxim,max77686.h. - - -The MAX77802 contains two 32.768khz clock outputs that can be controlled -(gated/ungated) over I2C. Clocks are defined as preprocessor macros in -dt-bindings/clock/maxim,max77802.h. - -The MAX77686 contains one 32.768khz clock outputs that can be controlled -(gated/ungated) over I2C. Clocks are defined as preprocessor macros in -dt-bindings/clock/maxim,max77620.h. - -Following properties should be presend in main device node of the MFD chip. - -Required properties: - -- #clock-cells: from common clock binding; shall be set to 1. - -Optional properties: -- clock-output-names: From common clock binding. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. Following indices are allowed: - - 0: 32khz_ap clock (max77686, max77802), 32khz_out0 (max77620) - - 1: 32khz_cp clock (max77686, max77802), - - 2: 32khz_pmic clock (max77686). - -Clocks are defined as preprocessor macros in above dt-binding header for -respective chips. - -Example: - -1. With MAX77686: - -#include -/* ... */ - - Node of the MFD chip - max77686: max77686@9 { - compatible = "maxim,max77686"; - interrupt-parent = <&wakeup_eint>; - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - reg = <0x09>; - #clock-cells = <1>; - - /* ... */ - }; - - Clock consumer node - - foo@0 { - compatible = "bar,foo"; - /* ... */ - clock-names = "my-clock"; - clocks = <&max77686 MAX77686_CLK_PMIC>; - }; - -2. With MAX77802: - -#include -/* ... */ - - Node of the MFD chip - max77802: max77802@9 { - compatible = "maxim,max77802"; - interrupt-parent = <&wakeup_eint>; - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - reg = <0x09>; - #clock-cells = <1>; - - /* ... */ - }; - - Clock consumer node - - foo@0 { - compatible = "bar,foo"; - /* ... */ - clock-names = "my-clock"; - clocks = <&max77802 MAX77802_CLK_32K_AP>; - }; - - -3. With MAX77620: - -#include -/* ... */ - - Node of the MFD chip - max77620: max77620@3c { - compatible = "maxim,max77620"; - reg = <0x3c>; - #clock-cells = <1>; - /* ... */ - }; - - Clock consumer node - - foo@0 { - compatible = "bar,foo"; - /* ... */ - clock-names = "my-clock"; - clocks = <&max77620 MAX77620_CLK_32K_OUT0>; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml index 340c7e5cf9802..5f7738d6835c4 100644 --- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml @@ -14,6 +14,7 @@ description: | domains on Qualcomm SoCs. See also:: + include/dt-bindings/clock/qcom,sm6350-videocc.h include/dt-bindings/clock/qcom,videocc-sc7180.h include/dt-bindings/clock/qcom,videocc-sc7280.h include/dt-bindings/clock/qcom,videocc-sdm845.h @@ -26,6 +27,7 @@ properties: - qcom,sc7180-videocc - qcom,sc7280-videocc - qcom,sdm845-videocc + - qcom,sm6350-videocc - qcom,sm8150-videocc - qcom,sm8250-videocc @@ -87,6 +89,24 @@ allOf: - const: bi_tcxo - const: bi_tcxo_ao + - if: + properties: + compatible: + enum: + - qcom,sm6350-videocc + then: + properties: + clocks: + items: + - description: Video AHB clock from GCC + - description: Board XO source + - description: Sleep Clock source + clock-names: + items: + - const: iface + - const: bi_tcxo + - const: sleep_clk + - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml index c3fe76abd549d..f261445bf341c 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml @@ -4,13 +4,13 @@ $id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG) +title: Renesas RZ/{G3E,V2H(P),V2N} Clock Pulse Generator (CPG) maintainers: - Lad Prabhakar description: - On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles + On Renesas RZ/{G3E,V2H(P),V2N} SoCs, the CPG (Clock Pulse Generator) handles generation and control of clock signals for the IP modules, generation and control of resets, and control over booting, low power consumption and power supply domains. @@ -19,6 +19,7 @@ properties: compatible: enum: - renesas,r9a09g047-cpg # RZ/G3E + - renesas,r9a09g056-cpg # RZ/V2N - renesas,r9a09g057-cpg # RZ/V2H reg: diff --git a/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml index 3330b27274747..6961a68098f43 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml @@ -8,6 +8,7 @@ title: Samsung ExynosAuto v920 SoC clock controller maintainers: - Sunyeal Hong + - Shin Son - Chanwoo Choi - Krzysztof Kozlowski - Sylwester Nawrocki @@ -32,6 +33,9 @@ properties: compatible: enum: - samsung,exynosautov920-cmu-top + - samsung,exynosautov920-cmu-cpucl0 + - samsung,exynosautov920-cmu-cpucl1 + - samsung,exynosautov920-cmu-cpucl2 - samsung,exynosautov920-cmu-peric0 - samsung,exynosautov920-cmu-peric1 - samsung,exynosautov920-cmu-misc @@ -69,6 +73,71 @@ allOf: items: - const: oscclk + - if: + properties: + compatible: + contains: + enum: + - samsung,exynosautov920-cmu-cpucl0 + + then: + properties: + clocks: + items: + - description: External reference clock (38.4 MHz) + - description: CMU_CPUCL0 SWITCH clock (from CMU_TOP) + - description: CMU_CPUCL0 CLUSTER clock (from CMU_TOP) + - description: CMU_CPUCL0 DBG clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: switch + - const: cluster + - const: dbg + + - if: + properties: + compatible: + contains: + enum: + - samsung,exynosautov920-cmu-cpucl1 + + then: + properties: + clocks: + items: + - description: External reference clock (38.4 MHz) + - description: CMU_CPUCL1 SWITCH clock (from CMU_TOP) + - description: CMU_CPUCL1 CLUSTER clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: switch + - const: cluster + + - if: + properties: + compatible: + contains: + enum: + - samsung,exynosautov920-cmu-cpucl2 + + then: + properties: + clocks: + items: + - description: External reference clock (38.4 MHz) + - description: CMU_CPUCL2 SWITCH clock (from CMU_TOP) + - description: CMU_CPUCL2 CLUSTER clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: switch + - const: cluster + - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/clock/sophgo,cv1800-clk.yaml b/Documentation/devicetree/bindings/clock/sophgo,cv1800-clk.yaml index 59ef41adb539b..379ce3e9e391c 100644 --- a/Documentation/devicetree/bindings/clock/sophgo,cv1800-clk.yaml +++ b/Documentation/devicetree/bindings/clock/sophgo,cv1800-clk.yaml @@ -11,10 +11,18 @@ maintainers: properties: compatible: - enum: - - sophgo,cv1800-clk - - sophgo,cv1810-clk - - sophgo,sg2000-clk + oneOf: + - enum: + - sophgo,cv1800b-clk + - sophgo,cv1812h-clk + - sophgo,sg2000-clk + - items: + - const: sophgo,sg2002-clk + - const: sophgo,sg2000-clk + - const: sophgo,cv1800-clk + deprecated: true + - const: sophgo,cv1810-clk + deprecated: true reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/clock/sophgo,sg2044-clk.yaml b/Documentation/devicetree/bindings/clock/sophgo,sg2044-clk.yaml new file mode 100644 index 0000000000000..272e58bdb62c4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sophgo,sg2044-clk.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sophgo,sg2044-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2044 Clock Controller + +maintainers: + - Inochi Amaoto + +description: | + The Sophgo SG2044 clock controller requires an external oscillator + as input clock. + + All available clocks are defined as preprocessor macros in + include/dt-bindings/clock/sophgo,sg2044-clk.h + +properties: + compatible: + const: sophgo,sg2044-clk + + reg: + maxItems: 1 + + clocks: + items: + - description: fpll0 + - description: fpll1 + - description: fpll2 + - description: dpll0 + - description: dpll1 + - description: dpll2 + - description: dpll3 + - description: dpll4 + - description: dpll5 + - description: dpll6 + - description: dpll7 + - description: mpll0 + - description: mpll1 + - description: mpll2 + - description: mpll3 + - description: mpll4 + - description: mpll5 + + clock-names: + items: + - const: fpll0 + - const: fpll1 + - const: fpll2 + - const: dpll0 + - const: dpll1 + - const: dpll2 + - const: dpll3 + - const: dpll4 + - const: dpll5 + - const: dpll6 + - const: dpll7 + - const: mpll0 + - const: mpll1 + - const: mpll2 + - const: mpll3 + - const: mpll4 + - const: mpll5 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@50002000 { + compatible = "sophgo,sg2044-clk"; + reg = <0x50002000 0x1000>; + #clock-cells = <1>; + clocks = <&syscon CLK_FPLL0>, <&syscon CLK_FPLL1>, + <&syscon CLK_FPLL2>, <&syscon CLK_DPLL0>, + <&syscon CLK_DPLL1>, <&syscon CLK_DPLL2>, + <&syscon CLK_DPLL3>, <&syscon CLK_DPLL4>, + <&syscon CLK_DPLL5>, <&syscon CLK_DPLL6>, + <&syscon CLK_DPLL7>, <&syscon CLK_MPLL0>, + <&syscon CLK_MPLL1>, <&syscon CLK_MPLL2>, + <&syscon CLK_MPLL3>, <&syscon CLK_MPLL4>, + <&syscon CLK_MPLL5>; + clock-names = "fpll0", "fpll1", "fpll2", "dpll0", + "dpll1", "dpll2", "dpll3", "dpll4", + "dpll5", "dpll6", "dpll7", "mpll0", + "mpll1", "mpll2", "mpll3", "mpll4", + "mpll5"; + }; diff --git a/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml b/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml new file mode 100644 index 0000000000000..06bafd68c00a0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/spacemit,k1-pll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K1 PLL + +maintainers: + - Haylen Chu + +properties: + compatible: + const: spacemit,k1-pll + + reg: + maxItems: 1 + + clocks: + description: External 24MHz oscillator + + spacemit,mpmu: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the "Main PMU (MPMU)" syscon. It is used to check PLL + lock status. + + "#clock-cells": + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - spacemit,mpmu + - "#clock-cells" + +additionalProperties: false + +examples: + - | + clock-controller@d4090000 { + compatible = "spacemit,k1-pll"; + reg = <0xd4090000 0x1000>; + clocks = <&vctcxo_24m>; + spacemit,mpmu = <&sysctl_mpmu>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/st,stm32h7-rcc.txt b/Documentation/devicetree/bindings/clock/st,stm32h7-rcc.txt deleted file mode 100644 index cac24ee10b72e..0000000000000 --- a/Documentation/devicetree/bindings/clock/st,stm32h7-rcc.txt +++ /dev/null @@ -1,71 +0,0 @@ -STMicroelectronics STM32H7 Reset and Clock Controller -===================================================== - -The RCC IP is both a reset and a clock controller. - -Please refer to clock-bindings.txt for common clock controller binding usage. -Please also refer to reset.txt for common reset controller binding usage. - -Required properties: -- compatible: Should be: - "st,stm32h743-rcc" - -- reg: should be register base and length as documented in the - datasheet - -- #reset-cells: 1, see below - -- #clock-cells : from common clock binding; shall be set to 1 - -- clocks: External oscillator clock phandle - - high speed external clock signal (HSE) - - low speed external clock signal (LSE) - - external I2S clock (I2S_CKIN) - -Optional properties: -- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain - write protection (RTC clock). - -Example: - - rcc: reset-clock-controller@58024400 { - compatible = "st,stm32h743-rcc", "st,stm32-rcc"; - reg = <0x58024400 0x400>; - #reset-cells = <1>; - #clock-cells = <1>; - clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s_ckin>; - - st,syscfg = <&pwrcfg>; -}; - -The peripheral clock consumer should specify the desired clock by -having the clock ID in its "clocks" phandle cell. - -Example: - - timer5: timer@40000c00 { - compatible = "st,stm32-timer"; - reg = <0x40000c00 0x400>; - interrupts = <50>; - clocks = <&rcc TIM5_CK>; - }; - -Specifying softreset control of devices -======================================= - -Device nodes should specify the reset channel required in their "resets" -property, containing a phandle to the reset device node and an index specifying -which channel to use. -The index is the bit number within the RCC registers bank, starting from RCC -base address. -It is calculated as: index = register_offset / 4 * 32 + bit_offset. -Where bit_offset is the bit offset within the register. - -For example, for CRC reset: - crc = AHB4RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x88 / 4 * 32 + 19 = 1107 - -Example: - - timer2 { - resets = <&rcc STM32H7_APB1L_RESET(TIM2)>; - }; diff --git a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml index 0129bd0ba4b3f..9d058c00ab3d5 100644 --- a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml +++ b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml @@ -8,7 +8,8 @@ title: T-HEAD TH1520 AP sub-system clock controller description: | The T-HEAD TH1520 AP sub-system clock controller configures the - CPU, DPU, GMAC and TEE PLLs. + CPU, DPU, GMAC and TEE PLLs. Additionally the VO subsystem configures + the clock gates for the HDMI, MIPI and the GPU. SoC reference manual https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf @@ -20,14 +21,24 @@ maintainers: properties: compatible: - const: thead,th1520-clk-ap + enum: + - thead,th1520-clk-ap + - thead,th1520-clk-vo reg: maxItems: 1 clocks: items: - - description: main oscillator (24MHz) + - description: | + One input clock: + - For "thead,th1520-clk-ap": the clock input must be the 24 MHz + main oscillator. + - For "thead,th1520-clk-vo": the clock input must be the VIDEO_PLL, + which is configured by the AP clock controller. According to the + TH1520 manual, VIDEO_PLL is a Silicon Creations Sigma-Delta PLL + (integer PLL) typically running at 792 MHz (FOUTPOSTDIV), with + a maximum FOUTVCO of 2376 MHz. "#clock-cells": const: 1 diff --git a/Documentation/devicetree/bindings/clock/vf610-clock.txt b/Documentation/devicetree/bindings/clock/vf610-clock.txt deleted file mode 100644 index 109ffa3a5b661..0000000000000 --- a/Documentation/devicetree/bindings/clock/vf610-clock.txt +++ /dev/null @@ -1,41 +0,0 @@ -* Clock bindings for Freescale Vybrid VF610 SOC - -Required properties: -- compatible: Should be "fsl,vf610-ccm" -- reg: Address and length of the register set -- #clock-cells: Should be <1> - -Optional properties: -- clocks: list of clock identifiers which are external input clocks to the - given clock controller. Please refer the next section to find - the input clocks for a given controller. -- clock-names: list of names of clocks which are external input clocks to the - given clock controller. - -Input clocks for top clock controller: - - sxosc (external crystal oscillator 32KHz, recommended) - - fxosc (external crystal oscillator 24MHz, recommended) - - audio_ext - - enet_ext - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h -for the full list of VF610 clock IDs. - -Examples: - -clks: ccm@4006b000 { - compatible = "fsl,vf610-ccm"; - reg = <0x4006b000 0x1000>; - #clock-cells = <1>; - clocks = <&sxosc>, <&fxosc>; - clock-names = "sxosc", "fxosc"; -}; - -uart1: serial@40028000 { - compatible = "fsl,vf610-uart"; - reg = <0x40028000 0x1000>; - interrupts = <0 62 0x04>; - clocks = <&clks VF610_CLK_UART1>; - clock-names = "ipg"; -}; diff --git a/Documentation/devicetree/bindings/counter/fsl,ftm-quaddec.yaml b/Documentation/devicetree/bindings/counter/fsl,ftm-quaddec.yaml new file mode 100644 index 0000000000000..384ca63b64d53 --- /dev/null +++ b/Documentation/devicetree/bindings/counter/fsl,ftm-quaddec.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/counter/fsl,ftm-quaddec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FlexTimer Quadrature decoder counter + +description: + Exposes a simple counter for the quadrature decoder mode. + +maintainers: + - Frank Li + +properties: + compatible: + const: fsl,ftm-quaddec + + reg: + maxItems: 1 + + big-endian: true + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + counter@29d0000 { + compatible = "fsl,ftm-quaddec"; + reg = <0x29d0000 0x10000>; + big-endian; + }; diff --git a/Documentation/devicetree/bindings/counter/ftm-quaddec.txt b/Documentation/devicetree/bindings/counter/ftm-quaddec.txt deleted file mode 100644 index 4d18cd7220745..0000000000000 --- a/Documentation/devicetree/bindings/counter/ftm-quaddec.txt +++ /dev/null @@ -1,18 +0,0 @@ -FlexTimer Quadrature decoder counter - -This driver exposes a simple counter for the quadrature decoder mode. - -Required properties: -- compatible: Must be "fsl,ftm-quaddec". -- reg: Must be set to the memory region of the flextimer. - -Optional property: -- big-endian: Access the device registers in big-endian mode. - -Example: - counter0: counter@29d0000 { - compatible = "fsl,ftm-quaddec"; - reg = <0x0 0x29d0000 0x0 0x10000>; - big-endian; - status = "disabled"; - }; diff --git a/Documentation/devicetree/bindings/cpu/cpu-topology.txt b/Documentation/devicetree/bindings/cpu/cpu-topology.txt deleted file mode 100644 index 9bd530a35d146..0000000000000 --- a/Documentation/devicetree/bindings/cpu/cpu-topology.txt +++ /dev/null @@ -1,553 +0,0 @@ -=========================================== -CPU topology binding description -=========================================== - -=========================================== -1 - Introduction -=========================================== - -In a SMP system, the hierarchy of CPUs is defined through three entities that -are used to describe the layout of physical CPUs in the system: - -- socket -- cluster -- core -- thread - -The bottom hierarchy level sits at core or thread level depending on whether -symmetric multi-threading (SMT) is supported or not. - -For instance in a system where CPUs support SMT, "cpu" nodes represent all -threads existing in the system and map to the hierarchy level "thread" above. -In systems where SMT is not supported "cpu" nodes represent all cores present -in the system and map to the hierarchy level "core" above. - -CPU topology bindings allow one to associate cpu nodes with hierarchical groups -corresponding to the system hierarchy; syntactically they are defined as device -tree nodes. - -Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be -used for any other architecture as well. - -The cpu nodes, as per bindings defined in [4], represent the devices that -correspond to physical CPUs and are to be mapped to the hierarchy levels. - -A topology description containing phandles to cpu nodes that are not compliant -with bindings standardized in [4] is therefore considered invalid. - -=========================================== -2 - cpu-map node -=========================================== - -The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct -child of the cpus node and provides a container where the actual topology -nodes are listed. - -- cpu-map node - - Usage: Optional - On SMP systems provide CPUs topology to the OS. - Uniprocessor systems do not require a topology - description and therefore should not define a - cpu-map node. - - Description: The cpu-map node is just a container node where its - subnodes describe the CPU topology. - - Node name must be "cpu-map". - - The cpu-map node's parent node must be the cpus node. - - The cpu-map node's child nodes can be: - - - one or more cluster nodes or - - one or more socket nodes in a multi-socket system - - Any other configuration is considered invalid. - -The cpu-map node can only contain 4 types of child nodes: - -- socket node -- cluster node -- core node -- thread node - -whose bindings are described in paragraph 3. - -The nodes describing the CPU topology (socket/cluster/core/thread) can -only be defined within the cpu-map node and every core/thread in the -system must be defined within the topology. Any other configuration is -invalid and therefore must be ignored. - -=========================================== -2.1 - cpu-map child nodes naming convention -=========================================== - -cpu-map child nodes must follow a naming convention where the node name -must be "socketN", "clusterN", "coreN", "threadN" depending on the node type -(ie socket/cluster/core/thread) (where N = {0, 1, ...} is the node number; nodes -which are siblings within a single common parent node must be given a unique and -sequential N value, starting from 0). -cpu-map child nodes which do not share a common parent node can have the same -name (ie same number N as other cpu-map child nodes at different device tree -levels) since name uniqueness will be guaranteed by the device tree hierarchy. - -=========================================== -3 - socket/cluster/core/thread node bindings -=========================================== - -Bindings for socket/cluster/cpu/thread nodes are defined as follows: - -- socket node - - Description: must be declared within a cpu-map node, one node - per physical socket in the system. A system can - contain single or multiple physical socket. - The association of sockets and NUMA nodes is beyond - the scope of this bindings, please refer [2] for - NUMA bindings. - - This node is optional for a single socket system. - - The socket node name must be "socketN" as described in 2.1 above. - A socket node can not be a leaf node. - - A socket node's child nodes must be one or more cluster nodes. - - Any other configuration is considered invalid. - -- cluster node - - Description: must be declared within a cpu-map node, one node - per cluster. A system can contain several layers of - clustering within a single physical socket and cluster - nodes can be contained in parent cluster nodes. - - The cluster node name must be "clusterN" as described in 2.1 above. - A cluster node can not be a leaf node. - - A cluster node's child nodes must be: - - - one or more cluster nodes; or - - one or more core nodes - - Any other configuration is considered invalid. - -- core node - - Description: must be declared in a cluster node, one node per core in - the cluster. If the system does not support SMT, core - nodes are leaf nodes, otherwise they become containers of - thread nodes. - - The core node name must be "coreN" as described in 2.1 above. - - A core node must be a leaf node if SMT is not supported. - - Properties for core nodes that are leaf nodes: - - - cpu - Usage: required - Value type: - Definition: a phandle to the cpu node that corresponds to the - core node. - - If a core node is not a leaf node (CPUs supporting SMT) a core node's - child nodes can be: - - - one or more thread nodes - - Any other configuration is considered invalid. - -- thread node - - Description: must be declared in a core node, one node per thread - in the core if the system supports SMT. Thread nodes are - always leaf nodes in the device tree. - - The thread node name must be "threadN" as described in 2.1 above. - - A thread node must be a leaf node. - - A thread node must contain the following property: - - - cpu - Usage: required - Value type: - Definition: a phandle to the cpu node that corresponds to - the thread node. - -=========================================== -4 - Example dts -=========================================== - -Example 1 (ARM 64-bit, 16-cpu system, two clusters of clusters in a single -physical socket): - -cpus { - #size-cells = <0>; - #address-cells = <2>; - - cpu-map { - socket0 { - cluster0 { - cluster0 { - core0 { - thread0 { - cpu = <&CPU0>; - }; - thread1 { - cpu = <&CPU1>; - }; - }; - - core1 { - thread0 { - cpu = <&CPU2>; - }; - thread1 { - cpu = <&CPU3>; - }; - }; - }; - - cluster1 { - core0 { - thread0 { - cpu = <&CPU4>; - }; - thread1 { - cpu = <&CPU5>; - }; - }; - - core1 { - thread0 { - cpu = <&CPU6>; - }; - thread1 { - cpu = <&CPU7>; - }; - }; - }; - }; - - cluster1 { - cluster0 { - core0 { - thread0 { - cpu = <&CPU8>; - }; - thread1 { - cpu = <&CPU9>; - }; - }; - core1 { - thread0 { - cpu = <&CPU10>; - }; - thread1 { - cpu = <&CPU11>; - }; - }; - }; - - cluster1 { - core0 { - thread0 { - cpu = <&CPU12>; - }; - thread1 { - cpu = <&CPU13>; - }; - }; - core1 { - thread0 { - cpu = <&CPU14>; - }; - thread1 { - cpu = <&CPU15>; - }; - }; - }; - }; - }; - }; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x0>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x1>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU4: cpu@10000 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10000>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU5: cpu@10001 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10001>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU6: cpu@10100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU7: cpu@10101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU8: cpu@100000000 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x0>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU9: cpu@100000001 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x1>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU10: cpu@100000100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU11: cpu@100000101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU12: cpu@100010000 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x10000>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU13: cpu@100010001 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x10001>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU14: cpu@100010100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x10100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU15: cpu@100010101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x10101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; -}; - -Example 2 (ARM 32-bit, dual-cluster, 8-cpu system, no SMT): - -cpus { - #size-cells = <0>; - #address-cells = <1>; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - core1 { - cpu = <&CPU1>; - }; - core2 { - cpu = <&CPU2>; - }; - core3 { - cpu = <&CPU3>; - }; - }; - - cluster1 { - core0 { - cpu = <&CPU4>; - }; - core1 { - cpu = <&CPU5>; - }; - core2 { - cpu = <&CPU6>; - }; - core3 { - cpu = <&CPU7>; - }; - }; - }; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x0>; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x1>; - }; - - CPU2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x2>; - }; - - CPU3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x3>; - }; - - CPU4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - }; - - CPU5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - }; - - CPU6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x102>; - }; - - CPU7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x103>; - }; -}; - -Example 3: HiFive Unleashed (RISC-V 64 bit, 4 core system) - -{ - #address-cells = <2>; - #size-cells = <2>; - compatible = "sifive,fu540g", "sifive,fu500"; - model = "sifive,hifive-unleashed-a00"; - - ... - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu-map { - socket0 { - cluster0 { - core0 { - cpu = <&CPU1>; - }; - core1 { - cpu = <&CPU2>; - }; - core2 { - cpu0 = <&CPU2>; - }; - core3 { - cpu0 = <&CPU3>; - }; - }; - }; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "sifive,rocket0", "riscv"; - reg = <0x1>; - } - - CPU2: cpu@2 { - device_type = "cpu"; - compatible = "sifive,rocket0", "riscv"; - reg = <0x2>; - } - CPU3: cpu@3 { - device_type = "cpu"; - compatible = "sifive,rocket0", "riscv"; - reg = <0x3>; - } - CPU4: cpu@4 { - device_type = "cpu"; - compatible = "sifive,rocket0", "riscv"; - reg = <0x4>; - } - } -}; -=============================================================================== -[1] ARM Linux kernel documentation - Documentation/devicetree/bindings/arm/cpus.yaml -[2] Devicetree NUMA binding description - Documentation/devicetree/bindings/numa.txt -[3] RISC-V Linux kernel documentation - Documentation/devicetree/bindings/riscv/cpus.yaml -[4] https://www.devicetree.org/specifications/ diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt deleted file mode 100644 index e0a4ba599abcd..0000000000000 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt +++ /dev/null @@ -1,250 +0,0 @@ -Binding for MediaTek's CPUFreq driver -===================================== - -Required properties: -- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names. -- clock-names: Should contain the following: - "cpu" - The multiplexer for clock input of CPU cluster. - "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock - source (usually MAINPLL) when the original CPU PLL is under - transition and not stable yet. - Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for - generic clock consumer properties. -- operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp-v2.yaml - for detail. -- proc-supply: Regulator for Vproc of CPU cluster. - -Optional properties: -- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver - needs to do "voltage tracking" to step by step scale up/down Vproc and - Vsram to fit SoC specific needs. When absent, the voltage scaling - flow is handled by hardware, hence no software "voltage tracking" is - needed. -- mediatek,cci: - Used to confirm the link status between cpufreq and mediatek cci. Because - cpufreq and mediatek cci could share the same regulator in some MediaTek SoCs. - To prevent the issue of high frequency and low voltage, we need to use this - property to make sure mediatek cci is ready. - For details of mediatek cci, please refer to - Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml -- #cooling-cells: - For details, please refer to - Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml - -Example 1 (MT7623 SoC): - - cpu_opp_table: opp_table { - compatible = "operating-points-v2"; - opp-shared; - - opp-598000000 { - opp-hz = /bits/ 64 <598000000>; - opp-microvolt = <1050000>; - }; - - opp-747500000 { - opp-hz = /bits/ 64 <747500000>; - opp-microvolt = <1050000>; - }; - - opp-1040000000 { - opp-hz = /bits/ 64 <1040000000>; - opp-microvolt = <1150000>; - }; - - opp-1196000000 { - opp-hz = /bits/ 64 <1196000000>; - opp-microvolt = <1200000>; - }; - - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1300000>; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - clocks = <&infracfg CLK_INFRA_CPUSEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - operating-points-v2 = <&cpu_opp_table>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - operating-points-v2 = <&cpu_opp_table>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - operating-points-v2 = <&cpu_opp_table>; - }; - -Example 2 (MT8173 SoC): - cpu_opp_table_a: opp_table_a { - compatible = "operating-points-v2"; - opp-shared; - - opp-507000000 { - opp-hz = /bits/ 64 <507000000>; - opp-microvolt = <859000>; - }; - - opp-702000000 { - opp-hz = /bits/ 64 <702000000>; - opp-microvolt = <908000>; - }; - - opp-1001000000 { - opp-hz = /bits/ 64 <1001000000>; - opp-microvolt = <983000>; - }; - - opp-1105000000 { - opp-hz = /bits/ 64 <1105000000>; - opp-microvolt = <1009000>; - }; - - opp-1183000000 { - opp-hz = /bits/ 64 <1183000000>; - opp-microvolt = <1028000>; - }; - - opp-1404000000 { - opp-hz = /bits/ 64 <1404000000>; - opp-microvolt = <1083000>; - }; - - opp-1508000000 { - opp-hz = /bits/ 64 <1508000000>; - opp-microvolt = <1109000>; - }; - - opp-1573000000 { - opp-hz = /bits/ 64 <1573000000>; - opp-microvolt = <1125000>; - }; - }; - - cpu_opp_table_b: opp_table_b { - compatible = "operating-points-v2"; - opp-shared; - - opp-507000000 { - opp-hz = /bits/ 64 <507000000>; - opp-microvolt = <828000>; - }; - - opp-702000000 { - opp-hz = /bits/ 64 <702000000>; - opp-microvolt = <867000>; - }; - - opp-1001000000 { - opp-hz = /bits/ 64 <1001000000>; - opp-microvolt = <927000>; - }; - - opp-1209000000 { - opp-hz = /bits/ 64 <1209000000>; - opp-microvolt = <968000>; - }; - - opp-1404000000 { - opp-hz = /bits/ 64 <1007000000>; - opp-microvolt = <1028000>; - }; - - opp-1612000000 { - opp-hz = /bits/ 64 <1612000000>; - opp-microvolt = <1049000>; - }; - - opp-1807000000 { - opp-hz = /bits/ 64 <1807000000>; - opp-microvolt = <1089000>; - }; - - opp-1989000000 { - opp-hz = /bits/ 64 <1989000000>; - opp-microvolt = <1125000>; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x000>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&infracfg CLK_INFRA_CA53SEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table_a>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x001>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&infracfg CLK_INFRA_CA53SEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table_a>; - }; - - cpu2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x100>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&infracfg CLK_INFRA_CA72SEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table_b>; - }; - - cpu3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x101>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&infracfg CLK_INFRA_CA72SEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table_b>; - }; - - &cpu0 { - proc-supply = <&mt6397_vpca15_reg>; - }; - - &cpu1 { - proc-supply = <&mt6397_vpca15_reg>; - }; - - &cpu2 { - proc-supply = <&da9211_vcpu_reg>; - sram-supply = <&mt6397_vsramca7_reg>; - }; - - &cpu3 { - proc-supply = <&da9211_vcpu_reg>; - sram-supply = <&mt6397_vsramca7_reg>; - }; diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml index e08c24633926b..5a99d9b9635e7 100644 --- a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml @@ -128,7 +128,7 @@ required: - power-domains - ports -additionalProperties: false +unevaluatedProperties: false examples: - | @@ -180,4 +180,69 @@ examples: }; }; }; + + - | + #include + + dsi1: dsi@10860000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,r9a07g044-mipi-dsi", "renesas,rzg2l-mipi-dsi"; + reg = <0x10860000 0x20000>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "seq0", "seq1", "vin1", "rcv", + "ferr", "ppi", "debug"; + clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>; + clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk"; + resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>, + <&cpg R9A07G044_MIPI_DSI_ARESET_N>, + <&cpg R9A07G044_MIPI_DSI_PRESET_N>; + reset-names = "rst", "arst", "prst"; + power-domains = <&cpg>; + + panel@0 { + compatible = "rocktech,jh057n00900"; + reg = <0>; + vcc-supply = <®_2v8_p>; + iovcc-supply = <®_1v8_p>; + reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi1_out>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&du_out_dsi1>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&panel_in>; + }; + }; + }; + }; ... diff --git a/Documentation/devicetree/bindings/display/fsl,tcon.txt b/Documentation/devicetree/bindings/display/fsl,tcon.txt deleted file mode 100644 index 475008747801e..0000000000000 --- a/Documentation/devicetree/bindings/display/fsl,tcon.txt +++ /dev/null @@ -1,17 +0,0 @@ -Device Tree bindings for Freescale TCON Driver - -Required properties: -- compatible: Should be one of - * "fsl,vf610-tcon". - -- reg: Address and length of the register set for tcon. -- clocks: From common clock binding: handle to tcon ipg clock. -- clock-names: From common clock binding: Shall be "ipg". - -Examples: -timing-controller@4003d000 { - compatible = "fsl,vf610-tcon"; - reg = <0x4003d000 0x1000>; - clocks = <&clks VF610_CLK_TCON0>; - clock-names = "ipg"; -}; diff --git a/Documentation/devicetree/bindings/display/fsl,vf610-tcon.yaml b/Documentation/devicetree/bindings/display/fsl,vf610-tcon.yaml new file mode 100644 index 0000000000000..06bd680524a56 --- /dev/null +++ b/Documentation/devicetree/bindings/display/fsl,vf610-tcon.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/fsl,vf610-tcon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale TCON + +maintainers: + - Frank Li + +properties: + compatible: + const: fsl,vf610-tcon + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: ipg + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + + timing-controller@4003d000 { + compatible = "fsl,vf610-tcon"; + reg = <0x4003d000 0x1000>; + clocks = <&clks VF610_CLK_TCON0>; + clock-names = "ipg"; + }; diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx-display-subsystem.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx-display-subsystem.yaml new file mode 100644 index 0000000000000..92a0a797d099a --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx-display-subsystem.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx-display-subsystem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX DRM master device + +maintainers: + - Frank Li + +description: + The freescale i.MX DRM master device is a virtual device needed to list all + IPU or other display interface nodes that comprise the graphics subsystem. + +properties: + compatible: + const: fsl,imx-display-subsystem + + ports: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Should contain a list of phandles pointing to camera + sensor interface ports of IPU devices. + +required: + - compatible + +additionalProperties: false + +examples: + - | + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&ipu_di0>; + }; diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx-parallel-display.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx-parallel-display.yaml new file mode 100644 index 0000000000000..bbcfe7e2958b7 --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx-parallel-display.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx-parallel-display.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Parallel display support + +maintainers: + - Frank Li + +properties: + compatible: + const: fsl,imx-parallel-display + + interface-pix-fmt: + $ref: /schemas/types.yaml#/definitions/string + enum: + - rgb24 + - rgb565 + - bgr666 + - lvds666 + + ddc: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle describing the i2c bus handling the display data channel + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: input port connected to the IPU display interface + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: output port connected to a panel + +required: + - compatible + +additionalProperties: false + +examples: + - | + display { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + + port@0 { + reg = <0>; + + endpoint { + remote-endpoint = <&ipu_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx6q-ipu.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx6q-ipu.yaml new file mode 100644 index 0000000000000..ec78645d4de00 --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx6q-ipu.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx6q-ipu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX IPUv3 + +maintainers: + - Frank Li + +properties: + compatible: + oneOf: + - enum: + - fsl,imx51-ipu + - fsl,imx53-ipu + - fsl,imx6q-ipu + - items: + - const: fsl,imx6qp-ipu + - const: fsl,imx6q-ipu + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 2 + + clocks: + maxItems: 3 + + clock-names: + items: + - const: bus + - const: di0 + - const: di1 + + resets: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + fsl,prg: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to prg node associated with this IPU instance + + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: CSI0 + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: CSI1 + + port@2: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: DI0 + + port@3: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: DI1 + +required: + - compatible + - reg + - interrupts + - resets + +additionalProperties: false + +examples: + - | + display-controller@18000000 { + compatible = "fsl,imx53-ipu"; + reg = <0x18000000 0x080000000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <11 10>; + resets = <&src 2>; + + port@2 { + reg = <2>; + + endpoint { + remote-endpoint = <&display_in>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx6q-ldb.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx6q-ldb.yaml new file mode 100644 index 0000000000000..1646f41d8f728 --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx6q-ldb.yaml @@ -0,0 +1,193 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx6q-ldb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale LVDS Display Bridge (ldb) + +description: + The LVDS Display Bridge device tree node contains up to two lvds-channel + nodes describing each of the two LVDS encoder channels of the bridge. + +maintainers: + - Frank Li + +properties: + compatible: + oneOf: + - enum: + - fsl,imx53-ldb + - items: + - enum: + - fsl,imx6q-ldb + - const: fsl,imx53-ldb + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + gpr: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle points to the iomuxc-gpr region containing the LVDS + control register. + + clocks: + minItems: 6 + maxItems: 8 + + clock-names: + oneOf: + - items: + - const: di0_pll + - const: di1_pll + - const: di0_sel + - const: di1_sel + - const: di0 + - const: di1 + - items: + - const: di0_pll + - const: di1_pll + - const: di0_sel + - const: di1_sel + - const: di2_sel + - const: di3_sel + - const: di0 + - const: di1 + + fsl,dual-channel: + $ref: /schemas/types.yaml#/definitions/flag + description: + if it exists, only LVDS channel 0 should + be configured - one input will be distributed on both outputs in dual + channel mode + +patternProperties: + '^lvds-channel@[0-1]$': + type: object + description: + Each LVDS Channel has to contain either an of graph link to a panel device node + or a display-timings node that describes the video timings for the connected + LVDS display as well as the fsl,data-mapping and fsl,data-width properties. + + properties: + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + display-timings: + $ref: /schemas/display/panel/display-timings.yaml# + + fsl,data-mapping: + enum: + - spwg + - jeida + + fsl,data-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: should be <18> or <24> + enum: + - 18 + - 24 + + fsl,panel: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to lcd panel + + patternProperties: + '^port@[0-4]$': + $ref: /schemas/graph.yaml#/properties/port + description: + On i.MX5, the internal two-input-multiplexer is used. Due to hardware + limitations, only one input port (port@[0,1]) can be used for each channel + (lvds-channel@[0,1], respectively). + On i.MX6, there should be four input ports (port@[0-3]) that correspond + to the four LVDS multiplexer inputs. + A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected + to a panel input port. Optionally, the output port can be left out if + display-timings are used instead. + + additionalProperties: false + +required: + - compatible + - gpr + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + + ldb@53fa8008 { + compatible = "fsl,imx53-ldb"; + reg = <0x53fa8008 0x4>; + #address-cells = <1>; + #size-cells = <0>; + gpr = <&gpr>; + clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, + <&clks IMX5_CLK_LDB_DI1_SEL>, + <&clks IMX5_CLK_IPU_DI0_SEL>, + <&clks IMX5_CLK_IPU_DI1_SEL>, + <&clks IMX5_CLK_LDB_DI0_GATE>, + <&clks IMX5_CLK_LDB_DI1_GATE>; + clock-names = "di0_pll", "di1_pll", + "di0_sel", "di1_sel", + "di0", "di1"; + + /* Using an of-graph endpoint link to connect the panel */ + lvds-channel@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + endpoint { + remote-endpoint = <&ipu_di0_lvds0>; + }; + }; + + port@2 { + reg = <2>; + + endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + /* Using display-timings and fsl,data-mapping/width instead */ + lvds-channel@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + + display-timings {/* ... */ + }; + + port@1 { + reg = <1>; + + endpoint { + remote-endpoint = <&ipu_di1_lvds1>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx6qp-pre.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx6qp-pre.yaml new file mode 100644 index 0000000000000..73bc73ff6e693 --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx6qp-pre.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx6qp-pre.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX PRE (Prefetch Resolve Engine) + +maintainers: + - Frank Li + +properties: + compatible: + const: fsl,imx6qp-pre + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: axi + fsl,iram: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle pointing to the mmio-sram device node, that should be + used for the PRE SRAM double buffer. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + pre@21c8000 { + compatible = "fsl,imx6qp-pre"; + reg = <0x021c8000 0x1000>; + interrupts = ; + clocks = <&clks IMX6QDL_CLK_PRE0>; + clock-names = "axi"; + fsl,iram = <&ocram2>; + }; diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx6qp-prg.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx6qp-prg.yaml new file mode 100644 index 0000000000000..582da8c489f45 --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx6qp-prg.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx6qp-prg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX PRG (Prefetch Resolve Gasket) + +maintainers: + - Frank Li + +properties: + compatible: + const: fsl,imx6qp-prg + + reg: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: ipg + - const: axi + + fsl,pres: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + maxItems: 1 + description: + phandles to the PRE units attached to this PRG, with the fixed + PRE as the first entry and the muxable PREs following. + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + + prg@21cc000 { + compatible = "fsl,imx6qp-prg"; + reg = <0x021cc000 0x1000>; + clocks = <&clks IMX6QDL_CLK_PRG0_APB>, <&clks IMX6QDL_CLK_PRG0_AXI>; + clock-names = "ipg", "axi"; + fsl,pres = <&pre1>, <&pre2>, <&pre3>; + }; + diff --git a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt deleted file mode 100644 index 269b1ae2fca99..0000000000000 --- a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt +++ /dev/null @@ -1,160 +0,0 @@ -Freescale i.MX DRM master device -================================ - -The freescale i.MX DRM master device is a virtual device needed to list all -IPU or other display interface nodes that comprise the graphics subsystem. - -Required properties: -- compatible: Should be "fsl,imx-display-subsystem" -- ports: Should contain a list of phandles pointing to display interface ports - of IPU devices - -example: - -display-subsystem { - compatible = "fsl,imx-display-subsystem"; - ports = <&ipu_di0>; -}; - - -Freescale i.MX IPUv3 -==================== - -Required properties: -- compatible: Should be "fsl,-ipu" where is one of - - imx51 - - imx53 - - imx6q - - imx6qp -- reg: should be register base and length as documented in the - datasheet -- interrupts: Should contain sync interrupt and error interrupt, - in this order. -- resets: phandle pointing to the system reset controller and - reset line index, see reset/fsl,imx-src.txt for details -Additional required properties for fsl,imx6qp-ipu: -- fsl,prg: phandle to prg node associated with this IPU instance -Optional properties: -- port@[0-3]: Port nodes with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. - Ports 0 and 1 should correspond to CSI0 and CSI1, - ports 2 and 3 should correspond to DI0 and DI1, respectively. - -example: - -ipu: ipu@18000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-ipu"; - reg = <0x18000000 0x080000000>; - interrupts = <11 10>; - resets = <&src 2>; - - ipu_di0: port@2 { - reg = <2>; - - ipu_di0_disp0: endpoint { - remote-endpoint = <&display_in>; - }; - }; -}; - -Freescale i.MX PRE (Prefetch Resolve Engine) -============================================ - -Required properties: -- compatible: should be "fsl,imx6qp-pre" -- reg: should be register base and length as documented in the - datasheet -- clocks : phandle to the PRE axi clock input, as described - in Documentation/devicetree/bindings/clock/clock-bindings.txt and - Documentation/devicetree/bindings/clock/imx6q-clock.yaml. -- clock-names: should be "axi" -- interrupts: should contain the PRE interrupt -- fsl,iram: phandle pointing to the mmio-sram device node, that should be - used for the PRE SRAM double buffer. - -example: - -pre@21c8000 { - compatible = "fsl,imx6qp-pre"; - reg = <0x021c8000 0x1000>; - interrupts = ; - clocks = <&clks IMX6QDL_CLK_PRE0>; - clock-names = "axi"; - fsl,iram = <&ocram2>; -}; - -Freescale i.MX PRG (Prefetch Resolve Gasket) -============================================ - -Required properties: -- compatible: should be "fsl,imx6qp-prg" -- reg: should be register base and length as documented in the - datasheet -- clocks : phandles to the PRG ipg and axi clock inputs, as described - in Documentation/devicetree/bindings/clock/clock-bindings.txt and - Documentation/devicetree/bindings/clock/imx6q-clock.yaml. -- clock-names: should be "ipg" and "axi" -- fsl,pres: phandles to the PRE units attached to this PRG, with the fixed - PRE as the first entry and the muxable PREs following. - -example: - -prg@21cc000 { - compatible = "fsl,imx6qp-prg"; - reg = <0x021cc000 0x1000>; - clocks = <&clks IMX6QDL_CLK_PRG0_APB>, - <&clks IMX6QDL_CLK_PRG0_AXI>; - clock-names = "ipg", "axi"; - fsl,pres = <&pre1>, <&pre2>, <&pre3>; -}; - -Parallel display support -======================== - -Required properties: -- compatible: Should be "fsl,imx-parallel-display" -Optional properties: -- interface-pix-fmt: How this display is connected to the - display interface. Currently supported types: "rgb24", "rgb565", "bgr666" - and "lvds666". -- ddc: phandle describing the i2c bus handling the display data - channel -- port@[0-1]: Port nodes with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. - Port 0 is the input port connected to the IPU display interface, - port 1 is the output port connected to a panel. - -example: - -disp0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - - port@0 { - reg = <0>; - - display_in: endpoint { - remote-endpoint = <&ipu_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -panel { - ... - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/imx/ldb.txt b/Documentation/devicetree/bindings/display/imx/ldb.txt deleted file mode 100644 index 03653a291b549..0000000000000 --- a/Documentation/devicetree/bindings/display/imx/ldb.txt +++ /dev/null @@ -1,146 +0,0 @@ -Device-Tree bindings for LVDS Display Bridge (ldb) - -LVDS Display Bridge -=================== - -The LVDS Display Bridge device tree node contains up to two lvds-channel -nodes describing each of the two LVDS encoder channels of the bridge. - -Required properties: - - #address-cells : should be <1> - - #size-cells : should be <0> - - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb". - Both LDB versions are similar, but i.MX6 has an additional - multiplexer in the front to select any of the four IPU display - interfaces as input for each LVDS channel. - - gpr : should be <&gpr> on i.MX53 and i.MX6q. - The phandle points to the iomuxc-gpr region containing the LVDS - control register. -- clocks, clock-names : phandles to the LDB divider and selector clocks and to - the display interface selector clocks, as described in - Documentation/devicetree/bindings/clock/clock-bindings.txt - The following clocks are expected on i.MX53: - "di0_pll" - LDB LVDS channel 0 mux - "di1_pll" - LDB LVDS channel 1 mux - "di0" - LDB LVDS channel 0 gate - "di1" - LDB LVDS channel 1 gate - "di0_sel" - IPU1 DI0 mux - "di1_sel" - IPU1 DI1 mux - On i.MX6q the following additional clocks are needed: - "di2_sel" - IPU2 DI0 mux - "di3_sel" - IPU2 DI1 mux - The needed clock numbers for each are documented in - Documentation/devicetree/bindings/clock/imx5-clock.yaml, and in - Documentation/devicetree/bindings/clock/imx6q-clock.yaml. - -Optional properties: - - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q - - pinctrl-0 : a phandle pointing to LVDS pin settings on i.MX53, - not used on i.MX6q - - fsl,dual-channel : boolean. if it exists, only LVDS channel 0 should - be configured - one input will be distributed on both outputs in dual - channel mode - -LVDS Channel -============ - -Each LVDS Channel has to contain either an of graph link to a panel device node -or a display-timings node that describes the video timings for the connected -LVDS display as well as the fsl,data-mapping and fsl,data-width properties. - -Required properties: - - reg : should be <0> or <1> - - port: Input and output port nodes with endpoint definitions as defined in - Documentation/devicetree/bindings/graph.txt. - On i.MX5, the internal two-input-multiplexer is used. Due to hardware - limitations, only one input port (port@[0,1]) can be used for each channel - (lvds-channel@[0,1], respectively). - On i.MX6, there should be four input ports (port@[0-3]) that correspond - to the four LVDS multiplexer inputs. - A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected - to a panel input port. Optionally, the output port can be left out if - display-timings are used instead. - -Optional properties (required if display-timings are used): - - display-timings : A node that describes the display timings as defined in - Documentation/devicetree/bindings/display/panel/display-timing.txt. - - fsl,data-mapping : should be "spwg" or "jeida" - This describes how the color bits are laid out in the - serialized LVDS signal. - - fsl,data-width : should be <18> or <24> - -example: - -gpr: iomuxc-gpr@53fa8000 { - /* ... */ -}; - -ldb: ldb@53fa8008 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-ldb"; - gpr = <&gpr>; - clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, - <&clks IMX5_CLK_LDB_DI1_SEL>, - <&clks IMX5_CLK_IPU_DI0_SEL>, - <&clks IMX5_CLK_IPU_DI1_SEL>, - <&clks IMX5_CLK_LDB_DI0_GATE>, - <&clks IMX5_CLK_LDB_DI1_GATE>; - clock-names = "di0_pll", "di1_pll", - "di0_sel", "di1_sel", - "di0", "di1"; - - /* Using an of-graph endpoint link to connect the panel */ - lvds-channel@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - port@0 { - reg = <0>; - - lvds0_in: endpoint { - remote-endpoint = <&ipu_di0_lvds0>; - }; - }; - - port@2 { - reg = <2>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - - /* Using display-timings and fsl,data-mapping/width instead */ - lvds-channel@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - fsl,data-mapping = "spwg"; - fsl,data-width = <24>; - - display-timings { - /* ... */ - }; - - port@1 { - reg = <1>; - - lvds1_in: endpoint { - remote-endpoint = <&ipu_di1_lvds1>; - }; - }; - }; -}; - -panel: lvds-panel { - /* ... */ - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml index 5d2089dc596ec..daf90ebb39bfa 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml @@ -25,6 +25,10 @@ properties: - mediatek,mt8173-disp-aal - mediatek,mt8183-disp-aal - mediatek,mt8195-mdp3-aal + - items: + - enum: + - mediatek,mt8188-mdp3-aal + - const: mediatek,mt8195-mdp3-aal - items: - enum: - mediatek,mt2712-disp-aal diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml index 6160439ce4d7e..5564f4063317b 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml @@ -27,6 +27,10 @@ properties: - mediatek,mt8167-disp-color - mediatek,mt8173-disp-color - mediatek,mt8195-mdp3-color + - items: + - enum: + - mediatek,mt8188-mdp3-color + - const: mediatek,mt8195-mdp3-color - items: - enum: - mediatek,mt7623-disp-color diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml index 0de9f64f3f845..3798a25402d3c 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml @@ -25,6 +25,10 @@ properties: - mediatek,mt8173-disp-merge - mediatek,mt8195-disp-merge - mediatek,mt8195-mdp3-merge + - items: + - enum: + - mediatek,mt8188-mdp3-merge + - const: mediatek,mt8195-mdp3-merge - items: - const: mediatek,mt6795-disp-merge - const: mediatek,mt8173-disp-merge diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml new file mode 100644 index 0000000000000..bde4dc556d4f9 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek HDMI MT8195 series HDMI Display Data Channel (DDC) + +maintainers: + - AngeloGioacchino Del Regno + - CK Hu + +properties: + compatible: + oneOf: + - const: mediatek,mt8195-hdmi-ddc + - items: + - const: mediatek,mt8188-hdmi-ddc + - const: mediatek,mt8195-hdmi-ddc + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - clocks + +additionalProperties: false + +examples: + - | + hdmi { + hdmi_ddc: i2c { + compatible = "mediatek,mt8195-hdmi-ddc"; + clocks = <&clk26m>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml new file mode 100644 index 0000000000000..1b382f99d3ced --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml @@ -0,0 +1,151 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT8195 series HDMI-TX Encoder + +maintainers: + - AngeloGioacchino Del Regno + - CK Hu + +description: + The MediaTek HDMI-TX v2 encoder can generate HDMI format data based on + the HDMI Specification 2.0b. + +properties: + compatible: + enum: + - mediatek,mt8188-hdmi-tx + - mediatek,mt8195-hdmi-tx + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: HDMI Peripheral Bus (APB) clock + - description: HDCP and HDMI_TOP clock + - description: HDCP, HDMI_TOP and HDMI Audio reference clock + - description: VPP HDMI Split clock + + clock-names: + items: + - const: bus + - const: hdcp + - const: hdcp24m + - const: hdmi-split + + i2c: + type: object + $ref: /schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml + unevaluatedProperties: false + description: HDMI DDC I2C controller + + phys: + maxItems: 1 + description: PHY providing clocking TMDS and pixel to controller + + phy-names: + items: + - const: hdmi + + power-domains: + maxItems: 1 + + '#sound-dai-cells': + const: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: + Input port, usually connected to the output port of a DPI + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + Output port that must be connected either to the input port of + a HDMI connector node containing a ddc-i2c-bus, or to the input + port of an attached bridge chip, such as a SlimPort transmitter. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + - phys + - phy-names + - ports + +allOf: + - $ref: /schemas/sound/dai-common.yaml# + +additionalProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + hdmi@1c300000 { + compatible = "mediatek,mt8195-hdmi-tx"; + reg = <0 0x1c300000 0 0x1000>; + clocks = <&topckgen CLK_TOP_HDMI_APB>, + <&topckgen CLK_TOP_HDCP>, + <&topckgen CLK_TOP_HDCP_24M>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>; + clock-names = "bus", "hdcp", "hdcp24m", "hdmi-split"; + interrupts = ; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + power-domains = <&spm MT8195_POWER_DOMAIN_HDMI_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins>; + #sound-dai-cells = <1>; + + hdmitx_ddc: i2c { + compatible = "mediatek,mt8195-hdmi-ddc"; + clocks = <&clk26m>; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_in: endpoint { + remote-endpoint = <&dpi1_out>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml index be07bbdc54e34..86787866ced0f 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml @@ -20,9 +20,13 @@ description: properties: compatible: - enum: - - mediatek,mt8188-disp-padding - - mediatek,mt8195-mdp3-padding + oneOf: + - enum: + - mediatek,mt8188-disp-padding + - mediatek,mt8195-mdp3-padding + - items: + - const: mediatek,mt8188-mdp3-padding + - const: mediatek,mt8195-mdp3-padding reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index e00b88332f2fe..246bbb509bea1 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -31,6 +31,7 @@ properties: - qcom,sm8650-dp - items: - enum: + - qcom,sar2130p-dp - qcom,sm6350-dp - qcom,sm8150-dp - qcom,sm8250-dp diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index 2aab33cd0017c..82fe95a6d9599 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -23,6 +23,8 @@ properties: - qcom,msm8996-dsi-ctrl - qcom,msm8998-dsi-ctrl - qcom,qcm2290-dsi-ctrl + - qcom,sa8775p-dsi-ctrl + - qcom,sar2130p-dsi-ctrl - qcom,sc7180-dsi-ctrl - qcom,sc7280-dsi-ctrl - qcom,sdm660-dsi-ctrl @@ -314,6 +316,8 @@ allOf: contains: enum: - qcom,msm8998-dsi-ctrl + - qcom,sa8775p-dsi-ctrl + - qcom,sar2130p-dsi-ctrl - qcom,sc7180-dsi-ctrl - qcom,sc7280-dsi-ctrl - qcom,sdm845-dsi-ctrl diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml index 321470435e654..3c75ff42999a5 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml @@ -17,6 +17,8 @@ properties: enum: - qcom,dsi-phy-7nm - qcom,dsi-phy-7nm-8150 + - qcom,sa8775p-dsi-phy-5nm + - qcom,sar2130p-dsi-phy-5nm - qcom,sc7280-dsi-phy-7nm - qcom,sm6375-dsi-phy-7nm - qcom,sm8350-dsi-phy-5nm diff --git a/Documentation/devicetree/bindings/display/msm/hdmi.yaml b/Documentation/devicetree/bindings/display/msm/hdmi.yaml index d4a2033afea8d..dfec6c3480f3f 100644 --- a/Documentation/devicetree/bindings/display/msm/hdmi.yaml +++ b/Documentation/devicetree/bindings/display/msm/hdmi.yaml @@ -66,21 +66,6 @@ properties: maxItems: 1 description: hpd pin - qcom,hdmi-tx-mux-en-gpios: - maxItems: 1 - deprecated: true - description: HDMI mux enable pin - - qcom,hdmi-tx-mux-sel-gpios: - maxItems: 1 - deprecated: true - description: HDMI mux select pin - - qcom,hdmi-tx-mux-lpm-gpios: - maxItems: 1 - deprecated: true - description: HDMI mux lpm pin - '#sound-dai-cells': const: 1 @@ -89,12 +74,12 @@ properties: $ref: /schemas/graph.yaml#/properties/ports properties: port@0: - $ref: /schemas/graph.yaml#/$defs/port-base + $ref: /schemas/graph.yaml#/properties/port description: | Input endpoints of the controller. port@1: - $ref: /schemas/graph.yaml#/$defs/port-base + $ref: /schemas/graph.yaml#/properties/port description: | Output endpoints of the controller. diff --git a/Documentation/devicetree/bindings/display/msm/mdp4.yaml b/Documentation/devicetree/bindings/display/msm/mdp4.yaml index 35204a2875795..03ee09faa335f 100644 --- a/Documentation/devicetree/bindings/display/msm/mdp4.yaml +++ b/Documentation/devicetree/bindings/display/msm/mdp4.yaml @@ -18,9 +18,10 @@ properties: clocks: minItems: 6 - maxItems: 6 + maxItems: 8 clock-names: + minItems: 6 items: - const: core_clk - const: iface_clk @@ -28,6 +29,12 @@ properties: - const: lut_clk - const: hdmi_clk - const: tv_clk + - const: lcdc_clk + - const: pxo + description: XO used to drive the internal LVDS PLL + + '#clock-cells': + const: 0 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml index 7c6462caa4428..db9c43b20e2a7 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml @@ -84,6 +84,18 @@ properties: items: - description: MDSS_CORE reset + interconnects: + minItems: 1 + items: + - description: Interconnect path from mdp0 (or a single mdp) port to the data bus + - description: Interconnect path from CPU to the reg bus + + interconnect-names: + minItems: 1 + items: + - const: mdp0-mem + - const: cpu-cfg + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml index 5fac3e2667032..1053b3bc49086 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml @@ -52,12 +52,23 @@ patternProperties: items: - const: qcom,sa8775p-dp + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + contains: + const: qcom,sa8775p-dsi-ctrl + "^phy@[0-9a-f]+$": type: object additionalProperties: true properties: compatible: - const: qcom,sa8775p-edp-phy + contains: + enum: + - qcom,sa8775p-dsi-phy-5nm + - qcom,sa8775p-edp-phy required: - compatible @@ -139,6 +150,20 @@ examples: remote-endpoint = <&mdss0_dp0_in>; }; }; + + port@1 { + reg = <1>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss0_dsi0_in>; + }; + }; + + port@2 { + reg = <2>; + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss0_dsi1_in>; + }; + }; }; mdss0_mdp_opp_table: opp-table { @@ -186,6 +211,160 @@ examples: vdda-pll-supply = <&vreg_l4a>; }; + dsi@ae94000 { + compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispc_byte_clk>, + <&dispcc_intf_clk>, + <&dispcc_pclk>, + <&dispcc_esc_clk>, + <&dispcc_ahb_clk>, + <&gcc_bus_clk>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc_byte_clk>, + <&dispcc_pclk>; + assigned-clock-parents = <&mdss0_dsi0_phy 0>, <&mdss0_dsi0_phy 1>; + phys = <&mdss0_dsi0_phy>; + + operating-points-v2 = <&dsi0_opp_table>; + power-domains = <&rpmhpd SA8775P_MMCX>; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss0_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss0_dsi0_out: endpoint { }; + }; + }; + + dsi0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss0_dsi0_phy: phy@ae94400 { + compatible = "qcom,sa8775p-dsi-phy-5nm"; + reg = <0x0ae94400 0x200>, + <0x0ae94600 0x280>, + <0x0ae94900 0x27c>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc_iface_clk>, + <&rpmhcc_ref_clk>; + clock-names = "iface", "ref"; + + vdds-supply = <&vreg_dsi_supply>; + }; + + dsi@ae96000 { + compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae96000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispc_byte_clk>, + <&dispcc_intf_clk>, + <&dispcc_pclk>, + <&dispcc_esc_clk>, + <&dispcc_ahb_clk>, + <&gcc_bus_clk>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc_byte_clk>, + <&dispcc_pclk>; + assigned-clock-parents = <&mdss0_dsi1_phy 0>, <&mdss0_dsi1_phy 1>; + phys = <&mdss0_dsi1_phy>; + + operating-points-v2 = <&dsi1_opp_table>; + power-domains = <&rpmhpd SA8775P_MMCX>; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss0_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + mdss0_dsi1_out: endpoint { }; + }; + }; + + dsi1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss0_dsi1_phy: phy@ae96400 { + compatible = "qcom,sa8775p-dsi-phy-5nm"; + reg = <0x0ae96400 0x200>, + <0x0ae96600 0x280>, + <0x0ae96900 0x27c>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc_iface_clk>, + <&rpmhcc_ref_clk>; + clock-names = "iface", "ref"; + + vdds-supply = <&vreg_dsi_supply>; + }; + displayport-controller@af54000 { compatible = "qcom,sa8775p-dp"; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml new file mode 100644 index 0000000000000..870144b53cec9 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml @@ -0,0 +1,439 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sar2130p-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SAR2130P Display MDSS + +maintainers: + - Dmitry Baryshkov + +description: + SAR2310P MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like + DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sar2130p-mdss + + clocks: + items: + - description: Display MDSS AHB + - description: Display AHB + - description: Display hf AXI + - description: Display core + + iommus: + maxItems: 1 + + interconnects: + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus + + interconnect-names: + items: + - const: mdp0-mem + - const: cpu-cfg + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,sar2130p-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + contains: + const: qcom,sar2130p-dp + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + contains: + const: qcom,sar2130p-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,sar2130p-dsi-phy-5nm + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + display-subsystem@ae00000 { + compatible = "qcom,sar2130p-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc_master_mdp &mc_virt_slave_ebi1>, + <&gem_noc_master_appss_proc &config_noc_slave_display_cfg>; + interconnect-names = "mdp0-mem", "cpu-cfg"; + + resets = <&dispcc_disp_cc_mdss_core_bcr>; + + power-domains = <&dispcc_mdss_gdsc>; + + clocks = <&dispcc_disp_cc_mdss_ahb_clk>, + <&gcc_gcc_disp_ahb_clk>, + <&gcc_gcc_disp_hf_axi_clk>, + <&dispcc_disp_cc_mdss_mdp_clk>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x1c00 0x2>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sar2130p-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc_gcc_disp_ahb_clk>, + <&gcc_gcc_disp_hf_axi_clk>, + <&dispcc_disp_cc_mdss_ahb_clk>, + <&dispcc_disp_cc_mdss_mdp_lut_clk>, + <&dispcc_disp_cc_mdss_mdp_clk>, + <&dispcc_disp_cc_mdss_vsync_clk>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc_disp_cc_mdss_vsync_clk>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; + }; + }; + + port@1 { + reg = <1>; + + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@2 { + reg = <2>; + + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-514000000 { + opp-hz = /bits/ 64 <514000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + displayport-controller@ae90000 { + compatible = "qcom,sar2130p-dp", + "qcom,sm8350-dp"; + reg = <0xae90000 0x200>, + <0xae90200 0x200>, + <0xae90400 0xc00>, + <0xae91000 0x400>, + <0xae91400 0x400>; + + interrupt-parent = <&mdss>; + interrupts = <12>; + clocks = <&dispcc_disp_cc_mdss_ahb_clk>, + <&dispcc_disp_cc_mdss_dptx0_aux_clk>, + <&dispcc_disp_cc_mdss_dptx0_link_clk>, + <&dispcc_disp_cc_mdss_dptx0_link_intf_clk>, + <&dispcc_disp_cc_mdss_dptx0_pixel0_clk>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc_disp_cc_mdss_dptx0_link_clk_src>, + <&dispcc_disp_cc_mdss_dptx0_pixel0_clk_src>; + assigned-clock-parents = <&usb_dp_qmpphy_QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy_QMP_USB43DP_DP_VCO_DIV_CLK>; + + phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dp0_out: endpoint { + remote-endpoint = <&usb_dp_qmpphy_dp_in>; + }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi@ae94000 { + compatible = "qcom,sar2130p-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc_disp_cc_mdss_byte0_clk>, + <&dispcc_disp_cc_mdss_byte0_intf_clk>, + <&dispcc_disp_cc_mdss_pclk0_clk>, + <&dispcc_disp_cc_mdss_esc0_clk>, + <&dispcc_disp_cc_mdss_ahb_clk>, + <&gcc_gcc_disp_hf_axi_clk>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc_disp_cc_mdss_byte0_clk_src>, + <&dispcc_disp_cc_mdss_pclk0_clk_src>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible = "qcom,sar2130p-dsi-phy-5nm"; + reg = <0x0ae95000 0x200>, + <0x0ae95200 0x280>, + <0x0ae95500 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc_disp_cc_mdss_ahb_clk>, + <&rpmhcc_rpmh_cxo_clk>; + clock-names = "iface", "ref"; + }; + + dsi@ae96000 { + compatible = "qcom,sar2130p-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0x0ae96000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc_disp_cc_mdss_byte1_clk>, + <&dispcc_disp_cc_mdss_byte1_intf_clk>, + <&dispcc_disp_cc_mdss_pclk1_clk>, + <&dispcc_disp_cc_mdss_esc1_clk>, + <&dispcc_disp_cc_mdss_ahb_clk>, + <&gcc_gcc_disp_hf_axi_clk>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc_disp_cc_mdss_byte1_clk_src>, + <&dispcc_disp_cc_mdss_pclk1_clk_src>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&mdss_dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae97000 { + compatible = "qcom,sar2130p-dsi-phy-5nm"; + reg = <0x0ae97000 0x200>, + <0x0ae97200 0x280>, + <0x0ae97500 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc_disp_cc_mdss_ahb_clk>, + <&rpmhcc_rpmh_cxo_clk>; + clock-names = "iface", "ref"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml index 6902795b4e2c2..df9ec15ad6c3c 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml @@ -17,6 +17,7 @@ $ref: /schemas/display/msm/dpu-common.yaml# properties: compatible: enum: + - qcom,sar2130p-dpu - qcom,sc7280-dpu - qcom,sc8280xp-dpu - qcom,sm8350-dpu diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml index 163fc83c1e80c..68176de854b36 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml @@ -38,12 +38,16 @@ properties: maxItems: 1 interconnects: - maxItems: 2 + items: + - description: Interconnect path from the MDP0 port to the data bus + - description: Interconnect path from the MDP1 port to the data bus + - description: Interconnect path from the CPU to the reg bus interconnect-names: items: - const: mdp0-mem - const: mdp1-mem + - const: cpu-cfg patternProperties: "^display-controller@[0-9a-f]+$": @@ -88,6 +92,7 @@ examples: #include #include #include + #include #include #include @@ -97,8 +102,10 @@ examples: reg-names = "mdss"; interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, - <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; - interconnect-names = "mdp0-mem", "mdp1-mem"; + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", "mdp1-mem", "cpu-cfg"; power-domains = <&dispcc MDSS_GDSC>; resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; diff --git a/Documentation/devicetree/bindings/display/panel/boe,td4320.yaml b/Documentation/devicetree/bindings/display/panel/boe,td4320.yaml new file mode 100644 index 0000000000000..c6bff0ece360e --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/boe,td4320.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/boe,td4320.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: BOE TD4320 MIPI-DSI panels + +maintainers: + - Barnabas Czeman + +description: + BOE TD4320 6.3" 1080x2340 panel found in Xiaomi Redmi Note 7 smartphone. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - const: boe,td4320 + + reg: + maxItems: 1 + + iovcc-supply: + description: I/O voltage rail + + vsn-supply: + description: Negative source voltage rail + + vsp-supply: + description: Positive source voltage rail + +required: + - compatible + - reg + - reset-gpios + - port + +unevaluatedProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "boe,td4320"; + reg = <0>; + backlight = <&backlight>; + reset-gpios = <&tlmm 45 GPIO_ACTIVE_LOW>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/panel/himax,hx8279.yaml b/Documentation/devicetree/bindings/display/panel/himax,hx8279.yaml new file mode 100644 index 0000000000000..f619aea82bdf6 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/himax,hx8279.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/himax,hx8279.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Himax HX8279/HX8279-D based MIPI-DSI panels + +maintainers: + - AngeloGioacchino Del Regno + +description: + The Himax HX8279 is a 1803 channel outputs source driver with MIPI + TCON, which generates the horizontal and vertical control timing to + the source and gate drivers. + This DriverIC is most suitable for 1200x1920, 1080x1920, 1200x1600, + and 600x1024 panels and outputs full RGB888 over two or four lanes, + single or dual, MIPI-DSI video interface. + +allOf: + - $ref: panel-common-dual.yaml# + +properties: + compatible: + items: + - enum: + - aoly,sl101pm1794fog-v15 + - startek,kd070fhfid078 + - const: himax,hx8279 + + reg: + maxItems: 1 + + iovcc-supply: + description: I/O voltage supply + + vdd-supply: + description: Panel power supply + +required: + - compatible + - reg + - backlight + - reset-gpios + - iovcc-supply + - vdd-supply + +unevaluatedProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "startek,kd070fhfid078", "himax,hx8279"; + reg = <0>; + backlight = <&backlight>; + enable-gpios = <&pio 25 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 45 GPIO_ACTIVE_HIGH>; + iovcc-supply = <&vreg_lcm_vio>; + vdd-supply = <&vreg_lcm_vdd>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/panel/leadtek,ltk050h3146w.yaml b/Documentation/devicetree/bindings/display/panel/leadtek,ltk050h3146w.yaml index e2a2dd4ef5fa2..5fcea62fd58f7 100644 --- a/Documentation/devicetree/bindings/display/panel/leadtek,ltk050h3146w.yaml +++ b/Documentation/devicetree/bindings/display/panel/leadtek,ltk050h3146w.yaml @@ -23,6 +23,7 @@ properties: maxItems: 1 backlight: true + port: true reset-gpios: true iovcc-supply: description: regulator that supplies the iovcc voltage diff --git a/Documentation/devicetree/bindings/display/panel/leadtek,ltk500hd1829.yaml b/Documentation/devicetree/bindings/display/panel/leadtek,ltk500hd1829.yaml index af9e0ea0e72f9..b0e2c82232d33 100644 --- a/Documentation/devicetree/bindings/display/panel/leadtek,ltk500hd1829.yaml +++ b/Documentation/devicetree/bindings/display/panel/leadtek,ltk500hd1829.yaml @@ -22,6 +22,7 @@ properties: maxItems: 1 backlight: true + port: true reset-gpios: true iovcc-supply: description: regulator that supplies the iovcc voltage diff --git a/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml b/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml index bbaaa783d184e..2219d3d4ac43b 100644 --- a/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml +++ b/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: LG SW43408 1080x2160 DSI panel maintainers: - - Caleb Connolly + - Casey Connolly description: This panel is used on the Pixel 3, it is a 60hz OLED panel which diff --git a/Documentation/devicetree/bindings/display/panel/novatek,nt37801.yaml b/Documentation/devicetree/bindings/display/panel/novatek,nt37801.yaml new file mode 100644 index 0000000000000..1b38c1d0af682 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/novatek,nt37801.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/novatek,nt37801.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Novatek NT37801 AMOLED DSI Panel + +maintainers: + - Krzysztof Kozlowski + +description: + Naming is inconclusive and different sources claim this is either Novatek + NT37801 or NT37810 AMOLED DSI Panel. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: novatek,nt37801 + + reg: + maxItems: 1 + description: DSI virtual channel + + vci-supply: true + vdd-supply: true + vddio-supply: true + port: true + reset-gpios: true + +required: + - compatible + - reg + - vci-supply + - vdd-supply + - vddio-supply + - port + - reset-gpios + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "novatek,nt37801"; + reg = <0>; + + vci-supply = <&vreg_l13b_3p0>; + vdd-supply = <&vreg_l11b_1p2>; + vddio-supply = <&vreg_l12b_1p8>; + + reset-gpios = <&tlmm 98 GPIO_ACTIVE_LOW>; + + port { + endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index b0de4fd6f3d41..5542c9229d54a 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -226,6 +226,8 @@ properties: - netron-dy,e231732 # Newhaven Display International 480 x 272 TFT LCD panel - newhaven,nhd-4.3-480272ef-atxl + # NLT Technologies, Ltd. 15.6" WXGA (1366×768) LVDS TFT LCD panel + - nlt,nl13676bc25-03f # New Vision Display 7.0" 800 RGB x 480 TFT LCD panel - nvd,9128 # OKAYA Electric America, Inc. RS800480T-7X0GP 7" WVGA LCD panel @@ -246,6 +248,8 @@ properties: - osddisplays,osd070t1718-19ts # One Stop Displays OSD101T2045-53TS 10.1" 1920x1200 panel - osddisplays,osd101t2045-53ts + # POWERTIP PH128800T004-ZZA01 10.1" WXGA TFT LCD panel + - powertip,ph128800t004-zza01 # POWERTIP PH128800T006-ZHC01 10.1" WXGA TFT LCD panel - powertip,ph128800t006-zhc01 # POWERTIP PH800480T013-IDF2 7.0" WVGA TFT LCD panel @@ -284,6 +288,8 @@ properties: - startek,kd070wvfpa # Team Source Display Technology TST043015CMHX 4.3" WQVGA TFT LCD panel - team-source-display,tst043015cmhx + # Tianma Micro-electronics P0700WXF1MBAA 7.0" WXGA (1280x800) LVDS TFT LCD panel + - tianma,p0700wxf1mbaa # Tianma Micro-electronics TM070JDHG30 7.0" WXGA TFT LCD panel - tianma,tm070jdhg30 # Tianma Micro-electronics TM070JDHG34-00 7.0" WXGA (1280x800) LVDS TFT LCD panel diff --git a/Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml b/Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml index 684c2896d2387..31f0c0f038e49 100644 --- a/Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml +++ b/Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml @@ -19,6 +19,8 @@ properties: - const: samsung,atna33xc20 - items: - enum: + # Samsung 14" WQXGA+ (2880×1800 pixels) eDP AMOLED panel + - samsung,atna40yk20 # Samsung 14.5" WQXGA+ (2880x1800 pixels) eDP AMOLED panel - samsung,atna45af01 # Samsung 14.5" 3K (2944x1840 pixels) eDP AMOLED panel diff --git a/Documentation/devicetree/bindings/display/panel/truly,nt35597-2K-display.yaml b/Documentation/devicetree/bindings/display/panel/truly,nt35597-2K-display.yaml new file mode 100644 index 0000000000000..36be09c900f2f --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/truly,nt35597-2K-display.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/truly,nt35597-2K-display.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Truly NT35597 DSI 2K display + +maintainers: + - Neil Armstrong + +description: | + Truly NT35597 DSI 2K display is used on the Qualcomm SDM845 MTP board. + +allOf: + - $ref: panel-common-dual.yaml# + +properties: + compatible: + const: truly,nt35597-2K-display + + reg: + maxItems: 1 + + vdda-supply: + description: regulator that provides the supply voltage Power IC supply + + vdispp-supply: + description: regulator that provides the supply voltage for positive LCD bias + + vdispn-supply: + description: regulator that provides the supply voltage for negative LCD bias + + reset-gpios: true + + mode-gpios: + description: + Gpio for choosing the mode of the display for single DSI or Dual DSI. + This should be low for dual DSI and high for single DSI mode. + + ports: + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - vdda-supply + - reset-gpios + - mode-gpios + - ports + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "truly,nt35597-2K-display"; + reg = <0>; + + vdda-supply = <&pm8998_l14>; + vdispp-supply = <&lab_regulator>; + vdispn-supply = <&ibb_regulator>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + mode-gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + panel0_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + panel1_in: endpoint { + remote-endpoint = <&dsi1_out>; + }; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/panel/visionox,g2647fb105.yaml b/Documentation/devicetree/bindings/display/panel/visionox,g2647fb105.yaml new file mode 100644 index 0000000000000..49dcd9b8f6700 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/visionox,g2647fb105.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/visionox,g2647fb105.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Visionox G2647FB105 6.47" 1080x2340 MIPI-DSI Panel + +maintainers: + - Alexander Baransky + +description: + The Visionox G2647FB105 is a 6.47 inch 1080x2340 MIPI-DSI CMD mode OLED panel. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: visionox,g2647fb105 + + reg: + maxItems: 1 + + vdd3p3-supply: + description: 3.3V source voltage rail + + vddio-supply: + description: I/O source voltage rail + + vsn-supply: + description: Negative source voltage rail + + vsp-supply: + description: Positive source voltage rail + + reset-gpios: true + port: true + +required: + - compatible + - reg + - vdd3p3-supply + - vddio-supply + - vsn-supply + - vsp-supply + - reset-gpios + - port + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "visionox,g2647fb105"; + reg = <0>; + + vdd3p3-supply = <&vreg_l7c_3p0>; + vddio-supply = <&vreg_l13a_1p8>; + vsn-supply = <&vreg_ibb>; + vsp-supply = <&vreg_lab>; + + reset-gpios = <&pm6150l_gpios 9 GPIO_ACTIVE_LOW>; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt deleted file mode 100644 index 8df7d2e393d62..0000000000000 --- a/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt +++ /dev/null @@ -1,74 +0,0 @@ -Rockchip RK3399 specific extensions to the cdn Display Port -================================ - -Required properties: -- compatible: must be "rockchip,rk3399-cdn-dp" - -- reg: physical base address of the controller and length - -- clocks: from common clock binding: handle to dp clock. - -- clock-names: from common clock binding: - Required elements: "core-clk" "pclk" "spdif" "grf" - -- resets : a list of phandle + reset specifier pairs -- reset-names : string of reset names - Required elements: "apb", "core", "dptx", "spdif" -- power-domains : power-domain property defined with a phandle - to respective power domain. -- assigned-clocks: main clock, should be <&cru SCLK_DP_CORE> -- assigned-clock-rates : the DP core clk frequency, shall be: 100000000 - -- rockchip,grf: this soc should set GRF regs, so need get grf here. - -- ports: contain a port nodes with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. - contained 2 endpoints, connecting to the output of vop. - -- phys: from general PHY binding: the phandle for the PHY device. - -- extcon: extcon specifier for the Power Delivery - -- #sound-dai-cells = it must be 1 if your system is using 2 DAIs: I2S, SPDIF - -------------------------------------------------------------------------------- - -Example: - cdn_dp: dp@fec00000 { - compatible = "rockchip,rk3399-cdn-dp"; - reg = <0x0 0xfec00000 0x0 0x100000>; - interrupts = ; - clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, - <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; - clock-names = "core-clk", "pclk", "spdif", "grf"; - assigned-clocks = <&cru SCLK_DP_CORE>; - assigned-clock-rates = <100000000>; - power-domains = <&power RK3399_PD_HDCP>; - phys = <&tcphy0_dp>, <&tcphy1_dp>; - resets = <&cru SRST_DPTX_SPDIF_REC>; - reset-names = "spdif"; - extcon = <&fusb0>, <&fusb1>; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - #sound-dai-cells = <1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - dp_in: port { - #address-cells = <1>; - #size-cells = <0>; - dp_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_dp>; - }; - - dp_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_dp>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml index 60dedf9b2be73..d99b23b88cc59 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml @@ -15,6 +15,7 @@ properties: enum: - rockchip,rk3288-dp - rockchip,rk3399-edp + - rockchip,rk3588-edp clocks: minItems: 2 @@ -31,16 +32,23 @@ properties: maxItems: 1 resets: - maxItems: 1 + minItems: 1 + maxItems: 2 reset-names: - const: dp + minItems: 1 + items: + - const: dp + - const: apb rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle description: This SoC makes use of GRF regs. + aux-bus: + $ref: /schemas/display/dp-aux-bus.yaml# + required: - compatible - clocks @@ -52,6 +60,19 @@ required: allOf: - $ref: /schemas/display/bridge/analogix,dp.yaml# + - if: + properties: + compatible: + contains: + enum: + - rockchip,rk3588-edp + then: + properties: + resets: + minItems: 2 + reset-names: + minItems: 2 + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,inno-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,inno-hdmi.yaml index 5b87b0f1963e1..290376bec079a 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,inno-hdmi.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,inno-hdmi.yaml @@ -23,13 +23,11 @@ properties: maxItems: 1 clocks: - minItems: 1 items: - description: The HDMI controller main clock - description: The HDMI PHY reference clock clock-names: - minItems: 1 items: - const: pclk - const: ref @@ -58,6 +56,12 @@ properties: - port@0 - port@1 + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to GRF used for control the polarity of hsync/vsync of rk3036 + HDMI. + required: - compatible - reg @@ -77,6 +81,8 @@ allOf: const: rockchip,rk3036-inno-hdmi then: + required: + - rockchip,grf properties: power-domains: false @@ -87,11 +93,6 @@ allOf: const: rockchip,rk3128-inno-hdmi then: - properties: - clocks: - minItems: 2 - clock-names: - minItems: 2 required: - power-domains @@ -106,10 +107,11 @@ examples: compatible = "rockchip,rk3036-inno-hdmi"; reg = <0x20034000 0x4000>; interrupts = ; - clocks = <&cru PCLK_HDMI>; - clock-names = "pclk"; + clocks = <&cru PCLK_HDMI>, <&cru SCLK_LCDC>; + clock-names = "pclk", "ref"; pinctrl-names = "default"; pinctrl-0 = <&hdmi_ctl>; + rockchip,grf = <&grf>; #sound-dai-cells = <0>; ports { diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3399-cdn-dp.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3399-cdn-dp.yaml new file mode 100644 index 0000000000000..1a33128e77f58 --- /dev/null +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3399-cdn-dp.yaml @@ -0,0 +1,170 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/rockchip/rockchip,rk3399-cdn-dp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3399 specific extensions to the CDN Display Port + +maintainers: + - Andy Yan + - Heiko Stuebner + - Sandy Huang + +allOf: + - $ref: /schemas/sound/dai-common.yaml# + +properties: + compatible: + items: + - const: rockchip,rk3399-cdn-dp + + reg: + maxItems: 1 + + clocks: + items: + - description: DP core work clock + - description: APB clock + - description: SPDIF interface clock + - description: GRF clock + + clock-names: + items: + - const: core-clk + - const: pclk + - const: spdif + - const: grf + + extcon: + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + items: + - description: Extcon device providing the cable state for DP PHY device 0 + - description: Extcon device providing the cable state for DP PHY device 1 + description: + List of phandle to the extcon device providing the cable state for the DP PHY. + + interrupts: + maxItems: 1 + + phys: + minItems: 1 + items: + - description: DP output to the DP PHY device 0 + - description: DP output to the DP PHY device 1 + description: + RK3399 have two DP-USB PHY, specifying one PHY which want to use, or + specify two PHYs here to let the driver determine which PHY to use. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Input of the CDN DP + + properties: + endpoint@0: + description: Connection to the VOPB + + endpoint@1: + description: Connection to the VOPL + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Output of the CDN DP + + required: + - port@0 + - port@1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 4 + + reset-names: + items: + - const: spdif + - const: dptx + - const: apb + - const: core + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to GRF register to control HPD. + + "#sound-dai-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - phys + - ports + - resets + - reset-names + - rockchip,grf + - "#sound-dai-cells" + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + + dp@fec00000 { + compatible = "rockchip,rk3399-cdn-dp"; + reg = <0x0 0xfec00000 0x0 0x100000>; + assigned-clocks = <&cru SCLK_DP_CORE>; + assigned-clock-rates = <100000000>; + interrupts = ; + clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, <&cru SCLK_SPDIF_REC_DPTX>, + <&cru PCLK_VIO_GRF>; + clock-names = "core-clk", "pclk", "spdif", "grf"; + power-domains = <&power RK3399_PD_HDCP>; + phys = <&tcphy0_dp>, <&tcphy1_dp>; + resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, + <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; + reset-names = "spdif", "dptx", "apb", "core"; + rockchip,grf = <&grf>; + #sound-dai-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dp_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dp_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_dp>; + }; + + dp_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_dp>; + }; + }; + + dp_out: port@1 { + reg = <1>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml index b339b7e708c65..8b5f58103dda9 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml @@ -73,12 +73,6 @@ properties: port: $ref: /schemas/graph.yaml#/properties/port - assigned-clocks: - maxItems: 2 - - assigned-clock-rates: - maxItems: 2 - iommus: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/sitronix,st7571.yaml b/Documentation/devicetree/bindings/display/sitronix,st7571.yaml new file mode 100644 index 0000000000000..4fea782fccd70 --- /dev/null +++ b/Documentation/devicetree/bindings/display/sitronix,st7571.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/sitronix,st7571.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sitronix ST7571 Display Controller + +maintainers: + - Marcus Folkesson + +description: + Sitronix ST7571 is a driver and controller for 4-level gray + scale and monochrome dot matrix LCD panels. + +allOf: + - $ref: panel/panel-common.yaml# + +properties: + compatible: + const: sitronix,st7571 + + reg: + maxItems: 1 + + sitronix,grayscale: + type: boolean + description: + Display supports 4-level grayscale. + + reset-gpios: true + width-mm: true + height-mm: true + panel-timing: true + +required: + - compatible + - reg + - reset-gpios + - width-mm + - height-mm + - panel-timing + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + display@3f { + compatible = "sitronix,st7571"; + reg = <0x3f>; + reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + width-mm = <37>; + height-mm = <27>; + + panel-timing { + hactive = <128>; + vactive = <96>; + hback-porch = <0>; + vback-porch = <0>; + clock-frequency = <0>; + hfront-porch = <0>; + hsync-len = <0>; + vfront-porch = <0>; + vsync-len = <0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/truly,nt35597.txt b/Documentation/devicetree/bindings/display/truly,nt35597.txt deleted file mode 100644 index f39c77ee36ea5..0000000000000 --- a/Documentation/devicetree/bindings/display/truly,nt35597.txt +++ /dev/null @@ -1,59 +0,0 @@ -Truly model NT35597 DSI display driver - -The Truly NT35597 is a generic display driver, currently only configured -for use in the 2K display on the Qualcomm SDM845 MTP board. - -Required properties: -- compatible: should be "truly,nt35597-2K-display" -- vdda-supply: phandle of the regulator that provides the supply voltage - Power IC supply -- vdispp-supply: phandle of the regulator that provides the supply voltage - for positive LCD bias -- vdispn-supply: phandle of the regulator that provides the supply voltage - for negative LCD bias -- reset-gpios: phandle of gpio for reset line - This should be 8mA, gpio can be configured using mux, pinctrl, pinctrl-names - (active low) -- mode-gpios: phandle of the gpio for choosing the mode of the display - for single DSI or Dual DSI - This should be low for dual DSI and high for single DSI mode -- ports: This device has two video ports driven by two DSIs. Their connections - are modeled using the OF graph bindings specified in - Documentation/devicetree/bindings/graph.txt. - - port@0: DSI input port driven by master DSI - - port@1: DSI input port driven by secondary DSI - -Example: - - dsi@ae94000 { - panel@0 { - compatible = "truly,nt35597-2K-display"; - reg = <0>; - vdda-supply = <&pm8998_l14>; - vdispp-supply = <&lab_regulator>; - vdispn-supply = <&ibb_regulator>; - pinctrl-names = "default", "suspend"; - pinctrl-0 = <&dpu_dsi_active>; - pinctrl-1 = <&dpu_dsi_suspend>; - - reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; - mode-gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>; - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - panel0_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - - port@1 { - reg = <1>; - panel1_in: endpoint { - remote-endpoint = <&dsi1_out>; - }; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-apbdma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra20-apbdma.txt deleted file mode 100644 index 447fb44e7abea..0000000000000 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra20-apbdma.txt +++ /dev/null @@ -1,44 +0,0 @@ -* NVIDIA Tegra APB DMA controller - -Required properties: -- compatible: Should be "nvidia,-apbdma" -- reg: Should contain DMA registers location and length. This should include - all of the per-channel registers. -- interrupts: Should contain all of the per-channel DMA interrupts. -- clocks: Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the following entries: - - dma -- #dma-cells : Must be <1>. This dictates the length of DMA specifiers in - client nodes' dmas properties. The specifier represents the DMA request - select value for the peripheral. For more details, consult the Tegra TRM's - documentation of the APB DMA channel control register REQ_SEL field. - -Examples: - -apbdma: dma@6000a000 { - compatible = "nvidia,tegra20-apbdma"; - reg = <0x6000a000 0x1200>; - interrupts = < 0 136 0x04 - 0 137 0x04 - 0 138 0x04 - 0 139 0x04 - 0 140 0x04 - 0 141 0x04 - 0 142 0x04 - 0 143 0x04 - 0 144 0x04 - 0 145 0x04 - 0 146 0x04 - 0 147 0x04 - 0 148 0x04 - 0 149 0x04 - 0 150 0x04 - 0 151 0x04 >; - clocks = <&tegra_car 34>; - resets = <&tegra_car 34>; - reset-names = "dma"; - #dma-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-apbdma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra20-apbdma.yaml new file mode 100644 index 0000000000000..a2ffd5209b3bf --- /dev/null +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-apbdma.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/nvidia,tegra20-apbdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra APB DMA Controller + +description: + The NVIDIA Tegra APB DMA controller is a hardware component that + enables direct memory access (DMA) on Tegra systems. It facilitates + data transfer between I/O devices and main memory without constant + CPU intervention. + +maintainers: + - Jonathan Hunter + +properties: + compatible: + oneOf: + - const: nvidia,tegra20-apbdma + - items: + - const: nvidia,tegra30-apbdma + - const: nvidia,tegra20-apbdma + + reg: + maxItems: 1 + + "#dma-cells": + const: 1 + + clocks: + maxItems: 1 + + interrupts: + description: + Should contain all of the per-channel DMA interrupts in + ascending order with respect to the DMA channel index. + minItems: 1 + maxItems: 32 + + resets: + maxItems: 1 + + reset-names: + const: dma + +required: + - compatible + - reg + - "#dma-cells" + - clocks + - interrupts + - resets + - reset-names + +allOf: + - $ref: dma-controller.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + dma-controller@6000a000 { + compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; + reg = <0x6000a000 0x1200>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&tegra_car 34>; + resets = <&tegra_car 34>; + reset-names = "dma"; + #dma-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/example-schema.yaml b/Documentation/devicetree/bindings/example-schema.yaml index 484f8babcda4b..c731d5045e805 100644 --- a/Documentation/devicetree/bindings/example-schema.yaml +++ b/Documentation/devicetree/bindings/example-schema.yaml @@ -178,7 +178,9 @@ properties: description: Child nodes are just another property from a json-schema perspective. type: object # DT nodes are json objects - # Child nodes also need additionalProperties or unevaluatedProperties + # Child nodes also need additionalProperties or unevaluatedProperties, where + # 'false' should be used in most cases (see 'child-node-with-own-schema' + # below). additionalProperties: false properties: vendor,a-child-node-property: @@ -189,6 +191,17 @@ properties: required: - vendor,a-child-node-property + child-node-with-own-schema: + description: | + Child node with their own compatible and device schema which ends in + 'additionalProperties: false' or 'unevaluatedProperties: false' can + mention only the compatible and use here 'additionalProperties: true'. + type: object + additionalProperties: true + properties: + compatible: + const: vendor,sub-device + # Describe the relationship between different properties dependencies: # 'vendor,bool-property' is only allowed when 'vendor,string-array-property' diff --git a/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.yaml b/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.yaml index 2cdad1bbae73b..9785aac3b5f34 100644 --- a/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.yaml +++ b/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.yaml @@ -27,6 +27,15 @@ properties: mboxes: maxItems: 1 + pmic: + description: Child node describing the main PMIC. + type: object + additionalProperties: true + + properties: + compatible: + const: samsung,s2mpg10-pmic + shmem: description: List of phandle pointing to the shared memory (SHM) area. The memory @@ -43,8 +52,34 @@ additionalProperties: false examples: - | + #include + power-management { compatible = "google,gs101-acpm-ipc"; mboxes = <&ap2apm_mailbox>; shmem = <&apm_sram>; + + pmic { + compatible = "samsung,s2mpg10-pmic"; + interrupts-extended = <&gpa0 6 IRQ_TYPE_LEVEL_LOW>; + + regulators { + LDO1 { + regulator-name = "vdd_ldo1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + }; + + // ... + + BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; }; diff --git a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt deleted file mode 100644 index 6eff1afd8daf9..0000000000000 --- a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt +++ /dev/null @@ -1,57 +0,0 @@ -Intel Service Layer Driver for Stratix10 SoC -============================================ -Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard -processor system (HPS) and Secure Device Manager (SDM). When the FPGA is -configured from HPS, there needs to be a way for HPS to notify SDM the -location and size of the configuration data. Then SDM will get the -configuration data from that location and perform the FPGA configuration. - -To meet the whole system security needs and support virtual machine requesting -communication with SDM, only the secure world of software (EL3, Exception -Layer 3) can interface with SDM. All software entities running on other -exception layers must channel through the EL3 software whenever it needs -service from SDM. - -Intel Stratix10 service layer driver, running at privileged exception level -(EL1, Exception Layer 1), interfaces with the service providers and provides -the services for FPGA configuration, QSPI, Crypto and warm reset. Service layer -driver also manages secure monitor call (SMC) to communicate with secure monitor -code running in EL3. - -Required properties: -------------------- -The svc node has the following mandatory properties, must be located under -the firmware node. - -- compatible: "intel,stratix10-svc" or "intel,agilex-svc" -- method: smc or hvc - smc - Secure Monitor Call - hvc - Hypervisor Call -- memory-region: - phandle to the reserved memory node. See - Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt - for details - -Example: -------- - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - service_reserved: svcbuffer@0 { - compatible = "shared-dma-pool"; - reg = <0x0 0x0 0x0 0x1000000>; - alignment = <0x1000>; - no-map; - }; - }; - - firmware { - svc { - compatible = "intel,stratix10-svc"; - method = "smc"; - memory-region = <&service_reserved>; - }; - }; diff --git a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml new file mode 100644 index 0000000000000..fac1e955852e4 --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/intel,stratix10-svc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Service Layer Driver for Stratix10 SoC + +maintainers: + - Dinh Nguyen + - Mahesh Rao + +description: > + Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard + processor system (HPS) and Secure Device Manager (SDM). When the FPGA is + configured from HPS, there needs to be a way for HPS to notify SDM the + location and size of the configuration data. Then SDM will get the + configuration data from that location and perform the FPGA configuration. + + To meet the whole system security needs and support virtual machine requesting + communication with SDM, only the secure world of software (EL3, Exception + Layer 3) can interface with SDM. All software entities running on other + exception layers must channel through the EL3 software whenever it needs + service from SDM. + + Intel Stratix10 service layer driver, running at privileged exception level + (EL1, Exception Layer 1), interfaces with the service providers and provides + the services for FPGA configuration, QSPI, Crypto and warm reset. Service layer + driver also manages secure monitor call (SMC) to communicate with secure monitor + code running in EL3. + +properties: + compatible: + enum: + - intel,stratix10-svc + - intel,agilex-svc + + method: + description: | + Supervisory call method to be used to communicate with the + secure service layer. + Permitted values are: + - "smc" : SMC #0, following the SMCCC + - "hvc" : HVC #0, following the SMCCC + + $ref: /schemas/types.yaml#/definitions/string-array + enum: + - smc + - hvc + + memory-region: + maxItems: 1 + description: + reserved memory region for the service layer driver to + communicate with the secure device manager. + + fpga-mgr: + $ref: /schemas/fpga/intel,stratix10-soc-fpga-mgr.yaml + description: Optional child node for fpga manager to perform fabric configuration. + +required: + - compatible + - method + - memory-region + +additionalProperties: false + +examples: + - | + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + + service_reserved: svcbuffer@0 { + compatible = "shared-dma-pool"; + reg = <0x0 0x0 0x0 0x1000000>; + alignment = <0x1000>; + no-map; + }; + }; + + firmware { + svc { + compatible = "intel,stratix10-svc"; + method = "smc"; + memory-region = <&service_reserved>; + + fpga-mgr { + compatible = "intel,stratix10-soc-fpga-mgr"; + }; + }; + }; + diff --git a/Documentation/devicetree/bindings/firmware/nxp,imx95-scmi.yaml b/Documentation/devicetree/bindings/firmware/nxp,imx95-scmi.yaml index 1a95010a546b1..2bda2e0e13693 100644 --- a/Documentation/devicetree/bindings/firmware/nxp,imx95-scmi.yaml +++ b/Documentation/devicetree/bindings/firmware/nxp,imx95-scmi.yaml @@ -11,6 +11,18 @@ maintainers: - Peng Fan properties: + protocol@80: + description: + SCMI LMM protocol which is for boot, shutdown, and reset of other logical + machines (LM). It is usually used to allow one LM to manage another used + as an offload or accelerator engine. + $ref: '/schemas/firmware/arm,scmi.yaml#/$defs/protocol-node' + unevaluatedProperties: false + + properties: + reg: + const: 0x80 + protocol@81: $ref: '/schemas/firmware/arm,scmi.yaml#/$defs/protocol-node' unevaluatedProperties: false @@ -19,6 +31,17 @@ properties: reg: const: 0x81 + protocol@82: + description: + SCMI CPU Protocol which allows an agent to start or stop a CPU. It is + used to manage auxiliary CPUs in a LM. + $ref: '/schemas/firmware/arm,scmi.yaml#/$defs/protocol-node' + unevaluatedProperties: false + + properties: + reg: + const: 0x82 + protocol@84: $ref: '/schemas/firmware/arm,scmi.yaml#/$defs/protocol-node' unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml new file mode 100644 index 0000000000000..6e536d6b28a97 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/intel,stratix10-soc-fpga-mgr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Stratix10 SoC FPGA Manager + +maintainers: + - Mahesh Rao + - Adrian Ng Ho Yin + - Niravkumar L Rabara + +description: + The Intel Stratix10 SoC consists of a 64-bit quad-core ARM Cortex A53 hard + processor system (HPS) and a Secure Device Manager (SDM). The Stratix10 + SoC FPGA Manager driver is used to configure/reconfigure the FPGA fabric + on the die.The driver communicates with SDM/ATF via the stratix10-svc + platform driver for performing its operations. + +properties: + compatible: + enum: + - intel,stratix10-soc-fpga-mgr + - intel,agilex-soc-fpga-mgr + +required: + - compatible + +additionalProperties: false + +examples: + - | + fpga-mgr { + compatible = "intel,stratix10-soc-fpga-mgr"; + }; diff --git a/Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt deleted file mode 100644 index 0f874137ca469..0000000000000 --- a/Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt +++ /dev/null @@ -1,18 +0,0 @@ -Intel Stratix10 SoC FPGA Manager - -Required properties: -The fpga_mgr node has the following mandatory property, must be located under -firmware/svc node. - -- compatible : should contain "intel,stratix10-soc-fpga-mgr" or - "intel,agilex-soc-fpga-mgr" - -Example: - - firmware { - svc { - fpga_mgr: fpga-mgr { - compatible = "intel,stratix10-soc-fpga-mgr"; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/gpio/atmel,at91rm9200-gpio.yaml b/Documentation/devicetree/bindings/gpio/atmel,at91rm9200-gpio.yaml index 3dd70933ed8ed..d810043b56b65 100644 --- a/Documentation/devicetree/bindings/gpio/atmel,at91rm9200-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/atmel,at91rm9200-gpio.yaml @@ -69,13 +69,13 @@ examples: #include gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; }; ... diff --git a/Documentation/devicetree/bindings/gpio/blaize,blzp1600-gpio.yaml b/Documentation/devicetree/bindings/gpio/blaize,blzp1600-gpio.yaml new file mode 100644 index 0000000000000..a05f6ea619c3e --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/blaize,blzp1600-gpio.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/blaize,blzp1600-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Blaize BLZP1600 GPIO controller + +description: + Blaize BLZP1600 GPIO controller is an implementation of the VeriSilicon + APB GPIO v0.2 IP block. It has 32 ports each of which are intended to be + represented as child nodes with the generic GPIO-controller properties + as described in this binding's file. + +maintainers: + - Nikolaos Pasaloukos + - James Cowgill + - Matt Redfearn + - Neil Jones + +properties: + $nodename: + pattern: "^gpio@[0-9a-f]+$" + + compatible: + enum: + - blaize,blzp1600-gpio + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + ngpios: + default: 32 + minimum: 1 + maximum: 32 + + interrupts: + maxItems: 1 + + gpio-line-names: true + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + +dependencies: + interrupt-controller: [ interrupts ] + +additionalProperties: false + +examples: + - | + #include + + gpio: gpio@4c0000 { + compatible = "blaize,blzp1600-gpio"; + reg = <0x004c0000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; +... diff --git a/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml b/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml index 0e5c22929bdeb..ab35bcf981016 100644 --- a/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml +++ b/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml @@ -71,15 +71,15 @@ unevaluatedProperties: false examples: - | spi { - #address-cells = <1>; - #size-cells = <0>; - - gpio5: gpio5@0 { - compatible = "fairchild,74hc595"; - reg = <0>; - gpio-controller; - #gpio-cells = <2>; - registers-number = <4>; - spi-max-frequency = <100000>; - }; + #address-cells = <1>; + #size-cells = <0>; + + gpio5@0 { + compatible = "fairchild,74hc595"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + registers-number = <4>; + spi-max-frequency = <100000>; + }; }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-mxs.yaml b/Documentation/devicetree/bindings/gpio/gpio-mxs.yaml index 8ff54369d16c8..b58e08c8ecd8a 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-mxs.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-mxs.yaml @@ -84,52 +84,52 @@ examples: reg = <0x80018000 0x2000>; gpio@0 { - compatible = "fsl,imx28-gpio"; - reg = <0>; - interrupts = <127>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; + compatible = "fsl,imx28-gpio"; + reg = <0>; + interrupts = <127>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; }; gpio@1 { - compatible = "fsl,imx28-gpio"; - reg = <1>; - interrupts = <126>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; + compatible = "fsl,imx28-gpio"; + reg = <1>; + interrupts = <126>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; }; gpio@2 { - compatible = "fsl,imx28-gpio"; - reg = <2>; - interrupts = <125>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; + compatible = "fsl,imx28-gpio"; + reg = <2>; + interrupts = <125>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; }; gpio@3 { - compatible = "fsl,imx28-gpio"; - reg = <3>; - interrupts = <124>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; + compatible = "fsl,imx28-gpio"; + reg = <3>; + interrupts = <124>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; }; gpio@4 { - compatible = "fsl,imx28-gpio"; - reg = <4>; - interrupts = <123>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; + compatible = "fsl,imx28-gpio"; + reg = <4>; + interrupts = <123>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; }; }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml b/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml index 7b1eb08fa055c..4d3f52f8d1b82 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml @@ -16,6 +16,9 @@ description: |+ properties: compatible: oneOf: + - items: + - const: toradex,ecgpiol16 + - const: nxp,pcal6416 - items: - const: diodes,pi4ioe5v6534q - const: nxp,pcal6534 @@ -132,6 +135,7 @@ allOf: - maxim,max7325 - maxim,max7326 - maxim,max7327 + - toradex,ecgpiol16 then: properties: reset-gpios: false diff --git a/Documentation/devicetree/bindings/gpio/gpio-vf610.yaml b/Documentation/devicetree/bindings/gpio/gpio-vf610.yaml index 4fb32e9aec0a3..a31f64b6d40b4 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-vf610.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-vf610.yaml @@ -70,6 +70,13 @@ properties: minItems: 1 maxItems: 4 + gpio-reserved-ranges: true + + ngpios: + minimum: 1 + maximum: 32 + default: 32 + patternProperties: "^.+-hog(-[0-9]+)?$": type: object diff --git a/Documentation/devicetree/bindings/gpio/maxim,max77759-gpio.yaml b/Documentation/devicetree/bindings/gpio/maxim,max77759-gpio.yaml new file mode 100644 index 0000000000000..55734190d5ebd --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/maxim,max77759-gpio.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/maxim,max77759-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim Integrated MAX77759 GPIO + +maintainers: + - André Draszik + +description: | + This module is part of the MAX77759 PMIC. For additional information, see + Documentation/devicetree/bindings/mfd/maxim,max77759.yaml. + + The MAX77759 is a PMIC integrating, amongst others, a GPIO controller + including interrupt support for 2 GPIO lines. + +properties: + compatible: + const: maxim,max77759-gpio + + "#gpio-cells": + const: 2 + + gpio-controller: true + + gpio-line-names: + minItems: 1 + maxItems: 2 + + "#interrupt-cells": + const: 2 + + interrupt-controller: true + +required: + - compatible + - "#gpio-cells" + - gpio-controller + - "#interrupt-cells" + - interrupt-controller + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml b/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml index 4ef06b2ff1ff0..065f5761a93f6 100644 --- a/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml @@ -111,6 +111,9 @@ properties: gpio-controller: true + gpio-ranges: + maxItems: 1 + "#gpio-cells": description: | Indicates how many cells are used in a consumer's GPIO specifier. In the diff --git a/Documentation/devicetree/bindings/gpio/nxp,pcf8575.yaml b/Documentation/devicetree/bindings/gpio/nxp,pcf8575.yaml index 8bca574bb66d4..5a6ecaa7b44bc 100644 --- a/Documentation/devicetree/bindings/gpio/nxp,pcf8575.yaml +++ b/Documentation/devicetree/bindings/gpio/nxp,pcf8575.yaml @@ -128,17 +128,17 @@ additionalProperties: false examples: - | i2c { - #address-cells = <1>; - #size-cells = <0>; - - pcf8575: gpio@20 { - compatible = "nxp,pcf8575"; - reg = <0x20>; - interrupt-parent = <&irqpin2>; - interrupts = <3 0>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; + #address-cells = <1>; + #size-cells = <0>; + + gpio@20 { + compatible = "nxp,pcf8575"; + reg = <0x20>; + interrupt-parent = <&irqpin2>; + interrupts = <3 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; diff --git a/Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml b/Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml index 39fd959c45d20..728099c658246 100644 --- a/Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml @@ -81,7 +81,7 @@ dependencies: examples: - | - gpio@3500 { + gpio@3500 { compatible = "realtek,rtl8380-gpio", "realtek,otto-gpio"; reg = <0x3500 0x1c>; gpio-controller; @@ -91,9 +91,9 @@ examples: #interrupt-cells = <2>; interrupt-parent = <&rtlintc>; interrupts = <23>; - }; + }; - | - gpio@3300 { + gpio@3300 { compatible = "realtek,rtl9300-gpio", "realtek,otto-gpio"; reg = <0x3300 0x1c>, <0x3338 0x8>; gpio-controller; @@ -103,6 +103,6 @@ examples: #interrupt-cells = <2>; interrupt-parent = <&rtlintc>; interrupts = <13>; - }; + }; ... diff --git a/Documentation/devicetree/bindings/gpio/renesas,em-gio.yaml b/Documentation/devicetree/bindings/gpio/renesas,em-gio.yaml index 8bdef812c87c3..49fb8f613ead4 100644 --- a/Documentation/devicetree/bindings/gpio/renesas,em-gio.yaml +++ b/Documentation/devicetree/bindings/gpio/renesas,em-gio.yaml @@ -57,14 +57,14 @@ examples: - | #include gpio0: gpio@e0050000 { - compatible = "renesas,em-gio"; - reg = <0xe0050000 0x2c>, <0xe0050040 0x20>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pfc 0 0 32>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; + compatible = "renesas,em-gio"; + reg = <0xe0050000 0x2c>, <0xe0050040 0x20>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 0 32>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; }; diff --git a/Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml b/Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml index cc7a950a60309..d32e103a64aac 100644 --- a/Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml @@ -138,16 +138,16 @@ examples: #include #include gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a77470", "renesas,rcar-gen2-gpio"; - reg = <0xe6053000 0x50>; - interrupts = ; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 909>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pfc 0 96 30>; - gpio-reserved-ranges = <17 10>; - interrupt-controller; - #interrupt-cells = <2>; + compatible = "renesas,gpio-r8a77470", "renesas,rcar-gen2-gpio"; + reg = <0xe6053000 0x50>; + interrupts = ; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 909>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 96 30>; + gpio-reserved-ranges = <17 10>; + interrupt-controller; + #interrupt-cells = <2>; }; diff --git a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml index fc095646adeae..4bdc201b719ef 100644 --- a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml @@ -76,8 +76,8 @@ additionalProperties: false examples: - | - #include - gpio@10060000 { + #include + gpio@10060000 { compatible = "sifive,fu540-c000-gpio", "sifive,gpio0"; interrupt-parent = <&plic>; interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>, @@ -88,6 +88,6 @@ examples: #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - }; + }; ... diff --git a/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml b/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml new file mode 100644 index 0000000000000..ec0232e72c712 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/spacemit,k1-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K1 GPIO controller + +maintainers: + - Yixun Lan + +description: + The controller's registers are organized as sets of eight 32-bit + registers with each set of port controlling 32 pins. A single + interrupt line is shared for all of the pins by the controller. + +properties: + $nodename: + pattern: "^gpio@[0-9a-f]+$" + + compatible: + const: spacemit,k1-gpio + + reg: + maxItems: 1 + + clocks: + items: + - description: GPIO Core Clock + - description: GPIO Bus Clock + + clock-names: + items: + - const: core + - const: bus + + resets: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 3 + description: + The first two cells are the GPIO bank index and offset inside the bank, + the third cell should specify GPIO flag. + + gpio-ranges: true + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 3 + description: + The first two cells are the GPIO bank index and offset inside the bank, + the third cell should specify interrupt flag. The controller does not + support level interrupts, so flags of IRQ_TYPE_LEVEL_HIGH, + IRQ_TYPE_LEVEL_LOW should not be used. + Refer for valid flags. + +required: + - compatible + - reg + - clocks + - clock-names + - gpio-controller + - "#gpio-cells" + - interrupts + - interrupt-controller + - "#interrupt-cells" + - gpio-ranges + +additionalProperties: false + +examples: + - | + gpio@d4019000 { + compatible = "spacemit,k1-gpio"; + reg = <0xd4019000 0x800>; + clocks =<&ccu 9>, <&ccu 61>; + clock-names = "core", "bus"; + gpio-controller; + #gpio-cells = <3>; + interrupts = <58>; + interrupt-controller; + interrupt-parent = <&plic>; + #interrupt-cells = <3>; + gpio-ranges = <&pinctrl 0 0 0 32>, + <&pinctrl 1 0 32 32>, + <&pinctrl 2 0 64 32>, + <&pinctrl 3 0 96 32>; + }; +... diff --git a/Documentation/devicetree/bindings/gpio/toshiba,gpio-visconti.yaml b/Documentation/devicetree/bindings/gpio/toshiba,gpio-visconti.yaml index b085450b527f8..712063417bc89 100644 --- a/Documentation/devicetree/bindings/gpio/toshiba,gpio-visconti.yaml +++ b/Documentation/devicetree/bindings/gpio/toshiba,gpio-visconti.yaml @@ -48,22 +48,22 @@ additionalProperties: false examples: - | - #include - #include + #include + #include - soc { + soc { #address-cells = <2>; #size-cells = <2>; gpio: gpio@28020000 { - compatible = "toshiba,gpio-tmpv7708"; - reg = <0 0x28020000 0 0x1000>; - #gpio-cells = <0x2>; - gpio-ranges = <&pmux 0 0 32>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&gic>; + compatible = "toshiba,gpio-tmpv7708"; + reg = <0 0x28020000 0 0x1000>; + #gpio-cells = <0x2>; + gpio-ranges = <&pmux 0 0 32>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; }; - }; + }; ... diff --git a/Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml b/Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml index d3d8a2e143ed2..8fbf12ca067ee 100644 --- a/Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml +++ b/Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml @@ -126,29 +126,29 @@ examples: - | #include - gpio@a0020000 { - compatible = "xlnx,xps-gpio-1.00.a"; - reg = <0xa0020000 0x10000>; - #gpio-cells = <2>; - #interrupt-cells = <0x2>; - clocks = <&zynqmp_clk 71>; - gpio-controller; - interrupt-controller; - interrupt-names = "ip2intc_irpt"; - interrupt-parent = <&gic>; - interrupts = <0 89 4>; - xlnx,all-inputs = <0x0>; - xlnx,all-inputs-2 = <0x0>; - xlnx,all-outputs = <0x0>; - xlnx,all-outputs-2 = <0x0>; - xlnx,dout-default = <0x0>; - xlnx,dout-default-2 = <0x0>; - xlnx,gpio-width = <0x20>; - xlnx,gpio2-width = <0x20>; - xlnx,interrupt-present = <0x1>; - xlnx,is-dual = <0x1>; - xlnx,tri-default = <0xFFFFFFFF>; - xlnx,tri-default-2 = <0xFFFFFFFF>; - }; + gpio@a0020000 { + compatible = "xlnx,xps-gpio-1.00.a"; + reg = <0xa0020000 0x10000>; + #gpio-cells = <2>; + #interrupt-cells = <0x2>; + clocks = <&zynqmp_clk 71>; + gpio-controller; + interrupt-controller; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&gic>; + interrupts = <0 89 4>; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x0>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x0>; + xlnx,dout-default-2 = <0x0>; + xlnx,gpio-width = <0x20>; + xlnx,gpio2-width = <0x20>; + xlnx,interrupt-present = <0x1>; + xlnx,is-dual = <0x1>; + xlnx,tri-default = <0xFFFFFFFF>; + xlnx,tri-default-2 = <0xFFFFFFFF>; + }; ... diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index 019bd28a29f19..b8d659d272d06 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -25,6 +25,8 @@ properties: - realtek,rtd1619-mali - renesas,r9a07g044-mali - renesas,r9a07g054-mali + - renesas,r9a09g047-mali + - renesas,r9a09g056-mali - renesas,r9a09g057-mali - rockchip,px30-mali - rockchip,rk3562-mali @@ -145,6 +147,8 @@ allOf: enum: - renesas,r9a07g044-mali - renesas,r9a07g054-mali + - renesas,r9a09g047-mali + - renesas,r9a09g056-mali - renesas,r9a09g057-mali then: properties: diff --git a/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml b/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml index dc078ceeca9ac..43c6d2d724565 100644 --- a/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml +++ b/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Broadcom V3D GPU maintainers: - - Eric Anholt + - Maíra Canal - Nicolas Saenz Julienne properties: @@ -22,20 +22,12 @@ properties: - brcm,7278-v3d reg: - items: - - description: hub register (required) - - description: core0 register (required) - - description: GCA cache controller register (if GCA controller present) - - description: bridge register (if no external reset controller) minItems: 2 + maxItems: 4 reg-names: - items: - - const: hub - - const: core0 - - enum: [ bridge, gca ] - - enum: [ bridge, gca ] minItems: 2 + maxItems: 4 interrupts: items: @@ -58,6 +50,76 @@ required: - reg-names - interrupts +allOf: + - if: + properties: + compatible: + contains: + const: brcm,2711-v3d + then: + properties: + reg: + items: + - description: hub register + - description: core0 register + reg-names: + items: + - const: hub + - const: core0 + - if: + properties: + compatible: + contains: + const: brcm,2712-v3d + then: + properties: + reg: + items: + - description: hub register + - description: core0 register + - description: SMS state manager register + reg-names: + items: + - const: hub + - const: core0 + - const: sms + - if: + properties: + compatible: + contains: + const: brcm,7268-v3d + then: + properties: + reg: + items: + - description: hub register + - description: core0 register + - description: GCA cache controller register + - description: bridge register + reg-names: + items: + - const: hub + - const: core0 + - const: gca + - const: bridge + - if: + properties: + compatible: + contains: + const: brcm,7278-v3d + then: + properties: + reg: + items: + - description: hub register + - description: core0 register + - description: bridge register + reg-names: + items: + - const: hub + - const: core0 + - const: bridge + additionalProperties: false examples: @@ -66,9 +128,9 @@ examples: compatible = "brcm,7268-v3d"; reg = <0xf1200000 0x4000>, <0xf1208000 0x4000>, - <0xf1204000 0x100>, - <0xf1204100 0x100>; - reg-names = "hub", "core0", "bridge", "gca"; + <0xf1204100 0x100>, + <0xf1204000 0x100>; + reg-names = "hub", "core0", "gca", "bridge"; interrupts = <0 78 4>, <0 77 4>; }; diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml index 256e252f8087f..4450e2e73b3cc 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml @@ -12,10 +12,28 @@ maintainers: properties: compatible: - items: - - enum: - - ti,am62-gpu - - const: img,img-axe # IMG AXE GPU model/revision is fully discoverable + oneOf: + - items: + - enum: + - ti,am62-gpu + - const: img,img-axe-1-16m + # This deprecated element must be kept around to allow old kernels to + # work with newer dts. + - const: img,img-axe + - const: img,img-rogue + - items: + - enum: + - ti,j721s2-gpu + - const: img,img-bxs-4-64 + - const: img,img-rogue + + # This legacy combination of compatible strings was introduced early on + # before the more specific GPU identifiers were used. + - items: + - enum: + - ti,am62-gpu + - const: img,img-axe + deprecated: true reg: maxItems: 1 @@ -35,6 +53,18 @@ properties: maxItems: 1 power-domains: + minItems: 1 + maxItems: 2 + + power-domain-names: + items: + - const: a + - const: b + minItems: 1 + + dma-coherent: true + + resets: maxItems: 1 required: @@ -47,11 +77,49 @@ required: additionalProperties: false allOf: + # Constraints added alongside the new compatible strings that would otherwise + # create an ABI break. + - if: + properties: + compatible: + contains: + const: img,img-rogue + then: + required: + - power-domains + - power-domain-names + + - if: + properties: + compatible: + contains: + const: img,img-axe-1-16m + then: + properties: + power-domains: + maxItems: 1 + power-domain-names: + maxItems: 1 + + - if: + properties: + compatible: + contains: + const: img,img-bxs-4-64 + then: + properties: + power-domains: + minItems: 2 + power-domain-names: + minItems: 2 + - if: properties: compatible: contains: - const: ti,am62-gpu + enum: + - ti,am62-gpu + - ti,j721s2-gpu then: properties: clocks: @@ -64,10 +132,12 @@ examples: #include gpu@fd00000 { - compatible = "ti,am62-gpu", "img,img-axe"; + compatible = "ti,am62-gpu", "img,img-axe-1-16m", "img,img-axe", + "img,img-rogue"; reg = <0x0fd00000 0x20000>; clocks = <&k3_clks 187 0>; clock-names = "core"; interrupts = ; power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>; + power-domain-names = "a"; }; diff --git a/Documentation/devicetree/bindings/hwinfo/via,vt8500-scc-id.yaml b/Documentation/devicetree/bindings/hwinfo/via,vt8500-scc-id.yaml new file mode 100644 index 0000000000000..b0f425a4a882b --- /dev/null +++ b/Documentation/devicetree/bindings/hwinfo/via,vt8500-scc-id.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwinfo/via,vt8500-scc-id.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: VIA/WonderMedia SoC system configuration information + +maintainers: + - Alexey Charkov + +description: + The system configuration controller on VIA/WonderMedia SoC's contains a chip + identifier and revision used to differentiate between different hardware + versions of on-chip IP blocks having their own peculiarities which may or + may not be captured by their respective DT compatible strings + +properties: + compatible: + items: + - const: via,vt8500-scc-id + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + chipid@d8120000 { + compatible = "via,vt8500-scc-id"; + reg = <0xd8120000 0x4>; + }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml index fda0467cdd954..23fe8ff76645e 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml @@ -52,6 +52,7 @@ properties: - const: mediatek,mt8173-i2c - items: - enum: + - mediatek,mt6893-i2c - mediatek,mt8195-i2c - const: mediatek,mt8192-i2c diff --git a/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml b/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml index 8101afa6f1469..2f1e97969c3f7 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml @@ -37,6 +37,7 @@ properties: - rockchip,px30-i2c - rockchip,rk3308-i2c - rockchip,rk3328-i2c + - rockchip,rk3528-i2c - rockchip,rk3562-i2c - rockchip,rk3568-i2c - rockchip,rk3576-i2c diff --git a/Documentation/devicetree/bindings/i2c/i2c-wmt.txt b/Documentation/devicetree/bindings/i2c/i2c-wmt.txt deleted file mode 100644 index 94a425eaa6c78..0000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-wmt.txt +++ /dev/null @@ -1,24 +0,0 @@ -* Wondermedia I2C Controller - -Required properties : - - - compatible : should be "wm,wm8505-i2c" - - reg : Offset and length of the register set for the device - - interrupts : where IRQ is the interrupt number - - clocks : phandle to the I2C clock source - -Optional properties : - - - clock-frequency : desired I2C bus clock frequency in Hz. - Valid values are 100000 and 400000. - Default to 100000 if not specified, or invalid value. - -Example : - - i2c_0: i2c@d8280000 { - compatible = "wm,wm8505-i2c"; - reg = <0xd8280000 0x1000>; - interrupts = <19>; - clocks = <&clki2c0>; - clock-frequency = <400000>; - }; diff --git a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml index 1b7fed2326423..cc39511a49d63 100644 --- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml +++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml @@ -29,6 +29,7 @@ properties: - enum: - renesas,riic-r9a08g045 # RZ/G3S - renesas,riic-r9a09g047 # RZ/G3E + - renesas,riic-r9a09g056 # RZ/V2N - const: renesas,riic-r9a09g057 # RZ/V2H(P) - const: renesas,riic-r9a09g057 # RZ/V2H(P) diff --git a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml index bc5d0fb5abfec..d904191bb0c6e 100644 --- a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml @@ -32,15 +32,13 @@ properties: - const: renesas,r9a06g032-i2c # RZ/N1D - const: renesas,rzn1-i2c # RZ/N1 - const: snps,designware-i2c - - description: Microsemi Ocelot SoCs I2C controller - items: - - const: mscc,ocelot-i2c - - const: snps,designware-i2c - description: Baikal-T1 SoC System I2C controller const: baikal,bt1-sys-i2c - - description: T-HEAD TH1520 SoCs I2C controller - items: - - const: thead,th1520-i2c + - items: + - enum: + - mscc,ocelot-i2c + - sophgo,sg2044-i2c + - thead,th1520-i2c - const: snps,designware-i2c reg: diff --git a/Documentation/devicetree/bindings/i2c/wm,wm8505-i2c.yaml b/Documentation/devicetree/bindings/i2c/wm,wm8505-i2c.yaml new file mode 100644 index 0000000000000..e498ce47b8852 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/wm,wm8505-i2c.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/wm,wm8505-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: I2C Controller on WonderMedia WM8505 and related SoCs + +maintainers: + - Alexey Charkov + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + const: wm,wm8505-i2c + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-frequency: + enum: [100000, 400000] + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + i2c_0: i2c@d8280000 { + compatible = "wm,wm8505-i2c"; + reg = <0xd8280000 0x1000>; + interrupts = <19>; + clocks = <&clki2c0>; + clock-frequency = <400000>; + }; diff --git a/Documentation/devicetree/bindings/i3c/silvaco,i3c-master.yaml b/Documentation/devicetree/bindings/i3c/silvaco,i3c-master.yaml index 4fbdcdac0aee5..853092f7522d3 100644 --- a/Documentation/devicetree/bindings/i3c/silvaco,i3c-master.yaml +++ b/Documentation/devicetree/bindings/i3c/silvaco,i3c-master.yaml @@ -9,14 +9,17 @@ title: Silvaco I3C master maintainers: - Conor Culhane -allOf: - - $ref: i3c.yaml# - properties: compatible: - enum: - - nuvoton,npcm845-i3c - - silvaco,i3c-master-v1 + oneOf: + - enum: + - nuvoton,npcm845-i3c + - silvaco,i3c-master-v1 + - items: + - enum: + - nxp,imx94-i3c + - nxp,imx95-i3c + - const: silvaco,i3c-master-v1 reg: maxItems: 1 @@ -25,12 +28,14 @@ properties: maxItems: 1 clocks: + minItems: 2 items: - description: system clock - description: bus clock - description: other (slower) events clock clock-names: + minItems: 2 items: - const: pclk - const: fast_clk @@ -46,6 +51,34 @@ required: - clock-names - clocks +allOf: + - $ref: i3c.yaml# + - if: + properties: + compatible: + enum: + - nuvoton,npcm845-i3c + - silvaco,i3c-master-v1 + then: + properties: + clocks: + minItems: 3 + clock-names: + minItems: 3 + - if: + properties: + compatible: + contains: + enum: + - nxp,imx94-i3c + - nxp,imx95-i3c + then: + properties: + clocks: + maxItems: 2 + clock-names: + maxItems: 2 + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml index f39bc92c2b99b..862e450da214d 100644 --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm's SPMI PMIC Round Robin ADC maintainers: - - Caleb Connolly + - Casey Connolly description: | The Qualcomm SPMI Round Robin ADC (RRADC) provides interface to clients to diff --git a/Documentation/devicetree/bindings/interrupt-controller/abilis,tb10x-ictl.txt b/Documentation/devicetree/bindings/interrupt-controller/abilis,tb10x-ictl.txt deleted file mode 100644 index 5a4dd263fc127..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/abilis,tb10x-ictl.txt +++ /dev/null @@ -1,37 +0,0 @@ -TB10x Top Level Interrupt Controller -==================================== - -The Abilis TB10x SOC contains a custom interrupt controller. It performs -one-to-one mapping of external interrupt sources to CPU interrupts and -provides support for reconfigurable trigger modes. - -Required properties -------------------- - -- compatible: Should be "abilis,tb10x-ictl" -- reg: specifies physical base address and size of register range. -- interrupt-congroller: Identifies the node as an interrupt controller. -- #interrupt cells: Specifies the number of cells used to encode an interrupt - source connected to this controller. The value shall be 2. -- interrupts: Specifies the list of interrupt lines which are handled by - the interrupt controller in the parent controller's notation. Interrupts - are mapped one-to-one to parent interrupts. - -Example -------- - -intc: interrupt-controller { /* Parent interrupt controller */ - interrupt-controller; - #interrupt-cells = <1>; /* For example below */ - /* ... */ -}; - -tb10x_ictl: pic@2000 { /* TB10x interrupt controller */ - compatible = "abilis,tb10x-ictl"; - reg = <0x2000 0x20>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 30 31>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/abilis,tb10x-ictl.yaml b/Documentation/devicetree/bindings/interrupt-controller/abilis,tb10x-ictl.yaml new file mode 100644 index 0000000000000..cd2c49670e7b4 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/abilis,tb10x-ictl.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/abilis,tb10x-ictl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TB10x Top Level Interrupt Controller + +maintainers: + - Christian Ruppert + +description: + The Abilis TB10x SOC contains a custom interrupt controller. It performs + one-to-one mapping of external interrupt sources to CPU interrupts and + provides support for reconfigurable trigger modes. + +properties: + compatible: + const: abilis,tb10x-ictl + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + description: A one-to-one mapping of external interrupt sources to parent + interrupts. + minItems: 1 + maxItems: 32 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - interrupts + +additionalProperties: false + +examples: + - | + interrupt-controller@2000 { + compatible = "abilis,tb10x-ictl"; + reg = <0x2000 0x20>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <5>, <6>, <7>, <8>, <9>, <10>, <11>, <12>, <13>, <14>, + <15>, <16>, <17>, <18>, <19>, <20>, <21>, <22>, <23>, + <24>, <25>, <26>, <27>, <28>, <29>, <30>, <31>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt b/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt deleted file mode 100644 index 5669764f9cc96..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt +++ /dev/null @@ -1,25 +0,0 @@ -Alpine MSIX controller - -See arm,gic-v3.txt for SPI and MSI definitions. - -Required properties: - -- compatible: should be "al,alpine-msix" -- reg: physical base address and size of the registers -- interrupt-controller: identifies the node as an interrupt controller -- msi-controller: identifies the node as an PCI Message Signaled Interrupt - controller -- al,msi-base-spi: SPI base of the MSI frame -- al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0 - -Example: - -msix: msix { - compatible = "al,alpine-msix"; - reg = <0x0 0xfbe00000 0x0 0x100000>; - interrupt-parent = <&gic>; - interrupt-controller; - msi-controller; - al,msi-base-spi = <160>; - al,msi-num-spis = <160>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.yaml b/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.yaml new file mode 100644 index 0000000000000..9f1ff8ec686fa --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/al,alpine-msix.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Alpine MSIX controller + +maintainers: + - Antoine Tenart + +properties: + compatible: + const: al,alpine-msix + + reg: + maxItems: 1 + + interrupt-parent: true + + msi-controller: true + + al,msi-base-spi: + description: SPI base of the MSI frame + $ref: /schemas/types.yaml#/definitions/uint32 + + al,msi-num-spis: + description: number of SPIs assigned to the MSI frame, relative to SPI0 + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - msi-controller + - al,msi-base-spi + - al,msi-num-spis + +additionalProperties: false + +examples: + - | + msi-controller@fbe00000 { + compatible = "al,alpine-msix"; + reg = <0xfbe00000 0x100000>; + interrupt-parent = <&gic>; + msi-controller; + al,msi-base-spi = <160>; + al,msi-num-spis = <160>; + }; diff --git a/Documentation/devicetree/bindings/pci/altr,msi-controller.yaml b/Documentation/devicetree/bindings/interrupt-controller/altr,msi-controller.yaml similarity index 94% rename from Documentation/devicetree/bindings/pci/altr,msi-controller.yaml rename to Documentation/devicetree/bindings/interrupt-controller/altr,msi-controller.yaml index 98814862d0064..d046954b8a273 100644 --- a/Documentation/devicetree/bindings/pci/altr,msi-controller.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/altr,msi-controller.yaml @@ -2,7 +2,7 @@ # Copyright (C) 2015, 2024, Intel Corporation %YAML 1.2 --- -$id: http://devicetree.org/schemas/altr,msi-controller.yaml# +$id: http://devicetree.org/schemas/interrupt-controller/altr,msi-controller.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Altera PCIe MSI controller diff --git a/Documentation/devicetree/bindings/interrupt-controller/amazon,al-fic.txt b/Documentation/devicetree/bindings/interrupt-controller/amazon,al-fic.txt deleted file mode 100644 index c676b03c752ed..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/amazon,al-fic.txt +++ /dev/null @@ -1,27 +0,0 @@ -Amazon's Annapurna Labs Fabric Interrupt Controller - -Required properties: - -- compatible: should be "amazon,al-fic" -- reg: physical base address and size of the registers -- interrupt-controller: identifies the node as an interrupt controller -- #interrupt-cells : must be 2. Specifies the number of cells needed to encode - an interrupt source. Supported trigger types are low-to-high edge - triggered and active high level-sensitive. -- interrupts: describes which input line in the interrupt parent, this - fic's output is connected to. This field property depends on the parent's - binding - -Please refer to interrupts.txt in this directory for details of the common -Interrupt Controllers bindings used by client devices. - -Example: - -amazon_fic: interrupt-controller@fd8a8500 { - compatible = "amazon,al-fic"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0xfd8a8500 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/amazon,al-fic.yaml b/Documentation/devicetree/bindings/interrupt-controller/amazon,al-fic.yaml new file mode 100644 index 0000000000000..26bc05dee0bce --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/amazon,al-fic.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/amazon,al-fic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amazon Annapurna Labs Fabric Interrupt Controller + +maintainers: + - Talel Shenhar + +properties: + compatible: + const: amazon,al-fic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - interrupts + +additionalProperties: false + +examples: + - | + #include + + interrupt-controller@fd8a8500 { + compatible = "amazon,al-fic"; + reg = <0xfd8a8500 0x1000>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,nvic.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,nvic.txt deleted file mode 100644 index 386ab37a383fa..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,nvic.txt +++ /dev/null @@ -1,36 +0,0 @@ -* ARM Nested Vector Interrupt Controller (NVIC) - -The NVIC provides an interrupt controller that is tightly coupled to -Cortex-M based processor cores. The NVIC implemented on different SoCs -vary in the number of interrupts and priority bits per interrupt. - -Main node required properties: - -- compatible : should be one of: - "arm,v6m-nvic" - "arm,v7m-nvic" - "arm,v8m-nvic" -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The type shall be a and the value shall be 2. - - The 1st cell contains the interrupt number for the interrupt type. - - The 2nd cell is the priority of the interrupt. - -- reg : Specifies base physical address(s) and size of the NVIC registers. - This is at a fixed address (0xe000e100) and size (0xc00). - -- arm,num-irq-priority-bits: The number of priority bits implemented by the - given SoC - -Example: - - intc: interrupt-controller@e000e100 { - compatible = "arm,v7m-nvic"; - #interrupt-cells = <2>; - #address-cells = <1>; - interrupt-controller; - reg = <0xe000e100 0xc00>; - arm,num-irq-priority-bits = <4>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,nvic.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,nvic.yaml new file mode 100644 index 0000000000000..d89eca956c5fa --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,nvic.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/arm,nvic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Nested Vector Interrupt Controller (NVIC) + +maintainers: + - Rob Herring + +description: + The NVIC provides an interrupt controller that is tightly coupled to Cortex-M + based processor cores. The NVIC implemented on different SoCs vary in the + number of interrupts and priority bits per interrupt. + +properties: + compatible: + enum: + - arm,v6m-nvic + - arm,v7m-nvic + - arm,v8m-nvic + + reg: + maxItems: 1 + + '#address-cells': + const: 0 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + description: | + Number of cells to encode an interrupt source: + first = interrupt number, second = priority. + + arm,num-irq-priority-bits: + description: Number of priority bits implemented by the SoC + minimum: 1 + maximum: 8 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - arm,num-irq-priority-bits + +additionalProperties: false + +examples: + - | + interrupt-controller@e000e100 { + compatible = "arm,v7m-nvic"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0xe000e100 0xc00>; + arm,num-irq-priority-bits = <4>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt deleted file mode 100644 index ea939f54c5eb1..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt +++ /dev/null @@ -1,38 +0,0 @@ -* ARM Versatile FPGA interrupt controller - -One or more FPGA IRQ controllers can be synthesized in an ARM reference board -such as the Integrator or Versatile family. The output of these different -controllers are OR:ed together and fed to the CPU tile's IRQ input. Each -instance can handle up to 32 interrupts. - -Required properties: -- compatible: "arm,versatile-fpga-irq" -- interrupt-controller: Identifies the node as an interrupt controller -- #interrupt-cells: The number of cells to define the interrupts. Must be 1 - as the FPGA IRQ controller has no configuration options for interrupt - sources. The cell is a u32 and defines the interrupt number. -- reg: The register bank for the FPGA interrupt controller. -- clear-mask: a u32 number representing the mask written to clear all IRQs - on the controller at boot for example. -- valid-mask: a u32 number representing a bit mask determining which of - the interrupts are valid. Unconnected/unused lines are set to 0, and - the system till not make it possible for devices to request these - interrupts. - -The "oxsemi,ox810se-rps-irq" compatible is deprecated. - -Example: - -pic: pic@14000000 { - compatible = "arm,versatile-fpga-irq"; - #interrupt-cells = <1>; - interrupt-controller; - reg = <0x14000000 0x100>; - clear-mask = <0xffffffff>; - valid-mask = <0x003fffff>; -}; - -Optional properties: -- interrupts: if the FPGA IRQ controller is cascaded, i.e. if its IRQ - output is simply connected to the input of another IRQ controller, - then the parent IRQ shall be specified in this property. diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.yaml new file mode 100644 index 0000000000000..8d581b3aac3a1 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/arm,versatile-fpga-irq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Versatile FPGA IRQ Controller + +maintainers: + - Linus Walleij + +description: + One or more FPGA IRQ controllers can be synthesized in an ARM reference board + such as the Integrator or Versatile family. The output of these different + controllers are OR:ed together and fed to the CPU tile's IRQ input. Each + instance can handle up to 32 interrupts. + +properties: + compatible: + const: arm,versatile-fpga-irq + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + + reg: + maxItems: 1 + + clear-mask: + description: A mask written to clear all IRQs on the controller at boot. + $ref: /schemas/types.yaml#/definitions/uint32 + + valid-mask: + description: + A bit mask determining which interrupts are valid; unused lines are set to 0. + $ref: /schemas/types.yaml#/definitions/uint32 + + interrupts: + maxItems: 1 + +additionalProperties: false + +required: + - compatible + - interrupt-controller + - '#interrupt-cells' + - reg + - clear-mask + - valid-mask + +examples: + - | + interrupt-controller@14000000 { + compatible = "arm,versatile-fpga-irq"; + #interrupt-cells = <1>; + interrupt-controller; + reg = <0x14000000 0x100>; + clear-mask = <0xffffffff>; + valid-mask = <0x003fffff>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-i2c-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-i2c-ic.txt deleted file mode 100644 index 033cc82e56840..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-i2c-ic.txt +++ /dev/null @@ -1,25 +0,0 @@ -Device tree configuration for the I2C Interrupt Controller on the AST24XX and -AST25XX SoCs. - -Required Properties: -- #address-cells : should be 1 -- #size-cells : should be 1 -- #interrupt-cells : should be 1 -- compatible : should be "aspeed,ast2400-i2c-ic" - or "aspeed,ast2500-i2c-ic" -- reg : address start and range of controller -- interrupts : interrupt number -- interrupt-controller : denotes that the controller receives and fires - new interrupts for child busses - -Example: - -i2c_ic: interrupt-controller@0 { - #address-cells = <1>; - #size-cells = <1>; - #interrupt-cells = <1>; - compatible = "aspeed,ast2400-i2c-ic"; - reg = <0x0 0x40>; - interrupts = <12>; - interrupt-controller; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-i2c-ic.yaml b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-i2c-ic.yaml new file mode 100644 index 0000000000000..6cff6a7231bb8 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-i2c-ic.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2400-i2c-ic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed I2C Interrupt Controller (AST24XX/AST25XX) + +maintainers: + - Ryan Chen + +properties: + compatible: + enum: + - aspeed,ast2400-i2c-ic + - aspeed,ast2500-i2c-ic + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + +required: + - compatible + - reg + - '#interrupt-cells' + - interrupts + - interrupt-controller + +additionalProperties: false + +examples: + - | + interrupt-controller@0 { + compatible = "aspeed,ast2400-i2c-ic"; + reg = <0x0 0x40>; + #interrupt-cells = <1>; + interrupts = <12>; + interrupt-controller; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2500-scu-ic.yaml b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2500-scu-ic.yaml new file mode 100644 index 0000000000000..d5287a2bf866b --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2500-scu-ic.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2025 Eddie James +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2500-scu-ic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed AST25XX and AST26XX SCU Interrupt Controller + +maintainers: + - Eddie James + +properties: + compatible: + enum: + - aspeed,ast2500-scu-ic + - aspeed,ast2600-scu-ic0 + - aspeed,ast2600-scu-ic1 + + reg: + maxItems: 1 + + '#interrupt-cells': + const: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + +required: + - compatible + - reg + - '#interrupt-cells' + - interrupts + - interrupt-controller + +additionalProperties: false + +examples: + - | + interrupt-controller@18 { + compatible = "aspeed,ast2500-scu-ic"; + reg = <0x18 0x4>; + #interrupt-cells = <1>; + interrupts = <21>; + interrupt-controller; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2xxx-scu-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2xxx-scu-ic.txt deleted file mode 100644 index 251ed44171db8..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2xxx-scu-ic.txt +++ /dev/null @@ -1,23 +0,0 @@ -Aspeed AST25XX and AST26XX SCU Interrupt Controller - -Required Properties: - - #interrupt-cells : must be 1 - - compatible : must be "aspeed,ast2500-scu-ic", - "aspeed,ast2600-scu-ic0" or - "aspeed,ast2600-scu-ic1" - - interrupts : interrupt from the parent controller - - interrupt-controller : indicates that the controller receives and - fires new interrupts for child busses - -Example: - - syscon@1e6e2000 { - ranges = <0 0x1e6e2000 0x1a8>; - - scu_ic: interrupt-controller@18 { - #interrupt-cells = <1>; - compatible = "aspeed,ast2500-scu-ic"; - interrupts = <21>; - interrupt-controller; - }; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt deleted file mode 100644 index bdd173056f72a..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt +++ /dev/null @@ -1,131 +0,0 @@ -BCM2835 Top-Level ("ARMCTRL") Interrupt Controller - -The BCM2835 contains a custom top-level interrupt controller, which supports -72 interrupt sources using a 2-level register scheme. The interrupt -controller, or the HW block containing it, is referred to occasionally -as "armctrl" in the SoC documentation, hence naming of this binding. - -The BCM2836 contains the same interrupt controller with the same -interrupts, but the per-CPU interrupt controller is the root, and an -interrupt there indicates that the ARMCTRL has an interrupt to handle. - -Required properties: - -- compatible : should be "brcm,bcm2835-armctrl-ic" or - "brcm,bcm2836-armctrl-ic" -- reg : Specifies base physical address and size of the registers. -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value shall be 2. - - The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic - pending" register, or 1/2 respectively for interrupts in the "IRQ pending - 1/2" register. - - The 2nd cell contains the interrupt number within the bank. Valid values - are 0..7 for bank 0, and 0..31 for bank 1. - -Additional required properties for brcm,bcm2836-armctrl-ic: -- interrupts : Specifies the interrupt on the parent for this interrupt - controller to handle. - -The interrupt sources are as follows: - -Bank 0: -0: ARM_TIMER -1: ARM_MAILBOX -2: ARM_DOORBELL_0 -3: ARM_DOORBELL_1 -4: VPU0_HALTED -5: VPU1_HALTED -6: ILLEGAL_TYPE0 -7: ILLEGAL_TYPE1 - -Bank 1: -0: TIMER0 -1: TIMER1 -2: TIMER2 -3: TIMER3 -4: CODEC0 -5: CODEC1 -6: CODEC2 -7: VC_JPEG -8: ISP -9: VC_USB -10: VC_3D -11: TRANSPOSER -12: MULTICORESYNC0 -13: MULTICORESYNC1 -14: MULTICORESYNC2 -15: MULTICORESYNC3 -16: DMA0 -17: DMA1 -18: VC_DMA2 -19: VC_DMA3 -20: DMA4 -21: DMA5 -22: DMA6 -23: DMA7 -24: DMA8 -25: DMA9 -26: DMA10 -27: DMA11-14 - shared interrupt for DMA 11 to 14 -28: DMAALL - triggers on all dma interrupts (including channel 15) -29: AUX -30: ARM -31: VPUDMA - -Bank 2: -0: HOSTPORT -1: VIDEOSCALER -2: CCP2TX -3: SDC -4: DSI0 -5: AVE -6: CAM0 -7: CAM1 -8: HDMI0 -9: HDMI1 -10: PIXELVALVE1 -11: I2CSPISLV -12: DSI1 -13: PWA0 -14: PWA1 -15: CPR -16: SMI -17: GPIO0 -18: GPIO1 -19: GPIO2 -20: GPIO3 -21: VC_I2C -22: VC_SPI -23: VC_I2SPCM -24: VC_SDIO -25: VC_UART -26: SLIMBUS -27: VEC -28: CPG -29: RNG -30: VC_ARASANSDIO -31: AVSPMON - -Example: - -/* BCM2835, first level */ -intc: interrupt-controller { - compatible = "brcm,bcm2835-armctrl-ic"; - reg = <0x7e00b200 0x200>; - interrupt-controller; - #interrupt-cells = <2>; -}; - -/* BCM2836, second level */ -intc: interrupt-controller { - compatible = "brcm,bcm2836-armctrl-ic"; - reg = <0x7e00b200 0x200>; - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&local_intc>; - interrupts = <8>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.yaml b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.yaml new file mode 100644 index 0000000000000..625eb22bedf0b --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.yaml @@ -0,0 +1,162 @@ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm2835-armctrl-ic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: BCM2835 ARMCTRL Interrupt Controller + +maintainers: + - Florian Fainelli + - Raspberry Pi Kernel Maintenance + +description: > + The BCM2835 contains a custom top-level interrupt controller, which supports + 72 interrupt sources using a 2-level register scheme. The interrupt + controller, or the HW block containing it, is referred to occasionally as + "armctrl" in the SoC documentation, hence naming of this binding. + + The BCM2836 contains the same interrupt controller with the same interrupts, + but the per-CPU interrupt controller is the root, and an interrupt there + indicates that the ARMCTRL has an interrupt to handle. + + The interrupt sources are as follows: + + Bank 0: + 0: ARM_TIMER + 1: ARM_MAILBOX + 2: ARM_DOORBELL_0 + 3: ARM_DOORBELL_1 + 4: VPU0_HALTED + 5: VPU1_HALTED + 6: ILLEGAL_TYPE0 + 7: ILLEGAL_TYPE1 + + Bank 1: + 0: TIMER0 + 1: TIMER1 + 2: TIMER2 + 3: TIMER3 + 4: CODEC0 + 5: CODEC1 + 6: CODEC2 + 7: VC_JPEG + 8: ISP + 9: VC_USB + 10: VC_3D + 11: TRANSPOSER + 12: MULTICORESYNC0 + 13: MULTICORESYNC1 + 14: MULTICORESYNC2 + 15: MULTICORESYNC3 + 16: DMA0 + 17: DMA1 + 18: VC_DMA2 + 19: VC_DMA3 + 20: DMA4 + 21: DMA5 + 22: DMA6 + 23: DMA7 + 24: DMA8 + 25: DMA9 + 26: DMA10 + 27: DMA11-14 - shared interrupt for DMA 11 to 14 + 28: DMAALL - triggers on all dma interrupts (including channel 15) + 29: AUX + 30: ARM + 31: VPUDMA + + Bank 2: + 0: HOSTPORT + 1: VIDEOSCALER + 2: CCP2TX + 3: SDC + 4: DSI0 + 5: AVE + 6: CAM0 + 7: CAM1 + 8: HDMI0 + 9: HDMI1 + 10: PIXELVALVE1 + 11: I2CSPISLV + 12: DSI1 + 13: PWA0 + 14: PWA1 + 15: CPR + 16: SMI + 17: GPIO0 + 18: GPIO1 + 19: GPIO2 + 20: GPIO3 + 21: VC_I2C + 22: VC_SPI + 23: VC_I2SPCM + 24: VC_SDIO + 25: VC_UART + 26: SLIMBUS + 27: VEC + 28: CPG + 29: RNG + 30: VC_ARASANSDIO + 31: AVSPMON + +properties: + compatible: + enum: + - brcm,bcm2835-armctrl-ic + - brcm,bcm2836-armctrl-ic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + description: > + The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic + pending" register, or 1/2 respectively for interrupts in the "IRQ pending + 1/2" register. + + The 2nd cell contains the interrupt number within the bank. Valid values + are 0..7 for bank 0, and 0..31 for bank 1. + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +allOf: + - if: + properties: + compatible: + contains: + const: brcm,bcm2836-armctrl-ic + then: + required: + - interrupts + else: + properties: + interrupts: false + +additionalProperties: false + +examples: + - | + interrupt-controller@7e00b200 { + compatible = "brcm,bcm2835-armctrl-ic"; + reg = <0x7e00b200 0x200>; + interrupt-controller; + #interrupt-cells = <2>; + }; + - | + interrupt-controller@7e00b200 { + compatible = "brcm,bcm2836-armctrl-ic"; + reg = <0x7e00b200 0x200>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <8>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-l1-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-l1-intc.txt deleted file mode 100644 index 2bc19b1ac877b..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-l1-intc.txt +++ /dev/null @@ -1,55 +0,0 @@ -Broadcom BCM6345-style Level 1 interrupt controller - -This block is a first level interrupt controller that is typically connected -directly to one of the HW INT lines on each CPU. - -Key elements of the hardware design include: - -- 32, 64 or 128 incoming level IRQ lines - -- Most onchip peripherals are wired directly to an L1 input - -- A separate instance of the register set for each CPU, allowing individual - peripheral IRQs to be routed to any CPU - -- Contains one or more enable/status word pairs per CPU - -- No atomic set/clear operations - -- No polarity/level/edge settings - -- No FIFO or priority encoder logic; software is expected to read all - 2-4 status words to determine which IRQs are pending - -Required properties: - -- compatible: should be "brcm,bcm-l1-intc", "brcm,bcm6345-l1-intc" -- reg: specifies the base physical address and size of the registers; - the number of supported IRQs is inferred from the size argument -- interrupt-controller: identifies the node as an interrupt controller -- #interrupt-cells: specifies the number of cells needed to encode an interrupt - source, should be 1. -- interrupts: specifies the interrupt line(s) in the interrupt-parent controller - node; valid values depend on the type of parent interrupt controller - -If multiple reg ranges and interrupt-parent entries are present on an SMP -system, the driver will allow IRQ SMP affinity to be set up through the -/proc/irq/ interface. In the simplest possible configuration, only one -reg range and one interrupt-parent is needed. - -The driver operates in native CPU endian by default, there is no support for -specifying an alternative endianness. - -Example: - -periph_intc: interrupt-controller@10000000 { - compatible = "brcm,bcm63168-l1-intc", "brcm,bcm6345-l1-intc"; - reg = <0x10000020 0x20>, - <0x10000040 0x20>; - - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-parent = <&cpu_intc>; - interrupts = <2>, <3>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-l1-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-l1-intc.yaml new file mode 100644 index 0000000000000..ca6a2ff43acdb --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-l1-intc.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm6345-l1-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM6345-style Level 1 interrupt controller + +maintainers: + - Simon Arlott + +description: > + This block is a first level interrupt controller that is typically connected + directly to one of the HW INT lines on each CPU. + + Key elements of the hardware design include: + + - 32, 64 or 128 incoming level IRQ lines + + - Most onchip peripherals are wired directly to an L1 input + + - A separate instance of the register set for each CPU, allowing individual + peripheral IRQs to be routed to any CPU + + - Contains one or more enable/status word pairs per CPU + + - No atomic set/clear operations + + - No polarity/level/edge settings + + - No FIFO or priority encoder logic; software is expected to read all + 2-4 status words to determine which IRQs are pending + + If multiple reg ranges and interrupt-parent entries are present on an SMP + system, the driver will allow IRQ SMP affinity to be set up through the + /proc/irq/ interface. In the simplest possible configuration, only one + reg range and one interrupt-parent is needed. + + The driver operates in native CPU endian by default, there is no support for + specifying an alternative endianness. + +properties: + compatible: + const: brcm,bcm6345-l1-intc + + reg: + description: One entry per CPU core + minItems: 1 + maxItems: 2 + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + + interrupts: + description: One entry per CPU core + minItems: 1 + maxItems: 2 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - interrupts + +additionalProperties: false + +examples: + - | + interrupt-controller@10000000 { + compatible = "brcm,bcm6345-l1-intc"; + reg = <0x10000020 0x20>, + <0x10000040 0x20>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupts = <2>, <3>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/cdns,xtensa-mx.txt b/Documentation/devicetree/bindings/interrupt-controller/cdns,xtensa-mx.txt deleted file mode 100644 index d4de980e55fa6..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/cdns,xtensa-mx.txt +++ /dev/null @@ -1,18 +0,0 @@ -* Xtensa Interrupt Distributor and Programmable Interrupt Controller (MX) - -Required properties: -- compatible: Should be "cdns,xtensa-mx". - -Remaining properties have exact same meaning as in Xtensa PIC -(see cdns,xtensa-pic.txt). - -Examples: - pic: pic { - compatible = "cdns,xtensa-mx"; - /* one cell: internal irq number, - * two cells: second cell == 0: internal irq number - * second cell == 1: external irq number - */ - #interrupt-cells = <2>; - interrupt-controller; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/cdns,xtensa-pic.txt b/Documentation/devicetree/bindings/interrupt-controller/cdns,xtensa-pic.txt deleted file mode 100644 index 026ef4cfc1d52..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/cdns,xtensa-pic.txt +++ /dev/null @@ -1,25 +0,0 @@ -* Xtensa built-in Programmable Interrupt Controller (PIC) - -Required properties: -- compatible: Should be "cdns,xtensa-pic". -- interrupt-controller: Identifies the node as an interrupt controller. -- #interrupt-cells: The number of cells to define the interrupts. - It may be either 1 or 2. - When it's 1, the first cell is the internal IRQ number. - When it's 2, the first cell is the IRQ number, and the second cell - specifies whether it's internal (0) or external (1). - Periferals are usually connected to a fixed external IRQ, but for different - core variants it may be mapped to different internal IRQ. - IRQ sensitivity and priority are fixed for each core variant and may not be - changed at runtime. - -Examples: - pic: pic { - compatible = "cdns,xtensa-pic"; - /* one cell: internal irq number, - * two cells: second cell == 0: internal irq number - * second cell == 1: external irq number - */ - #interrupt-cells = <2>; - interrupt-controller; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/cdns,xtensa-pic.yaml b/Documentation/devicetree/bindings/interrupt-controller/cdns,xtensa-pic.yaml new file mode 100644 index 0000000000000..6773207fee013 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/cdns,xtensa-pic.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2025 Max Filippov + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/cdns,xtensa-pic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xtensa Interrupt Controllers + +maintainers: + - Max Filippov + +description: + Xtensa Interrupt Distributor and Programmable Interrupt Controller (MX) and + Xtensa built-in Programmable Interrupt Controller (PIC) + +properties: + compatible: + enum: + - cdns,xtensa-mx + - cdns,xtensa-pic + + '#interrupt-cells': + enum: [ 1, 2 ] + description: + Number of cells to define the interrupts. When 1, the first cell is the + internal IRQ number; when 2, the second cell specifies internal (0) or + external (1). + + interrupt-controller: true + +required: + - compatible + - '#interrupt-cells' + - interrupt-controller + +additionalProperties: false + +examples: + - | + interrupt-controller { + compatible = "cdns,xtensa-pic"; + /* one cell: internal irq number, + * two cells: second cell == 0: internal irq number + * second cell == 1: external irq number + */ + #interrupt-cells = <2>; + interrupt-controller; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/chrp,open-pic.yaml b/Documentation/devicetree/bindings/interrupt-controller/chrp,open-pic.yaml new file mode 100644 index 0000000000000..f0d9bbd7d510a --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/chrp,open-pic.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/chrp,open-pic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Open PIC Interrupt Controller + +maintainers: + - Rob Herring + +description: + This binding specifies what properties must be available in the device tree + representation of an Open PIC compliant interrupt controller. This binding is + based on the binding defined for Open PIC in [1] and is a superset of that + binding. + +properties: + compatible: + oneOf: + - items: + - const: fsl,mpic + - const: chrp,open-pic + - const: chrp,open-pic + + device_type: + const: open-pci + deprecated: true + + reg: + maxItems: 1 + + interrupt-controller: true + + '#address-cells': + const: 0 + + '#interrupt-cells': + const: 2 + + pic-no-reset: + description: Indicates the PIC shall not be reset during runtime initialization. + type: boolean + +required: + - compatible + - reg + - interrupt-controller + - '#address-cells' + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller@40000 { + compatible = "chrp,open-pic"; + reg = <0x40000 0x40000>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + pic-no-reset; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/cirrus,clps711x-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/cirrus,clps711x-intc.txt deleted file mode 100644 index 969b4582ec604..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/cirrus,clps711x-intc.txt +++ /dev/null @@ -1,41 +0,0 @@ -Cirrus Logic CLPS711X Interrupt Controller - -Required properties: - -- compatible: Should be "cirrus,ep7209-intc". -- reg: Specifies base physical address of the registers set. -- interrupt-controller: Identifies the node as an interrupt controller. -- #interrupt-cells: Specifies the number of cells needed to encode an - interrupt source. The value shall be 1. - -The interrupt sources are as follows: -ID Name Description ---------------------------- -1: BLINT Battery low (FIQ) -3: MCINT Media changed (FIQ) -4: CSINT CODEC sound -5: EINT1 External 1 -6: EINT2 External 2 -7: EINT3 External 3 -8: TC1OI TC1 under flow -9: TC2OI TC2 under flow -10: RTCMI RTC compare match -11: TINT 64Hz tick -12: UTXINT1 UART1 transmit FIFO half empty -13: URXINT1 UART1 receive FIFO half full -14: UMSINT UART1 modem status changed -15: SSEOTI SSI1 end of transfer -16: KBDINT Keyboard -17: SS2RX SSI2 receive FIFO half or greater full -18: SS2TX SSI2 transmit FIFO less than half empty -28: UTXINT2 UART2 transmit FIFO half empty -29: URXINT2 UART2 receive FIFO half full -32: DAIINT DAI interface (FIQ) - -Example: - intc: interrupt-controller { - compatible = "cirrus,ep7312-intc", "cirrus,ep7209-intc"; - reg = <0x80000000 0x4000>; - interrupt-controller; - #interrupt-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/cirrus,ep7209-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/cirrus,ep7209-intc.yaml new file mode 100644 index 0000000000000..d3cc49d29e103 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/cirrus,ep7209-intc.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/cirrus,ep7209-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic CLPS711X Interrupt Controller + +maintainers: + - Alexander Shiyan + +description: > + Cirrus Logic CLPS711X Interrupt Controller + + The interrupt sources are as follows: + ID Name Description + --------------------------- + 1: BLINT Battery low (FIQ) + 3: MCINT Media changed (FIQ) + 4: CSINT CODEC sound + 5: EINT1 External 1 + 6: EINT2 External 2 + 7: EINT3 External 3 + 8: TC1OI TC1 under flow + 9: TC2OI TC2 under flow + 10: RTCMI RTC compare match + 11: TINT 64Hz tick + 12: UTXINT1 UART1 transmit FIFO half empty + 13: URXINT1 UART1 receive FIFO half full + 14: UMSINT UART1 modem status changed + 15: SSEOTI SSI1 end of transfer + 16: KBDINT Keyboard + 17: SS2RX SSI2 receive FIFO half or greater full + 18: SS2TX SSI2 transmit FIFO less than half empty + 28: UTXINT2 UART2 transmit FIFO half empty + 29: URXINT2 UART2 receive FIFO half full + 32: DAIINT DAI interface (FIQ) + +properties: + compatible: + oneOf: + - items: + - const: cirrus,ep7312-intc + - const: cirrus,ep7209-intc + - items: + - const: cirrus,ep7209-intc + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller@80000000 { + compatible = "cirrus,ep7312-intc", "cirrus,ep7209-intc"; + reg = <0x80000000 0x4000>; + interrupt-controller; + #interrupt-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/cnxt,cx92755-ic.yaml b/Documentation/devicetree/bindings/interrupt-controller/cnxt,cx92755-ic.yaml new file mode 100644 index 0000000000000..3f016cf478125 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/cnxt,cx92755-ic.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/cnxt,cx92755-ic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Conexant Digicolor Interrupt Controller + +maintainers: + - Baruch Siach + +description: Conexant Digicolor Interrupt Controller + +properties: + compatible: + const: cnxt,cx92755-ic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + + syscon: + description: A phandle to the syscon node describing UC registers + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - syscon + +additionalProperties: false + +examples: + - | + interrupt-controller@f0000040 { + compatible = "cnxt,cx92755-ic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xf0000040 0x40>; + syscon = <&uc_regs>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt deleted file mode 100644 index 44286dcbac626..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt +++ /dev/null @@ -1,62 +0,0 @@ -============================== -C-SKY APB Interrupt Controller -============================== - -C-SKY APB Interrupt Controller is a simple soc interrupt controller -on the apb bus and we only use it as root irq controller. - - - csky,apb-intc is used in a lot of csky fpgas and socs, it support 64 irq nums. - - csky,dual-apb-intc consists of 2 apb-intc and 128 irq nums supported. - - csky,gx6605s-intc is gx6605s soc internal irq interrupt controller, 64 irq nums. - -============================= -intc node bindings definition -============================= - - Description: Describes APB interrupt controller - - PROPERTIES - - - compatible - Usage: required - Value type: - Definition: must be "csky,apb-intc" - "csky,dual-apb-intc" - "csky,gx6605s-intc" - - #interrupt-cells - Usage: required - Value type: - Definition: must be <1> - - reg - Usage: required - Value type: - Definition: in soc from cpu view - - interrupt-controller: - Usage: required - - csky,support-pulse-signal: - Usage: select - Description: to support pulse signal flag - -Examples: ---------- - - intc: interrupt-controller@500000 { - compatible = "csky,apb-intc"; - #interrupt-cells = <1>; - reg = <0x00500000 0x400>; - interrupt-controller; - }; - - intc: interrupt-controller@500000 { - compatible = "csky,dual-apb-intc"; - #interrupt-cells = <1>; - reg = <0x00500000 0x400>; - interrupt-controller; - }; - - intc: interrupt-controller@500000 { - compatible = "csky,gx6605s-intc"; - #interrupt-cells = <1>; - reg = <0x00500000 0x400>; - interrupt-controller; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.yaml new file mode 100644 index 0000000000000..902648ead9755 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/csky,apb-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: C-SKY APB Interrupt Controller + +maintainers: + - Guo Ren + +description: > + C-SKY APB Interrupt Controller is a simple soc interrupt controller on the apb + bus and we only use it as root irq controller. + + - csky,apb-intc is used in a lot of csky fpgas and socs, it support 64 irq nums. + - csky,dual-apb-intc consists of 2 apb-intc and 128 irq nums supported. + - csky,gx6605s-intc is gx6605s soc internal irq interrupt controller, 64 irq nums. + +properties: + compatible: + enum: + - csky,apb-intc + - csky,dual-apb-intc + - csky,gx6605s-intc + + reg: + maxItems: 1 + + '#interrupt-cells': + const: 1 + + interrupt-controller: true + + csky,support-pulse-signal: + type: boolean + description: Support for pulse signal flag. + +additionalProperties: false + +required: + - compatible + - reg + - '#interrupt-cells' + - interrupt-controller + +examples: + - | + intc: interrupt-controller@500000 { + compatible = "csky,apb-intc"; + #interrupt-cells = <1>; + reg = <0x00500000 0x400>; + interrupt-controller; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt b/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt deleted file mode 100644 index e6bbcae4d07fb..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt +++ /dev/null @@ -1,52 +0,0 @@ -=========================================== -C-SKY Multi-processors Interrupt Controller -=========================================== - -C-SKY Multi-processors Interrupt Controller is designed for ck807/ck810/ck860 -SMP soc, and it also could be used in non-SMP system. - -Interrupt number definition: - 0-15 : software irq, and we use 15 as our IPI_IRQ. - 16-31 : private irq, and we use 16 as the co-processor timer. - 31-1024: common irq for soc ip. - -Interrupt trigger mode: (Defined in dt-bindings/interrupt-controller/irq.h) - IRQ_TYPE_LEVEL_HIGH (default) - IRQ_TYPE_LEVEL_LOW - IRQ_TYPE_EDGE_RISING - IRQ_TYPE_EDGE_FALLING - -============================= -intc node bindings definition -============================= - - Description: Describes SMP interrupt controller - - PROPERTIES - - - compatible - Usage: required - Value type: - Definition: must be "csky,mpintc" - - #interrupt-cells - Usage: required - Value type: - Definition: <2> - - interrupt-controller: - Usage: required - -Examples: ("interrupts = ") ---------- -#include - - intc: interrupt-controller { - compatible = "csky,mpintc"; - #interrupt-cells = <2>; - interrupt-controller; - }; - - device: device-example { - ... - interrupts = <34 IRQ_TYPE_EDGE_RISING>; - interrupt-parent = <&intc>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.yaml b/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.yaml new file mode 100644 index 0000000000000..3df7739e31c46 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/csky,mpintc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: C-SKY Multi-processors Interrupt Controller + +maintainers: + - Guo Ren + +description: > + C-SKY Multi-processors Interrupt Controller is designed for ck807/ck810/ck860 + SMP soc, and it also could be used in non-SMP system. + + Interrupt number definition: + 0-15 : software irq, and we use 15 as our IPI_IRQ. + 16-31 : private irq, and we use 16 as the co-processor timer. + 31-1024: common irq for soc ip. + +properties: + compatible: + const: csky,mpintc + + '#interrupt-cells': + const: 2 + + interrupt-controller: true + +required: + - compatible + - "#interrupt-cells" + - interrupt-controller + +additionalProperties: false + +examples: + - | + interrupt-controller { + compatible = "csky,mpintc"; + #interrupt-cells = <2>; + interrupt-controller; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/digicolor-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/digicolor-ic.txt deleted file mode 100644 index 42d41ec84c7bd..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/digicolor-ic.txt +++ /dev/null @@ -1,21 +0,0 @@ -Conexant Digicolor Interrupt Controller - -Required properties: - -- compatible : should be "cnxt,cx92755-ic" -- reg : Specifies base physical address and size of the interrupt controller - registers (IC) area -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value shall be 1. -- syscon: A phandle to the syscon node describing UC registers - -Example: - - intc: interrupt-controller@f0000040 { - compatible = "cnxt,cx92755-ic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xf0000040 0x40>; - syscon = <&uc_regs>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml new file mode 100644 index 0000000000000..5536319c49c31 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/econet,en751221-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EcoNet EN751221 Interrupt Controller + +maintainers: + - Caleb James DeLisle + +description: + The EcoNet EN751221 Interrupt Controller is a simple interrupt controller + designed for the MIPS 34Kc MT SMP processor with 2 VPEs. Each interrupt can + be routed to either VPE but not both, so to support per-CPU interrupts, a + secondary IRQ number is allocated to control masking/unmasking on VPE#1. For + lack of a better term we call these "shadow interrupts". The assignment of + shadow interrupts is defined by the SoC integrator when wiring the interrupt + lines, so they are configurable in the device tree. + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + const: econet,en751221-intc + + reg: + maxItems: 1 + + "#interrupt-cells": + const: 1 + + interrupt-controller: true + + interrupts: + maxItems: 1 + description: Interrupt line connecting this controller to its parent. + + econet,shadow-interrupts: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: + An array of interrupt number pairs where each pair represents a shadow + interrupt relationship. The first number in each pair is the primary IRQ, + and the second is its shadow IRQ used for VPE#1 control. For example, + <8 3> means IRQ 8 is shadowed by IRQ 3, so IRQ 3 cannot be mapped, but + when VPE#1 requests IRQ 8, it will manipulate the IRQ 3 mask bit. + minItems: 1 + maxItems: 20 + items: + items: + - description: primary per-CPU IRQ + - description: shadow IRQ number + +required: + - compatible + - reg + - interrupt-controller + - "#interrupt-cells" + - interrupts + +additionalProperties: false + +examples: + - | + interrupt-controller@1fb40000 { + compatible = "econet,en751221-intc"; + reg = <0x1fb40000 0x100>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; + + econet,shadow-interrupts = <7 2>, <8 3>, <13 12>, <30 29>; + }; +... diff --git a/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt deleted file mode 100644 index 888b2b9f70648..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt +++ /dev/null @@ -1,17 +0,0 @@ -EZchip NPS Interrupt Controller - -Required properties: - -- compatible : should be "ezchip,nps400-ic" -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value shall be 1. - - -Example: - -intc: interrupt-controller { - compatible = "ezchip,nps400-ic"; - interrupt-controller; - #interrupt-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.yaml b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.yaml new file mode 100644 index 0000000000000..589c6ebf6c1a1 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.yaml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ezchip,nps400-ic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EZchip NPS Interrupt Controller + +maintainers: + - Noam Camus + +properties: + compatible: + const: ezchip,nps400-ic + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + +required: + - compatible + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller { + compatible = "ezchip,nps400-ic"; + interrupt-controller; + #interrupt-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/faraday,ftintc010.txt b/Documentation/devicetree/bindings/interrupt-controller/faraday,ftintc010.txt deleted file mode 100644 index 24428d47f4872..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/faraday,ftintc010.txt +++ /dev/null @@ -1,25 +0,0 @@ -* Faraday Technologt FTINTC010 interrupt controller - -This interrupt controller is a stock IP block from Faraday Technology found -in the Gemini SoCs and other designs. - -Required properties: -- compatible: must be one of - "faraday,ftintc010" - "cortina,gemini-interrupt-controller" (deprecated) -- reg: The register bank for the interrupt controller. -- interrupt-controller: Identifies the node as an interrupt controller -- #interrupt-cells: The number of cells to define the interrupts. - Must be 2 as the controller can specify level or rising edge - IRQs. The bindings follows the standard binding for controllers - with two cells specified in - interrupt-controller/interrupts.txt - -Example: - -interrupt-controller@48000000 { - compatible = "faraday,ftintc010" - reg = <0x48000000 0x1000>; - interrupt-controller; - #interrupt-cells = <2>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/faraday,ftintc010.yaml b/Documentation/devicetree/bindings/interrupt-controller/faraday,ftintc010.yaml new file mode 100644 index 0000000000000..980e5c45f25b1 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/faraday,ftintc010.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +--- +$id: http://devicetree.org/schemas/interrupt-controller/faraday,ftintc010.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Faraday Technology FTINTC010 interrupt controller + +maintainers: + - Linus Walleij + +description: + This interrupt controller is a stock IP block from Faraday Technology found + in the Gemini SoCs and other designs. + +properties: + compatible: + oneOf: + - items: + - const: moxa,moxart-ic + - const: faraday,ftintc010 + - enum: + - faraday,ftintc010 + - cortina,gemini-interrupt-controller + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller@48000000 { + compatible = "faraday,ftintc010"; + reg = <0x48000000 0x1000>; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,tzic.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,tzic.yaml new file mode 100644 index 0000000000000..5f2c8761a31de --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,tzic.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/fsl,tzic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale tzic Interrupt controller + +maintainers: + - Frank Li + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,imx51-tzic + - fsl,imx53-tzic + - const: fsl,tzic + - items: + - const: fsl,imx50-tzic + - const: fsl,imx53-tzic + - const: fsl,tzic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + tz-interrupt-controller@fffc000 { + compatible = "fsl,imx53-tzic", "fsl,tzic"; + reg = <0x0fffc000 0x4000>; + interrupt-controller; + #interrupt-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.txt b/Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.txt deleted file mode 100644 index 35f752706e7d6..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.txt +++ /dev/null @@ -1,30 +0,0 @@ -Android Goldfish PIC - -Android Goldfish programmable interrupt device used by Android -emulator. - -Required properties: - -- compatible : should contain "google,goldfish-pic" -- reg : -- interrupts : - -Example for mips when used in cascade mode: - - cpuintc { - #interrupt-cells = <0x1>; - #address-cells = <0>; - interrupt-controller; - compatible = "mti,cpu-interrupt-controller"; - }; - - interrupt-controller@1f000000 { - compatible = "google,goldfish-pic"; - reg = <0x1f000000 0x1000>; - - interrupt-controller; - #interrupt-cells = <0x1>; - - interrupt-parent = <&cpuintc>; - interrupts = <0x2>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.yaml b/Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.yaml new file mode 100644 index 0000000000000..ac3c3c3ca1862 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/google,goldfish-pic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Android Goldfish PIC + +maintainers: + - Miodrag Dinic + +description: + Android Goldfish programmable interrupt device used by Android emulator. + +properties: + compatible: + const: google,goldfish-pic + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + +examples: + - | + interrupt-controller@1f000000 { + compatible = "google,goldfish-pic"; + reg = <0x1f000000 0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts = <2>; + }; + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/interrupt-controller/img,pdc-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/img,pdc-intc.txt deleted file mode 100644 index 5dc2a55ad8114..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/img,pdc-intc.txt +++ /dev/null @@ -1,105 +0,0 @@ -* ImgTec Powerdown Controller (PDC) Interrupt Controller Binding - -This binding specifies what properties must be available in the device tree -representation of a PDC IRQ controller. This has a number of input interrupt -lines which can wake the system, and are passed on through output interrupt -lines. - -Required properties: - - - compatible: Specifies the compatibility list for the interrupt controller. - The type shall be and the value shall include "img,pdc-intc". - - - reg: Specifies the base PDC physical address(s) and size(s) of the - addressable register space. The type shall be . - - - interrupt-controller: The presence of this property identifies the node - as an interrupt controller. No property value shall be defined. - - - #interrupt-cells: Specifies the number of cells needed to encode an - interrupt source. The type shall be a and the value shall be 2. - - - num-perips: Number of waking peripherals. - - - num-syswakes: Number of SysWake inputs. - - - interrupts: List of interrupt specifiers. The first specifier shall be the - shared SysWake interrupt, and remaining specifies shall be PDC peripheral - interrupts in order. - -* Interrupt Specifier Definition - - Interrupt specifiers consists of 2 cells encoded as follows: - - - <1st-cell>: The interrupt-number that identifies the interrupt source. - 0-7: Peripheral interrupts - 8-15: SysWake interrupts - - - <2nd-cell>: The level-sense information, encoded using the Linux interrupt - flags as follows (only 4 valid for peripheral interrupts): - 0 = none (decided by software) - 1 = low-to-high edge triggered - 2 = high-to-low edge triggered - 3 = both edge triggered - 4 = active-high level-sensitive (required for perip irqs) - 8 = active-low level-sensitive - -* Examples - -Example 1: - - /* - * TZ1090 PDC block - */ - pdc: pdc@02006000 { - // This is an interrupt controller node. - interrupt-controller; - - // Three cells to encode interrupt sources. - #interrupt-cells = <2>; - - // Offset address of 0x02006000 and size of 0x1000. - reg = <0x02006000 0x1000>; - - // Compatible with Meta hardware trigger block. - compatible = "img,pdc-intc"; - - // Three peripherals are connected. - num-perips = <3>; - - // Four SysWakes are connected. - num-syswakes = <4>; - - interrupts = <18 4 /* level */>, /* Syswakes */ - <30 4 /* level */>, /* Peripheral 0 (RTC) */ - <29 4 /* level */>, /* Peripheral 1 (IR) */ - <31 4 /* level */>; /* Peripheral 2 (WDT) */ - }; - -Example 2: - - /* - * An SoC peripheral that is wired through the PDC. - */ - rtc0 { - // The interrupt controller that this device is wired to. - interrupt-parent = <&pdc>; - - // Interrupt source Peripheral 0 - interrupts = <0 /* Peripheral 0 (RTC) */ - 4> /* IRQ_TYPE_LEVEL_HIGH */ - }; - -Example 3: - - /* - * An interrupt generating device that is wired to a SysWake pin. - */ - touchscreen0 { - // The interrupt controller that this device is wired to. - interrupt-parent = <&pdc>; - - // Interrupt source SysWake 0 that is active-low level-sensitive - interrupts = <8 /* SysWake0 */ - 8 /* IRQ_TYPE_LEVEL_LOW */>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/img,pdc-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/img,pdc-intc.yaml new file mode 100644 index 0000000000000..99e7a42815955 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/img,pdc-intc.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/img,pdc-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ImgTec Powerdown Controller (PDC) Interrupt Controller + +maintainers: + - James Hogan + +description: + ImgTec Powerdown Controller (PDC) Interrupt Controller has a number of input + interrupt lines which can wake the system, and are passed on through output + interrupt lines. + +properties: + compatible: + const: img,pdc-intc + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + description: > + <1st-cell>: The interrupt-number that identifies the interrupt source. + 0-7: Peripheral interrupts + 8-15: SysWake interrupts + + <2nd-cell>: The level-sense information, encoded using the Linux interrupt + flags as follows (only 4 valid for peripheral interrupts): + 0 = none (decided by software) + 1 = low-to-high edge triggered + 2 = high-to-low edge triggered + 3 = both edge triggered + 4 = active-high level-sensitive (required for perip irqs) + 8 = active-low level-sensitive + const: 2 + + num-perips: + description: Number of waking peripherals + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 8 + + num-syswakes: + description: Number of SysWake inputs + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 8 + + interrupts: + description: + First entry is syswake IRQ. Subsequent entries are 1 per peripheral. + minItems: 2 + maxItems: 9 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - num-perips + - num-syswakes + - interrupts + +additionalProperties: false + +examples: + - | + interrupt-controller@2006000 { + compatible = "img,pdc-intc"; + reg = <0x02006000 0x1000>; + interrupts = <18 4>, <30 4>, <29 4>, <31 4>; + interrupt-controller; + #interrupt-cells = <2>; + num-perips = <3>; + num-syswakes = <4>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt deleted file mode 100644 index ee2ad36f8df8c..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt +++ /dev/null @@ -1,26 +0,0 @@ -J-Core Advanced Interrupt Controller - -Required properties: - -- compatible: Should be "jcore,aic1" for the (obsolete) first-generation aic - with 8 interrupt lines with programmable priorities, or "jcore,aic2" for - the "aic2" core with 64 interrupts. - -- reg: Memory region(s) for configuration. For SMP, there should be one - region per cpu, indexed by the sequential, zero-based hardware cpu - number. - -- interrupt-controller: Identifies the node as an interrupt controller - -- #interrupt-cells: Specifies the number of cells needed to encode an - interrupt source. The value shall be 1. - - -Example: - -aic: interrupt-controller@200 { - compatible = "jcore,aic2"; - reg = < 0x200 0x30 0x500 0x30 >; - interrupt-controller; - #interrupt-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.yaml new file mode 100644 index 0000000000000..df8abc24591ca --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2018 Linaro Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/jcore,aic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: J-Core Advanced Interrupt Controller + +maintainers: + - Rich Felker + +properties: + compatible: + enum: + - jcore,aic1 + - jcore,aic2 + + reg: + description: Memory region(s) for configuration. For SMP, there should be one + region per CPU, indexed by the sequential, zero-based hardware CPU number. + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + aic: interrupt-controller@200 { + compatible = "jcore,aic2"; + reg = <0x200 0x30>, <0x500 0x30>; + interrupt-controller; + #interrupt-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/lsi,zevio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/lsi,zevio-intc.txt deleted file mode 100644 index aee38e7c13e7d..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/lsi,zevio-intc.txt +++ /dev/null @@ -1,18 +0,0 @@ -TI-NSPIRE interrupt controller - -Required properties: -- compatible: Compatible property value should be "lsi,zevio-intc". - -- reg: Physical base address of the controller and length of memory mapped - region. - -- interrupt-controller : Identifies the node as an interrupt controller - -Example: - -interrupt-controller { - compatible = "lsi,zevio-intc"; - interrupt-controller; - reg = <0xDC000000 0x1000>; - #interrupt-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/lsi,zevio-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/lsi,zevio-intc.yaml new file mode 100644 index 0000000000000..e66b25f579c37 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/lsi,zevio-intc.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2025 Daniel Tang +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/lsi,zevio-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI-NSPIRE Interrupt Controller + +maintainers: + - Daniel Tang + +description: | + TI-NSPIRE interrupt controller + +properties: + compatible: + const: lsi,zevio-intc + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller@dc000000 { + compatible = "lsi,zevio-intc"; + interrupt-controller; + reg = <0xdc000000 0x1000>; + #interrupt-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,ap806-gicp.yaml b/Documentation/devicetree/bindings/interrupt-controller/marvell,ap806-gicp.yaml new file mode 100644 index 0000000000000..5faedd95b9a9a --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,ap806-gicp.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/marvell,ap806-gicp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell GICP Controller + +maintainers: + - Thomas Petazzoni + +description: + GICP is a Marvell extension of the GIC that allows to trigger GIC SPI + interrupts by doing a memory transaction. It is used by the ICU + located in the Marvell CP110 to turn wired interrupts inside the CP + into GIC SPI interrupts. + +properties: + compatible: + const: marvell,ap806-gicp + + reg: + maxItems: 1 + + marvell,spi-ranges: + description: Tuples of GIC SPI interrupt ranges available for this GICP + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: SPI interrupt base + - description: Number of interrupts in the range + + msi-controller: true + +required: + - compatible + - reg + - msi-controller + - marvell,spi-ranges + +additionalProperties: false + +examples: + - | + msi-controller@3f0040 { + compatible = "marvell,ap806-gicp"; + reg = <0x3f0040 0x10>; + marvell,spi-ranges = <64 64>, <288 64>; + msi-controller; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,ap806-sei.yaml b/Documentation/devicetree/bindings/interrupt-controller/marvell,ap806-sei.yaml new file mode 100644 index 0000000000000..e812f9a863078 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,ap806-sei.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/marvell,ap806-sei.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell SEI (System Error Interrupt) Controller + +maintainers: + - Miquel Raynal + +description: > + Marvell SEI (System Error Interrupt) controller is an interrupt aggregator. It + receives interrupts from several sources and aggregates them to a single + interrupt line (an SPI) on the parent interrupt controller. + + This interrupt controller can handle up to 64 SEIs, a set comes from the AP + and is wired while a second set comes from the CPs by the mean of MSIs. + +properties: + compatible: + const: marvell,ap806-sei + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + '#interrupt-cells': + const: 1 + + interrupt-controller: true + + msi-controller: true + +required: + - compatible + - reg + - interrupts + - '#interrupt-cells' + - interrupt-controller + - msi-controller + +additionalProperties: false + +examples: + - | + #include + + interrupt-controller@3f0200 { + compatible = "marvell,ap806-sei"; + reg = <0x3f0200 0x40>; + interrupts = ; + #interrupt-cells = <1>; + interrupt-controller; + msi-controller; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-8k-pic.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-8k-pic.txt deleted file mode 100644 index 86a7b4cd03f5d..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-8k-pic.txt +++ /dev/null @@ -1,25 +0,0 @@ -Marvell Armada 7K/8K PIC Interrupt controller ---------------------------------------------- - -This is the Device Tree binding for the PIC, a secondary interrupt -controller available on the Marvell Armada 7K/8K ARM64 SoCs, and -typically connected to the GIC as the primary interrupt controller. - -Required properties: -- compatible: should be "marvell,armada-8k-pic" -- interrupt-controller: identifies the node as an interrupt controller -- #interrupt-cells: the number of cells to define interrupts on this - controller. Should be 1 -- reg: the register area for the PIC interrupt controller -- interrupts: the interrupt to the primary interrupt controller, - typically the GIC - -Example: - - pic: interrupt-controller@3f0100 { - compatible = "marvell,armada-8k-pic"; - reg = <0x3f0100 0x10>; - #interrupt-cells = <1>; - interrupt-controller; - interrupts = ; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-8k-pic.yaml b/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-8k-pic.yaml new file mode 100644 index 0000000000000..5a455f7353db0 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-8k-pic.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/marvell,armada-8k-pic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 7K/8K PIC Interrupt controller + +maintainers: + - Thomas Petazzoni + +description: + The Marvell Armada 7K/8K PIC is a secondary interrupt controller available on + the Marvell Armada 7K/8K ARM64 SoCs, and typically connected to the GIC as the + primary interrupt controller. + +properties: + compatible: + const: marvell,armada-8k-pic + + reg: + maxItems: 1 + + "#interrupt-cells": + const: 1 + + interrupt-controller: true + + interrupts: + maxItems: 1 + description: Interrupt to the primary interrupt controller (GIC). + +required: + - compatible + - reg + - "#interrupt-cells" + - interrupt-controller + - interrupts + +additionalProperties: false + +examples: + - | + #include + + interrupt-controller@3f0100 { + compatible = "marvell,armada-8k-pic"; + reg = <0x3f0100 0x10>; + #interrupt-cells = <1>; + interrupt-controller; + interrupts = ; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,cp110-icu.yaml b/Documentation/devicetree/bindings/interrupt-controller/marvell,cp110-icu.yaml new file mode 100644 index 0000000000000..9d4f06f45372e --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,cp110-icu.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/marvell,cp110-icu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +maintainers: + - Miquel Raynal + - Thomas Petazzoni + +title: Marvell ICU Interrupt Controller + +description: + The Marvell ICU (Interrupt Consolidation Unit) controller is responsible for + collecting all wired-interrupt sources in the CP and communicating them to the + GIC in the AP. The unit translates interrupt requests on input wires to MSG + memory mapped transactions to the GIC. These messages access different GIC + memory areas depending on their type (NSR, SR, SEI, REI, etc). + +properties: + compatible: + const: marvell,cp110-icu + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + ranges: true + +patternProperties: + "^interrupt-controller@": + type: object + description: Interrupt group child nodes + additionalProperties: false + + properties: + compatible: + enum: + - marvell,cp110-icu-nsr + - marvell,cp110-icu-sr + - marvell,cp110-icu-sei + - marvell,cp110-icu-rei + + reg: + maxItems: 1 + + '#interrupt-cells': + const: 2 + + interrupt-controller: true + + msi-parent: + maxItems: 1 + description: Phandle to the GICP controller + + required: + - compatible + - reg + - '#interrupt-cells' + - interrupt-controller + - msi-parent + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + interrupt-controller@1e0000 { + compatible = "marvell,cp110-icu"; + reg = <0x1e0000 0x440>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupt-controller@10 { + compatible = "marvell,cp110-icu-nsr"; + reg = <0x10 0x20>; + #interrupt-cells = <2>; + interrupt-controller; + msi-parent = <&gicp>; + }; + + interrupt-controller@50 { + compatible = "marvell,cp110-icu-sei"; + reg = <0x50 0x10>; + #interrupt-cells = <2>; + interrupt-controller; + msi-parent = <&sei>; + }; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt deleted file mode 100644 index 64a00ceb7da42..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt +++ /dev/null @@ -1,27 +0,0 @@ -Marvell GICP Controller ------------------------ - -GICP is a Marvell extension of the GIC that allows to trigger GIC SPI -interrupts by doing a memory transaction. It is used by the ICU -located in the Marvell CP110 to turn wired interrupts inside the CP -into GIC SPI interrupts. - -Required properties: - -- compatible: Must be "marvell,ap806-gicp" - -- reg: Must be the address and size of the GICP SPI registers - -- marvell,spi-ranges: tuples of GIC SPI interrupts ranges available - for this GICP - -- msi-controller: indicates that this is an MSI controller - -Example: - -gicp_spi: gicp-spi@3f0040 { - compatible = "marvell,ap806-gicp"; - reg = <0x3f0040 0x10>; - marvell,spi-ranges = <64 64>, <288 64>; - msi-controller; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt deleted file mode 100644 index 1c94a57a661e2..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt +++ /dev/null @@ -1,112 +0,0 @@ -Marvell ICU Interrupt Controller --------------------------------- - -The Marvell ICU (Interrupt Consolidation Unit) controller is -responsible for collecting all wired-interrupt sources in the CP and -communicating them to the GIC in the AP, the unit translates interrupt -requests on input wires to MSG memory mapped transactions to the GIC. -These messages will access a different GIC memory area depending on -their type (NSR, SR, SEI, REI, etc). - -Required properties: - -- compatible: Should be "marvell,cp110-icu" - -- reg: Should contain ICU registers location and length. - -Subnodes: Each group of interrupt is declared as a subnode of the ICU, -with their own compatible. - -Required properties for the icu_nsr/icu_sei subnodes: - -- compatible: Should be one of: - * "marvell,cp110-icu-nsr" - * "marvell,cp110-icu-sr" - * "marvell,cp110-icu-sei" - * "marvell,cp110-icu-rei" - -- #interrupt-cells: Specifies the number of cells needed to encode an - interrupt source. The value shall be 2. - - The 1st cell is the index of the interrupt in the ICU unit. - - The 2nd cell is the type of the interrupt. See arm,gic.txt for - details. - -- interrupt-controller: Identifies the node as an interrupt - controller. - -- msi-parent: Should point to the GICP controller, the GIC extension - that allows to trigger interrupts using MSG memory mapped - transactions. - -Note: each 'interrupts' property referring to any 'icu_xxx' node shall - have a different number within [0:206]. - -Example: - -icu: interrupt-controller@1e0000 { - compatible = "marvell,cp110-icu"; - reg = <0x1e0000 0x440>; - - CP110_LABEL(icu_nsr): interrupt-controller@10 { - compatible = "marvell,cp110-icu-nsr"; - reg = <0x10 0x20>; - #interrupt-cells = <2>; - interrupt-controller; - msi-parent = <&gicp>; - }; - - CP110_LABEL(icu_sei): interrupt-controller@50 { - compatible = "marvell,cp110-icu-sei"; - reg = <0x50 0x10>; - #interrupt-cells = <2>; - interrupt-controller; - msi-parent = <&sei>; - }; -}; - -node1 { - interrupt-parent = <&icu_nsr>; - interrupts = <106 IRQ_TYPE_LEVEL_HIGH>; -}; - -node2 { - interrupt-parent = <&icu_sei>; - interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; -}; - -/* Would not work with the above nodes */ -node3 { - interrupt-parent = <&icu_nsr>; - interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; -}; - -The legacy bindings were different in this way: - -- #interrupt-cells: The value was 3. - The 1st cell was the group type of the ICU interrupt. Possible - group types were: - ICU_GRP_NSR (0x0) : Shared peripheral interrupt, non-secure - ICU_GRP_SR (0x1) : Shared peripheral interrupt, secure - ICU_GRP_SEI (0x4) : System error interrupt - ICU_GRP_REI (0x5) : RAM error interrupt - The 2nd cell was the index of the interrupt in the ICU unit. - The 3rd cell was the type of the interrupt. See arm,gic.txt for - details. - -Example: - -icu: interrupt-controller@1e0000 { - compatible = "marvell,cp110-icu"; - reg = <0x1e0000 0x440>; - - #interrupt-cells = <3>; - interrupt-controller; - msi-parent = <&gicp>; -}; - -node1 { - interrupt-parent = <&icu>; - interrupts = ; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.txt deleted file mode 100644 index 0ebfc952cb340..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.txt +++ /dev/null @@ -1,42 +0,0 @@ - -* Marvell ODMI for MSI support - -Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller -which can be used by on-board peripheral for MSI interrupts. - -Required properties: - -- compatible : The value here should contain: - - "marvell,ap806-odmi-controller", "marvell,odmi-controller". - -- interrupt,controller : Identifies the node as an interrupt controller. - -- msi-controller : Identifies the node as an MSI controller. - -- marvell,odmi-frames : Number of ODMI frames available. Each frame - provides a number of events. - -- reg : List of register definitions, one for each - ODMI frame. - -- marvell,spi-base : List of GIC base SPI interrupts, one for each - ODMI frame. Those SPI interrupts are 0-based, - i.e marvell,spi-base = <128> will use SPI #96. - See Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml - for details about the GIC Device Tree binding. - -Example: - - odmi: odmi@300000 { - compatible = "marvell,ap806-odmi-controller", - "marvell,odmi-controller"; - interrupt-controller; - msi-controller; - marvell,odmi-frames = <4>; - reg = <0x300000 0x4000>, - <0x304000 0x4000>, - <0x308000 0x4000>, - <0x30C000 0x4000>; - marvell,spi-base = <128>, <136>, <144>, <152>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.yaml b/Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.yaml new file mode 100644 index 0000000000000..9ec1ed4a51554 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/marvell,odmi-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell ODMI controller + +maintainers: + - Thomas Petazzoni + +description: + Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller which can + be used by on-board peripherals for MSI interrupts. + +properties: + compatible: + const: marvell,odmi-controller + + reg: + description: List of register definitions, one for each ODMI frame. + + msi-controller: true + + marvell,odmi-frames: + description: Number of ODMI frames available. Each frame provides a number of events. + $ref: /schemas/types.yaml#/definitions/uint32 + + marvell,spi-base: + description: > + List of GIC base SPI interrupts, one for each ODMI frame. Those SPI + interrupts are 0-based, i.e. marvell,spi-base = <128> will use SPI #96. + See Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml + for details. + $ref: /schemas/types.yaml#/definitions/uint32-array + +required: + - compatible + - reg + - msi-controller + - marvell,odmi-frames + - marvell,spi-base + +additionalProperties: false + +examples: + - | + msi-controller@300000 { + compatible = "marvell,odmi-controller"; + msi-controller; + marvell,odmi-frames = <4>; + reg = <0x300000 0x4000>, <0x304000 0x4000>, <0x308000 0x4000>, <0x30C000 0x4000>; + marvell,spi-base = <128>, <136>, <144>, <152>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-bridge-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-bridge-intc.yaml new file mode 100644 index 0000000000000..e1310ec653828 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-bridge-intc.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +--- +$id: http://devicetree.org/schemas/interrupt-controller/marvell,orion-bridge-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Orion SoC Bridge Interrupt Controller + +maintainers: + - Andrew Lunn + - Gregory Clement + +properties: + compatible: + const: marvell,orion-bridge-intc + + reg: + minItems: 1 + maxItems: 2 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + + interrupts: + description: Bridge interrupt of the main interrupt controller + + marvell,#interrupts: + description: Number of interrupts provided by bridge interrupt controller. + $ref: /schemas/types.yaml#/definitions/uint32 + default: 32 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - interrupts + +additionalProperties: false + +examples: + - | + interrupt-controller@20110 { + compatible = "marvell,orion-bridge-intc"; + reg = <0x20110 0x8>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts = <0>; + /* Dove bridge provides 5 interrupts */ + marvell,#interrupts = <5>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-intc.txt deleted file mode 100644 index 2c11ac76fac99..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-intc.txt +++ /dev/null @@ -1,48 +0,0 @@ -Marvell Orion SoC interrupt controllers - -* Main interrupt controller - -Required properties: -- compatible: shall be "marvell,orion-intc" -- reg: base address(es) of interrupt registers starting with CAUSE register -- interrupt-controller: identifies the node as an interrupt controller -- #interrupt-cells: number of cells to encode an interrupt source, shall be 1 - -The interrupt sources map to the corresponding bits in the interrupt -registers, i.e. -- 0 maps to bit 0 of first base address, -- 1 maps to bit 1 of first base address, -- 32 maps to bit 0 of second base address, and so on. - -Example: - intc: interrupt-controller { - compatible = "marvell,orion-intc"; - interrupt-controller; - #interrupt-cells = <1>; - /* Dove has 64 first level interrupts */ - reg = <0x20200 0x10>, <0x20210 0x10>; - }; - -* Bridge interrupt controller - -Required properties: -- compatible: shall be "marvell,orion-bridge-intc" -- reg: base address of bridge interrupt registers starting with CAUSE register -- interrupts: bridge interrupt of the main interrupt controller -- interrupt-controller: identifies the node as an interrupt controller -- #interrupt-cells: number of cells to encode an interrupt source, shall be 1 - -Optional properties: -- marvell,#interrupts: number of interrupts provided by bridge interrupt - controller, defaults to 32 if not set - -Example: - bridge_intc: interrupt-controller { - compatible = "marvell,orion-bridge-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20110 0x8>; - interrupts = <0>; - /* Dove bridge provides 5 interrupts */ - marvell,#interrupts = <5>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt deleted file mode 100644 index 0beafed502f56..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt +++ /dev/null @@ -1,36 +0,0 @@ -Marvell SEI (System Error Interrupt) Controller ------------------------------------------------ - -Marvell SEI (System Error Interrupt) controller is an interrupt -aggregator. It receives interrupts from several sources and aggregates -them to a single interrupt line (an SPI) on the parent interrupt -controller. - -This interrupt controller can handle up to 64 SEIs, a set comes from the -AP and is wired while a second set comes from the CPs by the mean of -MSIs. - -Required properties: - -- compatible: should be one of: - * "marvell,ap806-sei" -- reg: SEI registers location and length. -- interrupts: identifies the parent IRQ that will be triggered. -- #interrupt-cells: number of cells to define an SEI wired interrupt - coming from the AP, should be 1. The cell is the IRQ - number. -- interrupt-controller: identifies the node as an interrupt controller - for AP interrupts. -- msi-controller: identifies the node as an MSI controller for the CPs - interrupts. - -Example: - - sei: interrupt-controller@3f0200 { - compatible = "marvell,ap806-sei"; - reg = <0x3f0200 0x40>; - interrupts = ; - #interrupt-cells = <1>; - interrupt-controller; - msi-controller; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32-evic.txt b/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32-evic.txt deleted file mode 100644 index c3a1b37c4c358..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32-evic.txt +++ /dev/null @@ -1,67 +0,0 @@ -Microchip PIC32 Interrupt Controller -==================================== - -The Microchip PIC32 contains an Enhanced Vectored Interrupt Controller (EVIC). -It handles all internal and external interrupts. This controller exists outside -of the CPU and is the arbitrator of all interrupts (including interrupts from -the CPU itself) before they are presented to the CPU. - -External interrupts have a software configurable edge polarity. Non external -interrupts have a type and polarity that is determined by the source of the -interrupt. - -Required properties -------------------- - -- compatible: Should be "microchip,pic32mzda-evic" -- reg: Specifies physical base address and size of register range. -- interrupt-controller: Identifies the node as an interrupt controller. -- #interrupt cells: Specifies the number of cells used to encode an interrupt - source connected to this controller. The value shall be 2 and interrupt - descriptor shall have the following format: - - - - hw_irq - represents the hardware interrupt number as in the data sheet. - irq_type - is used to describe the type and polarity of an interrupt. For - internal interrupts use IRQ_TYPE_EDGE_RISING for non persistent interrupts and - IRQ_TYPE_LEVEL_HIGH for persistent interrupts. For external interrupts use - IRQ_TYPE_EDGE_RISING or IRQ_TYPE_EDGE_FALLING to select the desired polarity. - -Optional properties -------------------- -- microchip,external-irqs: u32 array of external interrupts with software - polarity configuration. This array corresponds to the bits in the INTCON - SFR. - -Example -------- - -evic: interrupt-controller@1f810000 { - compatible = "microchip,pic32mzda-evic"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1f810000 0x1000>; - microchip,external-irqs = <3 8 13 18 23>; -}; - -Each device/peripheral must request its interrupt line with the associated type -and polarity. - -Internal interrupt DTS snippet ------------------------------- - -device@1f800000 { - ... - interrupts = <113 IRQ_TYPE_LEVEL_HIGH>; - ... -}; - -External interrupt DTS snippet ------------------------------- - -device@1f800000 { - ... - interrupts = <3 IRQ_TYPE_EDGE_RISING>; - ... -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mzda-evic.yaml b/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mzda-evic.yaml new file mode 100644 index 0000000000000..74bfc42693f08 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mzda-evic.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/microchip,pic32mzda-evic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PIC32 EVIC Interrupt Controller + +maintainers: + - Cristian Birsan + +description: > + The Microchip PIC32 contains an Enhanced Vectored Interrupt Controller (EVIC). + It handles all internal and external interrupts. This controller exists + outside of the CPU and is the arbitrator of all interrupts (including + interrupts from the CPU itself) before they are presented to the CPU. + + External interrupts have a software configurable edge polarity. Non external + interrupts have a type and polarity that is determined by the source of the + interrupt. + +properties: + compatible: + items: + - const: microchip,pic32mzda-evic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + maxItems: 1 + + microchip,external-irqs: + description: + External interrupts with software polarity configuration corresponding to + the INTCON SFR bits. + $ref: /schemas/types.yaml#/definitions/uint32-array + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller@1f810000 { + compatible = "microchip,pic32mzda-evic"; + reg = <0x1f810000 0x1000>; + interrupt-controller; + #interrupt-cells = <2>; + microchip,external-irqs = <3 8 13 18 23>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt deleted file mode 100644 index 2ff3566401003..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt +++ /dev/null @@ -1,41 +0,0 @@ -NVIDIA Legacy Interrupt Controller - -All Tegra SoCs contain a legacy interrupt controller that routes -interrupts to the GIC, and also serves as a wakeup source. It is also -referred to as "ictlr", hence the name of the binding. - -The HW block exposes a number of interrupt controllers, each -implementing a set of 32 interrupts. - -Required properties: - -- compatible : should be: "nvidia,tegra-ictlr". The LIC on - subsequent SoCs remained backwards-compatible with Tegra30, so on - Tegra generations later than Tegra30 the compatible value should - include "nvidia,tegra30-ictlr". -- reg : Specifies base physical address and size of the registers. - Each controller must be described separately (Tegra20 has 4 of them, - whereas Tegra30 and later have 5). -- interrupt-controller : Identifies the node as an interrupt controller. -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value must be 3. - -Notes: - -- Because this HW ultimately routes interrupts to the GIC, the - interrupt specifier must be that of the GIC. -- Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs - are explicitly forbidden. - -Example: - - ictlr: interrupt-controller@60004000 { - compatible = "nvidia,tegra20-ictlr", "nvidia,tegra-ictlr"; - reg = <0x60004000 64>, - <0x60004100 64>, - <0x60004200 64>, - <0x60004300 64>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&intc>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.yaml b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.yaml new file mode 100644 index 0000000000000..074a873880e57 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/nvidia,tegra20-ictlr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra20 Legacy Interrupt Controller + +maintainers: + - Thierry Reding + - Jonathan Hunter + +description: > + All Tegra SoCs contain a legacy interrupt controller that routes interrupts to + the GIC, and also serves as a wakeup source. It is also referred to as + "ictlr", hence the name of the binding. + + The HW block exposes a number of interrupt controllers, each implementing a + set of 32 interrupts. + + Notes: + - Because this HW ultimately routes interrupts to the GIC, the + interrupt specifier must be that of the GIC. + - Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs + are explicitly forbidden. + +properties: + compatible: + oneOf: + - items: + - enum: + - nvidia,tegra114-ictlr + - nvidia,tegra124-ictlr + - const: nvidia,tegra30-ictlr + - enum: + - nvidia,tegra20-ictlr + - nvidia,tegra30-ictlr + + reg: + description: Each entry is a block of 32 interrupts + minItems: 4 + maxItems: 5 + + interrupt-controller: true + + '#interrupt-cells': + const: 3 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: nvidia,tegra20-ictlr + then: + properties: + reg: + maxItems: 4 + else: + properties: + reg: + minItems: 5 + +examples: + - | + interrupt-controller@60004000 { + compatible = "nvidia,tegra20-ictlr"; + reg = <0x60004000 64>, + <0x60004100 64>, + <0x60004200 64>, + <0x60004300 64>; + interrupt-controller; + #interrupt-cells = <3>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/open-pic.txt b/Documentation/devicetree/bindings/interrupt-controller/open-pic.txt deleted file mode 100644 index ccbbfdc53c727..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/open-pic.txt +++ /dev/null @@ -1,97 +0,0 @@ -* Open PIC Binding - -This binding specifies what properties must be available in the device tree -representation of an Open PIC compliant interrupt controller. This binding is -based on the binding defined for Open PIC in [1] and is a superset of that -binding. - -Required properties: - - NOTE: Many of these descriptions were paraphrased here from [1] to aid - readability. - - - compatible: Specifies the compatibility list for the PIC. The type - shall be and the value shall include "open-pic". - - - reg: Specifies the base physical address(s) and size(s) of this - PIC's addressable register space. The type shall be . - - - interrupt-controller: The presence of this property identifies the node - as an Open PIC. No property value shall be defined. - - - #interrupt-cells: Specifies the number of cells needed to encode an - interrupt source. The type shall be a and the value shall be 2. - - - #address-cells: Specifies the number of cells needed to encode an - address. The type shall be and the value shall be 0. As such, - 'interrupt-map' nodes do not have to specify a parent unit address. - -Optional properties: - - - pic-no-reset: The presence of this property indicates that the PIC - shall not be reset during runtime initialization. No property value shall - be defined. The presence of this property also mandates that any - initialization related to interrupt sources shall be limited to sources - explicitly referenced in the device tree. - -* Interrupt Specifier Definition - - Interrupt specifiers consists of 2 cells encoded as - follows: - - - <1st-cell>: The interrupt-number that identifies the interrupt source. - - - <2nd-cell>: The level-sense information, encoded as follows: - 0 = low-to-high edge triggered - 1 = active low level-sensitive - 2 = active high level-sensitive - 3 = high-to-low edge triggered - -* Examples - -Example 1: - - /* - * An Open PIC interrupt controller - */ - mpic: pic@40000 { - // This is an interrupt controller node. - interrupt-controller; - - // No address cells so that 'interrupt-map' nodes which reference - // this Open PIC node do not need a parent address specifier. - #address-cells = <0>; - - // Two cells to encode interrupt sources. - #interrupt-cells = <2>; - - // Offset address of 0x40000 and size of 0x40000. - reg = <0x40000 0x40000>; - - // Compatible with Open PIC. - compatible = "open-pic"; - - // The PIC shall not be reset. - pic-no-reset; - }; - -Example 2: - - /* - * An interrupt generating device that is wired to an Open PIC. - */ - serial0: serial@4500 { - // Interrupt source '42' that is active high level-sensitive. - // Note that there are only two cells as specified in the interrupt - // parent's '#interrupt-cells' property. - interrupts = <42 2>; - - // The interrupt controller that this device is wired to. - interrupt-parent = <&mpic>; - }; - -* References - -[1] Devicetree Specification - (https://www.devicetree.org/specifications/) - diff --git a/Documentation/devicetree/bindings/interrupt-controller/opencores,or1k-pic.txt b/Documentation/devicetree/bindings/interrupt-controller/opencores,or1k-pic.txt deleted file mode 100644 index 55c04faa3f3fe..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/opencores,or1k-pic.txt +++ /dev/null @@ -1,23 +0,0 @@ -OpenRISC 1000 Programmable Interrupt Controller - -Required properties: - -- compatible : should be "opencores,or1k-pic-level" for variants with - level triggered interrupt lines, "opencores,or1k-pic-edge" for variants with - edge triggered interrupt lines or "opencores,or1200-pic" for machines - with the non-spec compliant or1200 type implementation. - - "opencores,or1k-pic" is also provided as an alias to "opencores,or1200-pic", - but this is only for backwards compatibility. - -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value shall be 1. - -Example: - -intc: interrupt-controller { - compatible = "opencores,or1k-pic-level"; - interrupt-controller; - #interrupt-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/opencores,or1k-pic.yaml b/Documentation/devicetree/bindings/interrupt-controller/opencores,or1k-pic.yaml new file mode 100644 index 0000000000000..995b68c3aed45 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/opencores,or1k-pic.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/opencores,or1k-pic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OpenRISC 1000 Programmable Interrupt Controller + +maintainers: + - Stefan Kristiansson + +properties: + compatible: + enum: + - opencores,or1k-pic-level + - opencores,or1k-pic-edge + - opencores,or1200-pic + - opencores,or1k-pic + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + +required: + - compatible + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller { + compatible = "opencores,or1k-pic-level"; + interrupt-controller; + #interrupt-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt b/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt deleted file mode 100644 index caec07cc71496..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt +++ /dev/null @@ -1,22 +0,0 @@ -Open Multi-Processor Interrupt Controller - -Required properties: - -- compatible : This should be "openrisc,ompic" -- reg : Specifies base physical address and size of the register space. The - size is based on the number of cores the controller has been configured - to handle, this should be set to 8 bytes per cpu core. -- interrupt-controller : Identifies the node as an interrupt controller. -- #interrupt-cells : This should be set to 0 as this will not be an irq - parent. -- interrupts : Specifies the interrupt line to which the ompic is wired. - -Example: - -ompic: interrupt-controller@98000000 { - compatible = "openrisc,ompic"; - reg = <0x98000000 16>; - interrupt-controller; - #interrupt-cells = <0>; - interrupts = <1>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.yaml b/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.yaml new file mode 100644 index 0000000000000..4efbfba3aa6b5 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/openrisc,ompic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Open Multi-Processor Interrupt Controller + +maintainers: + - Stafford Horne + +properties: + compatible: + items: + - const: openrisc,ompic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 0 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - interrupts + +additionalProperties: false + +examples: + - | + interrupt-controller@98000000 { + compatible = "openrisc,ompic"; + reg = <0x98000000 16>; + interrupt-controller; + #interrupt-cells = <0>; + interrupts = <1>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/qca,ar7100-cpu-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qca,ar7100-cpu-intc.yaml new file mode 100644 index 0000000000000..ab32a91af4c4c --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/qca,ar7100-cpu-intc.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/qca,ar7100-cpu-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Atheros ath79 CPU interrupt controller + +maintainers: + - Alban Bedel + +description: + On most SoC the IRQ controller need to flush the DDR FIFO before running the + interrupt handler of some devices. This is configured using the + qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties. + +properties: + compatible: + oneOf: + - items: + - const: qca,ar9132-cpu-intc + - const: qca,ar7100-cpu-intc + - items: + - const: qca,ar7100-cpu-intc + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + + qca,ddr-wb-channel-interrupts: + description: List of interrupts needing a write buffer flush + $ref: /schemas/types.yaml#/definitions/uint32-array + + qca,ddr-wb-channels: + description: List of write buffer channel phandles for each interrupt + $ref: /schemas/types.yaml#/definitions/phandle-array + +required: + - compatible + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller { + compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc"; + + interrupt-controller; + #interrupt-cells = <1>; + + qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>; + qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>, + <&ddr_ctrl 0>, <&ddr_ctrl 1>; + }; + + ddr_ctrl: memory-controller { + #qca,ddr-wb-channel-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/qca,ar7100-misc-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qca,ar7100-misc-intc.yaml new file mode 100644 index 0000000000000..ae813189f5ab6 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/qca,ar7100-misc-intc.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/qca,ar7100-misc-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller + +maintainers: + - Alban Bedel + - Alexander Couzens + +description: + The Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller is a secondary + controller for lower priority interrupts. + +properties: + compatible: + oneOf: + - items: + - const: qca,ar9132-misc-intc + - const: qca,ar7100-misc-intc + - const: qca,ar7240-misc-intc + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - "#interrupt-cells" + +examples: + - | + interrupt-controller@18060010 { + compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc"; + reg = <0x18060010 0x4>; + interrupts = <6>; + interrupt-controller; + #interrupt-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-cpu-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-cpu-intc.txt deleted file mode 100644 index aabce7810d29c..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-cpu-intc.txt +++ /dev/null @@ -1,44 +0,0 @@ -Binding for Qualcomm Atheros AR7xxx/AR9XXX CPU interrupt controller - -On most SoC the IRQ controller need to flush the DDR FIFO before running -the interrupt handler of some devices. This is configured using the -qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties. - -Required Properties: - -- compatible: has to be "qca,-cpu-intc", "qca,ar7100-cpu-intc" - as fallback -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode interrupt - source, should be 1 for intc - -Please refer to interrupts.txt in this directory for details of the common -Interrupt Controllers bindings used by client devices. - -Optional Properties: - -- qca,ddr-wb-channel-interrupts: List of the interrupts needing a write - buffer flush -- qca,ddr-wb-channels: List of phandles to the write buffer channels for - each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt - default to the entry's index. - -Example: - - interrupt-controller { - compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc"; - - interrupt-controller; - #interrupt-cells = <1>; - - qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>; - qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>, - <&ddr_ctrl 0>, <&ddr_ctrl 1>; - }; - - ... - - ddr_ctrl: memory-controller@18000000 { - ... - #qca,ddr-wb-channel-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt deleted file mode 100644 index ad70006c1848f..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt +++ /dev/null @@ -1,45 +0,0 @@ -Binding for Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller - -The MISC interrupt controller is a secondary controller for lower priority -interrupt. - -Required Properties: -- compatible: has to be "qca,-cpu-intc", "qca,ar7100-misc-intc" or - "qca,-cpu-intc", "qca,ar7240-misc-intc" -- reg: Base address and size of the controllers memory area -- interrupts: Interrupt specifier for the controllers interrupt. -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode interrupt - source, should be 1 - -Compatible fallback depends on the SoC. Use ar7100 for ar71xx and ar913x, -use ar7240 for all other SoCs. - -Please refer to interrupts.txt in this directory for details of the common -Interrupt Controllers bindings used by client devices. - -Example: - - interrupt-controller@18060010 { - compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc"; - reg = <0x18060010 0x4>; - - interrupt-parent = <&cpuintc>; - interrupts = <6>; - - interrupt-controller; - #interrupt-cells = <1>; - }; - -Another example: - - interrupt-controller@18060010 { - compatible = "qca,ar9331-misc-intc", qca,ar7240-misc-intc"; - reg = <0x18060010 0x4>; - - interrupt-parent = <&cpuintc>; - interrupts = <6>; - - interrupt-controller; - #interrupt-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 3dfe425909d1e..ffc4768bad065 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -70,6 +70,7 @@ properties: - sophgo,cv1812h-plic - sophgo,sg2002-plic - sophgo,sg2042-plic + - sophgo,sg2044-plic - thead,th1520-plic - const: thead,c900-plic - items: diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,arc700-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/snps,arc700-intc.txt deleted file mode 100644 index 9a5d562435ea7..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/snps,arc700-intc.txt +++ /dev/null @@ -1,24 +0,0 @@ -* ARC700 incore Interrupt Controller - - The core interrupt controller provides 32 prioritised interrupts (2 levels) - to ARC700 core. - -Properties: - -- compatible: "snps,arc700-intc" -- interrupt-controller: This is an interrupt controller. -- #interrupt-cells: Must be <1>. - - Single Cell "interrupts" property of a device specifies the IRQ number - between 0 to 31 - - intc accessed via the special ARC AUX register interface, hence "reg" property - is not specified. - -Example: - - intc: interrupt-controller { - compatible = "snps,arc700-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,arc700-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/snps,arc700-intc.yaml new file mode 100644 index 0000000000000..000a734d997cf --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/snps,arc700-intc.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/snps,arc700-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARC700 incore Interrupt Controller + +maintainers: + - Vineet Gupta + +description: > + The core interrupt controller provides 32 prioritized interrupts (2 levels) + to ARC700 core. + + intc accessed via the special ARC AUX register interface, hence "reg" property + is not specified. + +properties: + compatible: + const: snps,arc700-intc + + interrupt-controller: true + + '#interrupt-cells': + description: An interrupt number 0-31 + const: 1 + +required: + - compatible + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller { + compatible = "snps,arc700-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt deleted file mode 100644 index a5c1db95b3ecb..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt +++ /dev/null @@ -1,46 +0,0 @@ -* ARC-HS Interrupt Distribution Unit - - This optional 2nd level interrupt controller can be used in SMP configurations - for dynamic IRQ routing, load balancing of common/external IRQs towards core - intc. - -Properties: - -- compatible: "snps,archs-idu-intc" -- interrupt-controller: This is an interrupt controller. -- #interrupt-cells: Must be <1> or <2>. - - Value of the first cell specifies the "common" IRQ from peripheral to IDU. - Number N of the particular interrupt line of IDU corresponds to the line N+24 - of the core interrupt controller. - - The (optional) second cell specifies any of the following flags: - - bits[3:0] trigger type and level flags - 1 = low-to-high edge triggered - 2 = NOT SUPPORTED (high-to-low edge triggered) - 4 = active high level-sensitive <<< DEFAULT - 8 = NOT SUPPORTED (active low level-sensitive) - When no second cell is specified, the interrupt is assumed to be level - sensitive. - - The interrupt controller is accessed via the special ARC AUX register - interface, hence "reg" property is not specified. - -Example: - core_intc: core-interrupt-controller { - compatible = "snps,archs-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - - idu_intc: idu-interrupt-controller { - compatible = "snps,archs-idu-intc"; - interrupt-controller; - interrupt-parent = <&core_intc>; - #interrupt-cells = <1>; - }; - - some_device: serial@c0fc1000 { - interrupt-parent = <&idu_intc>; - interrupts = <0>; /* upstream idu IRQ #24 */ - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.yaml new file mode 100644 index 0000000000000..286a964f23e18 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/snps,archs-idu-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARC-HS Interrupt Distribution Unit + +maintainers: + - Vineet Gupta + +description: > + ARC-HS Interrupt Distribution Unit is an optional 2nd level interrupt + controller which can be used in SMP configurations for dynamic IRQ routing, + load balancing of common/external IRQs towards core intc. + + The interrupt controller is accessed via the special ARC AUX register + interface, hence "reg" property is not specified. + +properties: + compatible: + const: snps,archs-idu-intc + + interrupt-controller: true + + '#interrupt-cells': + description: | + Number of interrupt specifier cells: + - 1: only a common IRQ is specified. + - 2: a second cell encodes trigger type and level flags: + 1 = low-to-high edge triggered + 4 = active high level-sensitive (default) + enum: [1, 2] + +required: + - compatible + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller { + compatible = "snps,archs-idu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,archs-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/snps,archs-intc.txt deleted file mode 100644 index 69f326d6a5ad2..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/snps,archs-intc.txt +++ /dev/null @@ -1,22 +0,0 @@ -* ARC-HS incore Interrupt Controller (Provided by cores implementing ARCv2 ISA) - -Properties: - -- compatible: "snps,archs-intc" -- interrupt-controller: This is an interrupt controller. -- #interrupt-cells: Must be <1>. - - Single Cell "interrupts" property of a device specifies the IRQ number - between 16 to 256 - - intc accessed via the special ARC AUX register interface, hence "reg" property - is not specified. - -Example: - - intc: interrupt-controller { - compatible = "snps,archs-intc"; - interrupt-controller; - #interrupt-cells = <1>; - interrupts = <16 17 18 19 20 21 22 23 24 25>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,archs-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/snps,archs-intc.yaml new file mode 100644 index 0000000000000..9d248ef7fe3d8 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/snps,archs-intc.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/snps,archs-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARC-HS incore Interrupt Controller + +maintainers: + - Vineet Gupta + +description: + ARC-HS incore Interrupt Controller provided by cores implementing ARCv2 ISA. + intc accessed via the special ARC AUX register interface, hence "reg" property + is not specified. + +properties: + compatible: + const: snps,archs-intc + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + + interrupts: + description: List of IRQ numbers between 16 and 256 + items: + items: + - minimum: 16 + maximum: 256 + +required: + - compatible + - interrupt-controller + - '#interrupt-cells' + - interrupts + +additionalProperties: false + +examples: + - | + interrupt-controller { + compatible = "snps,archs-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupts = <16>, <17>, <18>, <19>, <20>, <21>, <22>, <23>, <24>, <25>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt deleted file mode 100644 index 2db59df9408f4..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt +++ /dev/null @@ -1,43 +0,0 @@ -Synopsys DesignWare APB interrupt controller (dw_apb_ictl) - -Synopsys DesignWare provides interrupt controller IP for APB known as -dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with -APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt -controller in some SoCs, e.g. Hisilicon SD5203. - -Required properties: -- compatible: shall be "snps,dw-apb-ictl" -- reg: physical base address of the controller and length of memory mapped - region starting with ENABLE_LOW register -- interrupt-controller: identifies the node as an interrupt controller -- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1 - -Additional required property when it's used as secondary interrupt controller: -- interrupts: interrupt reference to primary interrupt controller - -The interrupt sources map to the corresponding bits in the interrupt -registers, i.e. -- 0 maps to bit 0 of low interrupts, -- 1 maps to bit 1 of low interrupts, -- 32 maps to bit 0 of high interrupts, -- 33 maps to bit 1 of high interrupts, -- (optional) fast interrupts start at 64. - -Example: - /* dw_apb_ictl is used as secondary interrupt controller */ - aic: interrupt-controller@3000 { - compatible = "snps,dw-apb-ictl"; - reg = <0x3000 0xc00>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - - /* dw_apb_ictl is used as primary interrupt controller */ - vic: interrupt-controller@10130000 { - compatible = "snps,dw-apb-ictl"; - reg = <0x10130000 0x1000>; - interrupt-controller; - #interrupt-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.yaml b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.yaml new file mode 100644 index 0000000000000..6b59b600a0377 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/snps,dw-apb-ictl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare APB interrupt controller + +maintainers: + - Sebastian Hesselbarth + - Zhen Lei + +description: + Synopsys DesignWare provides interrupt controller IP for APB known as + dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs + with APB bus, e.g. Marvell Armada 1500. It can also be used as primary + interrupt controller in some SoCs, e.g. Hisilicon SD5203. + +properties: + compatible: + const: snps,dw-apb-ictl + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + + interrupts: + maxItems: 1 + description: > + Interrupt input connected to the primary interrupt controller when used + as a secondary controller. The interrupt specifier maps to bits in the + low and high interrupt registers (0⇒bit 0 low, 1⇒bit 1 low, 32⇒bit 0 high, + 33⇒bit 1 high, fast interrupts start at 64). + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + #include + + interrupt-controller@3000 { + compatible = "snps,dw-apb-ictl"; + reg = <0x3000 0xc00>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts = ; + }; + - | + interrupt-controller@10130000 { + compatible = "snps,dw-apb-ictl"; + reg = <0x10130000 0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml index e1ffd55fa7bf8..f6b8b1d92f799 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml @@ -18,7 +18,9 @@ allOf: properties: compatible: - const: sophgo,sg2042-msi + enum: + - sophgo,sg2042-msi + - sophgo,sg2044-msi reg: items: diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,spear300-shirq.yaml b/Documentation/devicetree/bindings/interrupt-controller/st,spear300-shirq.yaml new file mode 100644 index 0000000000000..27d36173366ad --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/st,spear300-shirq.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/st,spear300-shirq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SPEAr3xx Shared IRQ controller + +maintainers: + - Viresh Kumar + - Shiraz Hashim + +description: | + SPEAr3xx architecture includes shared/multiplexed irqs for certain set of + devices. The multiplexor provides a single interrupt to parent interrupt + controller (VIC) on behalf of a group of devices. + + There can be multiple groups available on SPEAr3xx variants but not exceeding + 4. The number of devices in a group can differ, further they may share same + set of status/mask registers spanning across different bit masks. Also in some + cases the group may not have enable or other registers. This makes software + little complex. + + A single node in the device tree is used to describe the shared interrupt + multiplexer (one node for all groups). A group in the interrupt controller + shares config/control registers with other groups. For example, a 32-bit + interrupt enable/disable config register can accommodate up to 4 interrupt + groups. + +properties: + compatible: + enum: + - st,spear300-shirq + - st,spear310-shirq + - st,spear320-shirq + + reg: + maxItems: 1 + + '#interrupt-cells': + const: 1 + + interrupt-controller: true + + interrupts: + description: Interrupt specifier array for SHIRQ groups + minItems: 1 + maxItems: 4 + +required: + - compatible + - reg + - '#interrupt-cells' + - interrupt-controller + - interrupts + +additionalProperties: false + +examples: + - | + interrupt-controller@b3000000 { + compatible = "st,spear320-shirq"; + reg = <0xb3000000 0x1000>; + interrupts = <28 29 30 1>; + #interrupt-cells = <1>; + interrupt-controller; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,spear3xx-shirq.txt b/Documentation/devicetree/bindings/interrupt-controller/st,spear3xx-shirq.txt deleted file mode 100644 index a407c499b3cc7..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/st,spear3xx-shirq.txt +++ /dev/null @@ -1,44 +0,0 @@ -* SPEAr Shared IRQ layer (shirq) - -SPEAr3xx architecture includes shared/multiplexed irqs for certain set -of devices. The multiplexor provides a single interrupt to parent -interrupt controller (VIC) on behalf of a group of devices. - -There can be multiple groups available on SPEAr3xx variants but not -exceeding 4. The number of devices in a group can differ, further they -may share same set of status/mask registers spanning across different -bit masks. Also in some cases the group may not have enable or other -registers. This makes software little complex. - -A single node in the device tree is used to describe the shared -interrupt multiplexor (one node for all groups). A group in the -interrupt controller shares config/control registers with other groups. -For example, a 32-bit interrupt enable/disable config register can -accommodate up to 4 interrupt groups. - -Required properties: - - compatible: should be, either of - - "st,spear300-shirq" - - "st,spear310-shirq" - - "st,spear320-shirq" - - interrupt-controller: Identifies the node as an interrupt controller. - - #interrupt-cells: should be <1> which basically contains the offset - (starting from 0) of interrupts for all the groups. - - reg: Base address and size of shirq registers. - - interrupts: The list of interrupts generated by the groups which are - then connected to a parent interrupt controller. Each group is - associated with one of the interrupts, hence number of interrupts (to - parent) is equal to number of groups. The format of the interrupt - specifier depends in the interrupt parent controller. - -Example: - -The following is an example from the SPEAr320 SoC dtsi file. - -shirq: interrupt-controller@b3000000 { - compatible = "st,spear320-shirq"; - reg = <0xb3000000 0x1000>; - interrupts = <28 29 30 1>; - #interrupt-cells = <1>; - interrupt-controller; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/technologic,ts4800-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/technologic,ts4800-irqc.yaml new file mode 100644 index 0000000000000..f1a15d725cd66 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/technologic,ts4800-irqc.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/technologic,ts4800-irqc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TS-4800 FPGA Interrupt Controller + +maintainers: + - Damien Riegel + +description: + TS-4800 FPGA has an internal interrupt controller. When one of the interrupts + is triggered, the SoC is notified, usually using a GPIO as parent interrupt + source. + +properties: + compatible: + const: technologic,ts4800-irqc + + reg: + maxItems: 1 + + '#interrupt-cells': + const: 1 + + interrupt-controller: true + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - interrupts + +additionalProperties: false + +examples: + - | + interrupt-controller@1000 { + compatible = "technologic,ts4800-irqc"; + reg = <0x1000 0x80>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts = <10>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/technologic,ts4800.txt b/Documentation/devicetree/bindings/interrupt-controller/technologic,ts4800.txt deleted file mode 100644 index 341ae5909333f..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/technologic,ts4800.txt +++ /dev/null @@ -1,14 +0,0 @@ -TS-4800 FPGA interrupt controller - -TS-4800 FPGA has an internal interrupt controller. When one of the -interrupts is triggered, the SoC is notified, usually using a GPIO as -parent interrupt source. - -Required properties: -- compatible: should be "technologic,ts4800-irqc" -- interrupt-controller: identifies the node as an interrupt controller -- reg: physical base address of the controller and length of memory mapped - region -- #interrupt-cells: specifies the number of cells needed to encode an interrupt - source, should be 1. -- interrupts: specifies the interrupt line in the interrupt-parent controller diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml index 065f2544b63b0..d6fb08a54167f 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml @@ -14,6 +14,7 @@ properties: items: - enum: - sophgo,sg2042-aclint-mswi + - sophgo,sg2044-aclint-mswi - const: thead,c900-aclint-mswi reg: diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,cp-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ti,cp-intc.txt deleted file mode 100644 index 597e8a089fe43..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/ti,cp-intc.txt +++ /dev/null @@ -1,27 +0,0 @@ -* TI Common Platform Interrupt Controller - -Common Platform Interrupt Controller (cp_intc) is used on -OMAP-L1x SoCs and can support several configurable number -of interrupts. - -Main node required properties: - -- compatible : should be: - "ti,cp-intc" -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The type shall be a and the value shall be 1. - - The cell contains the interrupt number in the range [0-128]. -- ti,intc-size: Number of interrupts handled by the interrupt controller. -- reg: physical base address and size of the intc registers map. - -Example: - - intc: interrupt-controller@1 { - compatible = "ti,cp-intc"; - interrupt-controller; - #interrupt-cells = <1>; - ti,intc-size = <101>; - reg = <0xfffee000 0x2000>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,cp-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/ti,cp-intc.yaml new file mode 100644 index 0000000000000..77d018d20f9fe --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,cp-intc.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/ti,cp-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI Common Platform Interrupt Controller + +maintainers: + - Bartosz Golaszewski + +description: + Common Platform Interrupt Controller (cp_intc) is used on OMAP-L1x SoCs and + can support several configurable number of interrupts. + +properties: + compatible: + const: ti,cp-intc + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + description: Encodes an interrupt number in the range 0–128. + + ti,intc-size: + description: Number of interrupts handled by the interrupt controller. + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - ti,intc-size + +additionalProperties: false + +examples: + - | + interrupt-controller@fffee000 { + compatible = "ti,cp-intc"; + reg = <0xfffee000 0x2000>; + interrupt-controller; + #interrupt-cells = <1>; + ti,intc-size = <101>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.txt b/Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.txt deleted file mode 100644 index 5f94d7739d8d2..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.txt +++ /dev/null @@ -1,36 +0,0 @@ -Keystone 2 IRQ controller IP - -On Keystone SOCs, DSP cores can send interrupts to ARM -host using the IRQ controller IP. It provides 28 IRQ signals to ARM. -The IRQ handler running on HOST OS can identify DSP signal source by -analyzing SRCCx bits in IPCARx registers. This is one of the component -used by the IPC mechanism used on Keystone SOCs. - -Required Properties: -- compatible: should be "ti,keystone-irq" -- ti,syscon-dev : phandle and offset pair. The phandle to syscon used to - access device control registers and the offset inside - device control registers range. -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode interrupt - source should be 1. -- interrupts: interrupt reference to primary interrupt controller - -Please refer to interrupts.txt in this directory for details of the common -Interrupt Controllers bindings used by client devices. - -Example: - kirq0: keystone_irq0@26202a0 { - compatible = "ti,keystone-irq"; - ti,syscon-dev = <&devctrl 0x2a0>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - }; - - dsp0: dsp0 { - compatible = "linux,rproc-user"; - ... - interrupt-parent = <&kirq0>; - interrupts = <10 2>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.yaml b/Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.yaml new file mode 100644 index 0000000000000..27d448d1786aa --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ti,keystone-irq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Keystone 2 IRQ controller IP + +maintainers: + - Grygorii Strashko + +description: + On Keystone SOCs, DSP cores can send interrupts to ARM host using the IRQ + controller IP. It provides 28 IRQ signals to ARM. The IRQ handler running on + HOST OS can identify DSP signal source by analyzing SRCCx bits in IPCARx + registers. This is one of the component used by the IPC mechanism used on + Keystone SOCs. + +properties: + compatible: + const: ti,keystone-irq + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + + interrupts: + maxItems: 1 + + ti,syscon-dev: + description: Phandle and offset to syscon device + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to syscon device control registers + - description: Offset to control register + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - interrupts + - ti,syscon-dev + +additionalProperties: false + +examples: + - | + #include + + interrupt-controller@2a0 { + compatible = "ti,keystone-irq"; + reg = <0x2a0 0x4>; + ti,syscon-dev = <&devctrl 0x2a0>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,omap-intc-irq.txt b/Documentation/devicetree/bindings/interrupt-controller/ti,omap-intc-irq.txt deleted file mode 100644 index 38ce5d0377229..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/ti,omap-intc-irq.txt +++ /dev/null @@ -1,28 +0,0 @@ -Omap2/3 intc controller - -On TI omap2 and 3 the intc interrupt controller can provide -96 or 128 IRQ signals to the ARM host depending on the SoC. - -Required Properties: -- compatible: should be one of - "ti,omap2-intc" - "ti,omap3-intc" - "ti,dm814-intc" - "ti,dm816-intc" - "ti,am33xx-intc" - -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode interrupt - source, should be 1 for intc -- interrupts: interrupt reference to primary interrupt controller - -Please refer to interrupts.txt in this directory for details of the common -Interrupt Controllers bindings used by client devices. - -Example: - intc: interrupt-controller@48200000 { - compatible = "ti,omap3-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x48200000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,omap-intc-irq.yaml b/Documentation/devicetree/bindings/interrupt-controller/ti,omap-intc-irq.yaml new file mode 100644 index 0000000000000..cb118180621f9 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,omap-intc-irq.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/ti,omap-intc-irq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI OMAP Interrupt Controller + +maintainers: + - Tony Lindgren + +description: + On TI omap2 and 3 the intc interrupt controller can provide 96 or 128 IRQ + signals to the ARM host depending on the SoC. + +properties: + compatible: + enum: + - ti,omap2-intc + - ti,omap3-intc + - ti,dm814-intc + - ti,dm816-intc + - ti,am33xx-intc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller@48200000 { + compatible = "ti,omap3-intc"; + reg = <0x48200000 0x1000>; + interrupts = <32>; + interrupt-controller; + #interrupt-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,omap2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ti,omap2-intc.txt deleted file mode 100644 index f2583e6ec0609..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/ti,omap2-intc.txt +++ /dev/null @@ -1,27 +0,0 @@ -* OMAP Interrupt Controller - -OMAP2/3 are using a TI interrupt controller that can support several -configurable number of interrupts. - -Main node required properties: - -- compatible : should be: - "ti,omap2-intc" -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The type shall be a and the value shall be 1. - - The cell contains the interrupt number in the range [0-128]. -- ti,intc-size: Number of interrupts handled by the interrupt controller. -- reg: physical base address and size of the intc registers map. - -Example: - - intc: interrupt-controller@1 { - compatible = "ti,omap2-intc"; - interrupt-controller; - #interrupt-cells = <1>; - ti,intc-size = <96>; - reg = <0x48200000 0x1000>; - }; - diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu.txt b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu.txt deleted file mode 100644 index 422d6908f8b2a..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu.txt +++ /dev/null @@ -1,31 +0,0 @@ -TI OMAP4 Wake-up Generator - -All TI OMAP4/5 (and their derivatives) an interrupt controller that -routes interrupts to the GIC, and also serves as a wakeup source. It -is also referred to as "WUGEN-MPU", hence the name of the binding. - -Required properties: - -- compatible : should contain at least "ti,omap4-wugen-mpu" or - "ti,omap5-wugen-mpu" -- reg : Specifies base physical address and size of the registers. -- interrupt-controller : Identifies the node as an interrupt controller. -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value must be 3. - -Notes: - -- Because this HW ultimately routes interrupts to the GIC, the - interrupt specifier must be that of the GIC. -- Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs - are explicitly forbidden. - -Example: - - wakeupgen: interrupt-controller@48281000 { - compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x48281000 0x1000>; - interrupt-parent = <&gic>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu.yaml b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu.yaml new file mode 100644 index 0000000000000..6e3d6e6d9e073 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/ti,omap4-wugen-mpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI OMAP4 Wake-up Generator + +maintainers: + - Krzysztof Kozlowski + +description: > + All TI OMAP4/5 (and their derivatives) are interrupt controllers that route + interrupts to the GIC, and also serve as wakeup sources. They are also + referred to as "WUGEN-MPU", hence the name of the binding. + + Notes: + + - Because this HW ultimately routes interrupts to the GIC, the interrupt + specifier must be that of the GIC. + - Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs are + explicitly forbidden. + +properties: + compatible: + oneOf: + - items: + - const: ti,omap5-wugen-mpu + - const: ti,omap4-wugen-mpu + - const: ti,omap4-wugen-mpu + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 3 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller@48281000 { + compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; + reg = <0x48281000 0x1000>; + interrupt-controller; + #interrupt-cells = <3>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/via,vt8500-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/via,vt8500-intc.txt deleted file mode 100644 index 0a4ce1051b025..0000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/via,vt8500-intc.txt +++ /dev/null @@ -1,16 +0,0 @@ -VIA/Wondermedia VT8500 Interrupt Controller ------------------------------------------------------ - -Required properties: -- compatible : "via,vt8500-intc" -- reg : Should contain 1 register ranges(address and length) -- #interrupt-cells : should be <1> - -Example: - - intc: interrupt-controller@d8140000 { - compatible = "via,vt8500-intc"; - interrupt-controller; - reg = <0xd8140000 0x10000>; - #interrupt-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/via,vt8500-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/via,vt8500-intc.yaml new file mode 100644 index 0000000000000..bc14c74bf7d57 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/via,vt8500-intc.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/via,vt8500-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: VIA and WonderMedia SoCs Interrupt Controller + +description: + This is the interrupt controller used in single-core ARM SoCs made by + VIA and WonderMedia (up to and including WM8950). Each block handles + up to 64 interrupt sources (level or edge triggered) and can generate + up to 8 interrupts to its parent when used in a chained configuration. + +maintainers: + - Alexey Charkov + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + const: via,vt8500-intc + + reg: + maxItems: 1 + + interrupts: + items: + - description: + Interrupt number raised by the IRQ0 output of this controller + Only used if this controller is chained + - description: + Interrupt number raised by the IRQ1 output of this controller + Only used if this controller is chained + - description: + Interrupt number raised by the IRQ2 output of this controller + Only used if this controller is chained + - description: + Interrupt number raised by the IRQ3 output of this controller + Only used if this controller is chained + - description: + Interrupt number raised by the IRQ4 output of this controller + Only used if this controller is chained + - description: + Interrupt number raised by the IRQ5 output of this controller + Only used if this controller is chained + - description: + Interrupt number raised by the IRQ6 output of this controller + Only used if this controller is chained + - description: + Interrupt number raised by the IRQ7 output of this controller + Only used if this controller is chained + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller@d8140000 { + compatible = "via,vt8500-intc"; + interrupt-controller; + reg = <0xd8140000 0x10000>; + #interrupt-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml index ea6b0f5f24de7..75750c64157c8 100644 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml @@ -74,6 +74,7 @@ properties: - mediatek,mt2712-m4u # generation two - mediatek,mt6779-m4u # generation two - mediatek,mt6795-m4u # generation two + - mediatek,mt6893-iommu-mm # generation two - mediatek,mt8167-m4u # generation two - mediatek,mt8173-m4u # generation two - mediatek,mt8183-m4u # generation two @@ -131,6 +132,7 @@ properties: dt-binding/memory/mt2712-larb-port.h for mt2712, dt-binding/memory/mt6779-larb-port.h for mt6779, dt-binding/memory/mt6795-larb-port.h for mt6795, + dt-binding/memory/mediatek,mt6893-memory-port.h for mt6893, dt-binding/memory/mt8167-larb-port.h for mt8167, dt-binding/memory/mt8173-larb-port.h for mt8173, dt-binding/memory/mt8183-larb-port.h for mt8183, @@ -157,6 +159,7 @@ allOf: - mediatek,mt2701-m4u - mediatek,mt2712-m4u - mediatek,mt6795-m4u + - mediatek,mt6893-iommu-mm - mediatek,mt8173-m4u - mediatek,mt8186-iommu-mm - mediatek,mt8188-iommu-vdo @@ -173,6 +176,7 @@ allOf: properties: compatible: enum: + - mediatek,mt6893-iommu-mm - mediatek,mt8186-iommu-mm - mediatek,mt8188-iommu-vdo - mediatek,mt8188-iommu-vpp diff --git a/Documentation/devicetree/bindings/leds/backlight/ti,lp8864.yaml b/Documentation/devicetree/bindings/leds/backlight/ti,lp8864.yaml new file mode 100644 index 0000000000000..d44232d462bde --- /dev/null +++ b/Documentation/devicetree/bindings/leds/backlight/ti,lp8864.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/backlight/ti,lp8864.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments - LP8864/LP8866 4/6-Channel LED Driver family + +maintainers: + - Andrew Davis + - Alexander Sverdlin + +description: | + LP8866-Q1, LP8866S-Q1, LP8864-Q1, LP8864S-Q1 are display LED-backlight drivers + with 4/6 channels. LED brightness can be controlled globally through the I2C + interface or PWM input. + + For more product information please see the links below: + https://www.ti.com/product/LP8864-Q1 + https://www.ti.com/product/LP8864S-Q1 + https://www.ti.com/product/LP8866-Q1 + https://www.ti.com/product/LP8866S-Q1 + +properties: + compatible: + const: ti,lp8864 + + reg: + maxItems: 1 + description: I2C slave address + + enable-gpios: + maxItems: 1 + description: GPIO pin to enable (active high) / disable the device + + vled-supply: + description: LED supply + + led: + type: object + $ref: common.yaml# + properties: + function: true + color: true + label: true + linux,default-trigger: true + + additionalProperties: false + +required: + - compatible + - reg + - led + +additionalProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + led-controller@3a { + compatible = "ti,lp8864"; + reg = <0x3a>; + enable-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + vled-supply = <&vbatt>; + + led { + function = LED_FUNCTION_BACKLIGHT; + color = ; + linux,default-trigger = "backlight"; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/media/amlogic,c3-isp.yaml b/Documentation/devicetree/bindings/media/amlogic,c3-isp.yaml new file mode 100644 index 0000000000000..123bf462f098c --- /dev/null +++ b/Documentation/devicetree/bindings/media/amlogic,c3-isp.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/amlogic,c3-isp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic C3 Image Signal Processing Unit + +maintainers: + - Keke Li + +description: + Amlogic ISP is the RAW image processing module + and supports three channels image output. + +properties: + compatible: + enum: + - amlogic,c3-isp + + reg: + maxItems: 1 + + reg-names: + items: + - const: isp + + power-domains: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: vapb + - const: isp0 + + interrupts: + maxItems: 1 + + port: + $ref: /schemas/graph.yaml#/properties/port + description: input port node. + +required: + - compatible + - reg + - reg-names + - power-domains + - clocks + - clock-names + - interrupts + - port + +additionalProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + isp: isp@ff000000 { + compatible = "amlogic,c3-isp"; + reg = <0x0 0xff000000 0x0 0xf000>; + reg-names = "isp"; + power-domains = <&pwrc PWRC_C3_ISP_TOP_ID>; + clocks = <&clkc_periphs CLKID_VAPB>, + <&clkc_periphs CLKID_ISP0>; + clock-names = "vapb", "isp0"; + assigned-clocks = <&clkc_periphs CLKID_VAPB>, + <&clkc_periphs CLKID_ISP0>; + assigned-clock-rates = <0>, <400000000>; + interrupts = ; + + port { + c3_isp_in: endpoint { + remote-endpoint = <&c3_adap_out>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/media/amlogic,c3-mipi-adapter.yaml b/Documentation/devicetree/bindings/media/amlogic,c3-mipi-adapter.yaml new file mode 100644 index 0000000000000..ba43bc6709a0c --- /dev/null +++ b/Documentation/devicetree/bindings/media/amlogic,c3-mipi-adapter.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/amlogic,c3-mipi-adapter.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic C3 MIPI adapter receiver + +maintainers: + - Keke Li + +description: + MIPI adapter is used to convert the MIPI CSI-2 data + into an ISP supported data format. + +properties: + compatible: + enum: + - amlogic,c3-mipi-adapter + + reg: + maxItems: 3 + + reg-names: + items: + - const: top + - const: fd + - const: rd + + power-domains: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: vapb + - const: isp0 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: input port node. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: output port node. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - reg-names + - power-domains + - clocks + - clock-names + - ports + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + adap: adap@ff010000 { + compatible = "amlogic,c3-mipi-adapter"; + reg = <0x0 0xff010000 0x0 0x100>, + <0x0 0xff01b000 0x0 0x100>, + <0x0 0xff01d000 0x0 0x200>; + reg-names = "top", "fd", "rd"; + power-domains = <&pwrc PWRC_C3_ISP_TOP_ID>; + clocks = <&clkc_periphs CLKID_VAPB>, + <&clkc_periphs CLKID_ISP0>; + clock-names = "vapb", "isp0"; + assigned-clocks = <&clkc_periphs CLKID_VAPB>, + <&clkc_periphs CLKID_ISP0>; + assigned-clock-rates = <0>, <400000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + c3_adap_in: endpoint { + remote-endpoint = <&c3_mipi_csi_out>; + }; + }; + + port@1 { + reg = <1>; + c3_adap_out: endpoint { + remote-endpoint = <&c3_isp_in>; + }; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/media/amlogic,c3-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/amlogic,c3-mipi-csi2.yaml new file mode 100644 index 0000000000000..b0129beab0c37 --- /dev/null +++ b/Documentation/devicetree/bindings/media/amlogic,c3-mipi-csi2.yaml @@ -0,0 +1,127 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/amlogic,c3-mipi-csi2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic C3 MIPI CSI-2 receiver + +maintainers: + - Keke Li + +description: + MIPI CSI-2 receiver contains CSI-2 RX PHY and host controller. + It receives the MIPI data from the image sensor and sends MIPI data + to MIPI adapter. + +properties: + compatible: + enum: + - amlogic,c3-mipi-csi2 + + reg: + maxItems: 3 + + reg-names: + items: + - const: aphy + - const: dphy + - const: host + + power-domains: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: vapb + - const: phy0 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: input port node, connected to sensor. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: output port node + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - reg-names + - power-domains + - clocks + - clock-names + - ports + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + csi: csi@ff018000 { + compatible = "amlogic,c3-mipi-csi2"; + reg = <0x0 0xff018000 0x0 0x400>, + <0x0 0xff019000 0x0 0x300>, + <0x0 0xff01a000 0x0 0x100>; + reg-names = "aphy", "dphy", "host"; + power-domains = <&pwrc PWRC_C3_MIPI_ISP_WRAP_ID>; + clocks = <&clkc_periphs CLKID_VAPB>, + <&clkc_periphs CLKID_CSI_PHY0>; + clock-names = "vapb", "phy0"; + assigned-clocks = <&clkc_periphs CLKID_VAPB>, + <&clkc_periphs CLKID_CSI_PHY0>; + assigned-clock-rates = <0>, <200000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + c3_mipi_csi_in: endpoint { + remote-endpoint = <&imx290_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + c3_mipi_csi_out: endpoint { + remote-endpoint = <&c3_adap_in>; + }; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/media/cec/nvidia,tegra114-cec.yaml b/Documentation/devicetree/bindings/media/cec/nvidia,tegra114-cec.yaml index a6b73498bc217..4b46aa755ccd3 100644 --- a/Documentation/devicetree/bindings/media/cec/nvidia,tegra114-cec.yaml +++ b/Documentation/devicetree/bindings/media/cec/nvidia,tegra114-cec.yaml @@ -14,10 +14,16 @@ allOf: properties: compatible: - enum: - - nvidia,tegra114-cec - - nvidia,tegra124-cec - - nvidia,tegra210-cec + oneOf: + - enum: + - nvidia,tegra114-cec + - nvidia,tegra124-cec + - nvidia,tegra210-cec + - items: + - enum: + - nvidia,tegra186-cec + - nvidia,tegra194-cec + - const: nvidia,tegra210-cec clocks: maxItems: 1 diff --git a/Documentation/devicetree/bindings/media/fsl,imx-capture-subsystem.yaml b/Documentation/devicetree/bindings/media/fsl,imx-capture-subsystem.yaml new file mode 100644 index 0000000000000..25e65a344a0ac --- /dev/null +++ b/Documentation/devicetree/bindings/media/fsl,imx-capture-subsystem.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/fsl,imx-capture-subsystem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX Media Video Device + +description: + This is the media controller node for video capture support. It is a + virtual device that lists the camera serial interface nodes that the + media device will control + +maintainers: + - Frank Li + +properties: + compatible: + const: fsl,imx-capture-subsystem + + ports: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Should contain a list of phandles pointing to camera + sensor interface ports of IPU devices. + +required: + - compatible + +additionalProperties: false + +examples: + - | + capture-subsystem { + compatible = "fsl,imx-capture-subsystem"; + ports = <&ipu1_csi0>, <&ipu1_csi1>; + }; diff --git a/Documentation/devicetree/bindings/media/fsl,imx6-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/fsl,imx6-mipi-csi2.yaml new file mode 100644 index 0000000000000..65255f576f268 --- /dev/null +++ b/Documentation/devicetree/bindings/media/fsl,imx6-mipi-csi2.yaml @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/fsl,imx6-mipi-csi2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MIPI CSI-2 Receiver core in the i.MX SoC + +description: + This is the device node for the MIPI CSI-2 Receiver core in the i.MX + SoC. This is a Synopsys Designware MIPI CSI-2 host controller core + combined with a D-PHY core mixed into the same register block. In + addition this device consists of an i.MX-specific "CSI2IPU gasket" + glue logic, also controlled from the same register block. The CSI2IPU + gasket demultiplexes the four virtual channel streams from the host + controller's 32-bit output image bus onto four 16-bit parallel busses + to the i.MX IPU CSIs. + +maintainers: + - Frank Li + +properties: + compatible: + const: fsl,imx6-mipi-csi2 + + reg: + maxItems: 1 + + clocks: + items: + - description: hsi_tx (the D-PHY clock) + - description: video_27m (D-PHY PLL reference clock) + - description: eim_podf; + + clock-names: + items: + - const: dphy + - const: ref + - const: pix + + interrupts: + items: + - description: CSI-2 ERR1 irq + - description: CSI-2 ERR2 irq + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port node, single endpoint describing the CSI-2 transmitter. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + const: 0 + + data-lanes: + minItems: 1 + items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + + required: + - data-lanes + +patternProperties: + '^port@[1-4]$': + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + ports 1 through 4 are output ports connecting with parallel bus sink + endpoint nodes and correspond to the four MIPI CSI-2 virtual channel + outputs. + + properties: + endpoint@0: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + endpoint@1: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + + mipi@21dc000 { + compatible = "fsl,imx6-mipi-csi2"; + reg = <0x021dc000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clks IMX6QDL_CLK_HSI_TX>, + <&clks IMX6QDL_CLK_VIDEO_27M>, + <&clks IMX6QDL_CLK_EIM_PODF>; + clock-names = "dphy", "ref", "pix"; + + port@0 { + reg = <0>; + + endpoint { + remote-endpoint = <&ov5640_to_mipi_csi2>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + endpoint@0 { + reg = <0>; + remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>; + }; + + endpoint@1 { + reg = <1>; + remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/i2c/ad5820.txt b/Documentation/devicetree/bindings/media/i2c/ad5820.txt deleted file mode 100644 index 5764cbedf9b73..0000000000000 --- a/Documentation/devicetree/bindings/media/i2c/ad5820.txt +++ /dev/null @@ -1,28 +0,0 @@ -* Analog Devices AD5820 autofocus coil - -Required Properties: - - - compatible: Must contain one of: - - "adi,ad5820" - - "adi,ad5821" - - "adi,ad5823" - - - reg: I2C slave address - - - VANA-supply: supply of voltage for VANA pin - -Optional properties: - - - enable-gpios : GPIO spec for the XSHUTDOWN pin. The XSHUTDOWN signal is -active low, a high level on the pin enables the device. - -Example: - - ad5820: coil@c { - compatible = "adi,ad5820"; - reg = <0x0c>; - - VANA-supply = <&vaux4>; - enable-gpios = <&msmgpio 26 GPIO_ACTIVE_HIGH>; - }; - diff --git a/Documentation/devicetree/bindings/media/i2c/adi,ad5820.yaml b/Documentation/devicetree/bindings/media/i2c/adi,ad5820.yaml new file mode 100644 index 0000000000000..0c8f24f692cac --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/adi,ad5820.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/adi,ad5820.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD5820 autofocus coil + +maintainers: + - Pavel Machek + +description: + The AD5820 is a current sink driver designed for precise control of + voice coil motors (VCMs) in camera autofocus systems. + +properties: + compatible: + enum: + - adi,ad5820 + - adi,ad5821 + - adi,ad5823 + + reg: + maxItems: 1 + + enable-gpios: + maxItems: 1 + description: + GPIO spec for the XSHUTDOWN pin. The XSHUTDOWN signal is active low, + a high level on the pin enables the device. + + VANA-supply: + description: supply of voltage for VANA pin + +required: + - compatible + - reg + - VANA-supply + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + coil@c { + compatible = "adi,ad5820"; + reg = <0x0c>; + + enable-gpios = <&msmgpio 26 GPIO_ACTIVE_HIGH>; + VANA-supply = <&vaux4>; + }; + }; diff --git a/Documentation/devicetree/bindings/media/i2c/adp1653.txt b/Documentation/devicetree/bindings/media/i2c/adi,adp1653.txt similarity index 100% rename from Documentation/devicetree/bindings/media/i2c/adp1653.txt rename to Documentation/devicetree/bindings/media/i2c/adi,adp1653.txt diff --git a/Documentation/devicetree/bindings/media/i2c/adi,adv7180.yaml b/Documentation/devicetree/bindings/media/i2c/adi,adv7180.yaml new file mode 100644 index 0000000000000..dee8ce7cb7ba2 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/adi,adv7180.yaml @@ -0,0 +1,189 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/adi,adv7180.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices ADV7180 analog video decoder family + +maintainers: + - Lars-Peter Clausen + +description: + The adv7180 family devices are used to capture analog video to different + digital interfaces like MIPI CSI-2 or parallel video. + +properties: + compatible: + items: + - enum: + - adi,adv7180 + - adi,adv7180cp + - adi,adv7180st + - adi,adv7182 + - adi,adv7280 + - adi,adv7280-m + - adi,adv7281 + - adi,adv7281-m + - adi,adv7281-ma + - adi,adv7282 + - adi,adv7282-m + + reg: + maxItems: 1 + + powerdown-gpios: + maxItems: 1 + + reset-gpios: + maxItems: 1 + + adv,force-bt656-4: + deprecated: true + description: + Indicates that the output is a BT.656-4 compatible stream. + type: boolean + + adi,force-bt656-4: + description: + Indicates that the output is a BT.656-4 compatible stream. + type: boolean + + interrupts: + items: + - description: The GPIO connected to the INTRQ pin. + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + ports: true + +additionalProperties: false + +required: + - compatible + - reg + +allOf: + - if: + properties: + compatible: + enum: + - adi,adv7180 + - adi,adv7182 + - adi,adv7280 + - adi,adv7280-m + - adi,adv7281 + - adi,adv7281-m + - adi,adv7281-ma + - adi,adv7282 + - adi,adv7282-m + then: + required: + - port + + - if: + properties: + compatible: + contains: + const: adi,adv7180cp + then: + properties: + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@3: + $ref: /schemas/graph.yaml#/properties/port + description: Output port + + patternProperties: + "^port@[0-2]$": + $ref: /schemas/graph.yaml#/properties/port + description: Input port + + required: + - port@3 + + required: + - ports + + - if: + properties: + compatible: + contains: + const: adi,adv7180st + then: + properties: + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@6: + $ref: /schemas/graph.yaml#/properties/port + description: Output port + + patternProperties: + "^port@[0-5]$": + $ref: /schemas/graph.yaml#/properties/port + description: Input port + + required: + - port@6 + + required: + - ports + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + composite-in@20 { + compatible = "adi,adv7180"; + reg = <0x20>; + + port { + adv7180: endpoint { + bus-width = <8>; + remote-endpoint = <&vin1ep>; + }; + }; + }; + + }; + + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + composite-in@20 { + compatible = "adi,adv7180cp"; + reg = <0x20>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7180_in: endpoint { + remote-endpoint = <&composite_con_in>; + }; + }; + + port@3 { + reg = <3>; + adv7180_out: endpoint { + remote-endpoint = <&vin4_in>; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/i2c/adv7343.txt b/Documentation/devicetree/bindings/media/i2c/adi,adv7343.txt similarity index 100% rename from Documentation/devicetree/bindings/media/i2c/adv7343.txt rename to Documentation/devicetree/bindings/media/i2c/adi,adv7343.txt diff --git a/Documentation/devicetree/bindings/media/i2c/adi,adv748x.yaml b/Documentation/devicetree/bindings/media/i2c/adi,adv748x.yaml new file mode 100644 index 0000000000000..254987350321b --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/adi,adv748x.yaml @@ -0,0 +1,212 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/adi,adv748x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices ADV748X video decoder with HDMI receiver + +maintainers: + - Kieran Bingham + - Niklas Söderlund + +description: + The ADV7481 and ADV7482 are multi format video decoders with an integrated + HDMI receiver. They can output CSI-2 on two independent outputs TXA and TXB + from three input sources HDMI, analog and TTL. + +properties: + compatible: + items: + - enum: + - adi,adv7481 + - adi,adv7482 + + reg: + minItems: 1 + maxItems: 12 + description: + The ADV748x has up to twelve 256-byte maps that can be accessed via the + main I2C ports. Each map has it own I2C address and acts as a standard + slave device on the I2C bus. The main address is mandatory, others are + optional and remain at default values if not specified. + + reg-names: + minItems: 1 + items: + - const: main + - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] + - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] + - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] + - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] + - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] + - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] + - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] + - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] + - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] + - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] + - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] + + interrupts: true + + interrupt-names: true + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + patternProperties: + "^port@[0-7]$": + $ref: /schemas/graph.yaml#/properties/port + description: Input port nodes for analog inputs AIN[0-7]. + + properties: + port@8: + $ref: /schemas/graph.yaml#/properties/port + description: Input port node for HDMI. + + port@9: + $ref: /schemas/graph.yaml#/properties/port + description: Input port node for TTL. + + port@a: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Output port node, single endpoint describing the CSI-2 transmitter TXA. + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@b: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Output port node, single endpoint describing the CSI-2 transmitter TXB. + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + maxItems: 1 + + required: + - clock-lanes + - data-lanes + +allOf: + - if: + properties: + compatible: + contains: + const: adi,adv7481 + then: + properties: + interrupts: + minItems: 1 + maxItems: 3 + + interrupt-names: + minItems: 1 + maxItems: 3 + items: + enum: [ intrq1, intrq2, intrq3 ] + else: + properties: + interrupts: + minItems: 1 + maxItems: 2 + + interrupt-names: + minItems: 1 + maxItems: 2 + items: + enum: [ intrq1, intrq2 ] + +additionalProperties: false + +required: + - compatible + - reg + - ports + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + video-receiver@70 { + compatible = "adi,adv7482"; + reg = <0x70 0x71 0x72 0x73 0x74 0x75 + 0x60 0x61 0x62 0x63 0x64 0x65>; + reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater", + "infoframe", "cbus", "cec", "sdp", "txa", "txb"; + + interrupt-parent = <&gpio6>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>, <31 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "intrq1", "intrq2"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + + adv7482_ain7: endpoint { + remote-endpoint = <&cvbs_in>; + }; + }; + + port@8 { + reg = <8>; + + adv7482_hdmi: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; + + port@a { + reg = <10>; + + adv7482_txa: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi40_in>; + }; + }; + + port@b { + reg = <11>; + + adv7482_txb: endpoint { + clock-lanes = <0>; + data-lanes = <1>; + remote-endpoint = <&csi20_in>; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/i2c/adi,adv7604.yaml b/Documentation/devicetree/bindings/media/i2c/adi,adv7604.yaml new file mode 100644 index 0000000000000..6c403003cdda1 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/adi,adv7604.yaml @@ -0,0 +1,160 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/adi,adv7604.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices ADV7604/10/11/12 video decoder with HDMI receiver + +maintainers: + - Hans Verkuil + +description: + The ADV7604 and ADV7610/11/12 are multiformat video decoders with + an integrated HDMI receiver. The ADV7604 has four multiplexed HDMI inputs + and one analog input, and the ADV7610/11 have one HDMI input and no analog + input. The ADV7612 is similar to the ADV7610/11 but has 2 HDMI inputs. + + These device tree bindings support the ADV7610/11/12 only at the moment. + +properties: + compatible: + items: + - enum: + - adi,adv7610 + - adi,adv7611 + - adi,adv7612 + + reg: + minItems: 1 + maxItems: 13 + + reg-names: + minItems: 1 + items: + - const: main + - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] + - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] + - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] + - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] + - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] + - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] + - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] + - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] + - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] + - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] + - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] + - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] + + interrupts: + maxItems: 1 + + reset-gpios: + maxItems: 1 + + hpd-gpios: + minItems: 1 + description: + References to the GPIOs that control the HDMI hot-plug detection pins, + one per HDMI input. The active flag indicates the GPIO level that + enables hot-plug detection. + + default-input: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1 ] + description: + Select which input is selected after reset. + + ports: true + +required: + - compatible + - reg + - ports + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: adi,adv7611 + then: + properties: + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Input port + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Output port + + required: + - port@1 + + - if: + properties: + compatible: + contains: + const: adi,adv7612 + then: + properties: + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: Output port + + patternProperties: + "^port@[0-1]$": + $ref: /schemas/graph.yaml#/properties/port + description: Input port + + required: + - port@2 + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_receiver@4c { + compatible = "adi,adv7611"; + /* + * The edid page will be accessible @ 0x66 on the I2C bus. All + * other maps will retain their default addresses. + */ + reg = <0x4c>, <0x66>; + reg-names = "main", "edid"; + + reset-gpios = <&ioexp 0 GPIO_ACTIVE_LOW>; + hpd-gpios = <&ioexp 2 GPIO_ACTIVE_HIGH>; + default-input = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + hdmi_in: endpoint { + remote-endpoint = <&ccdc_in>; + }; + }; + }; + + + }; + }; diff --git a/Documentation/devicetree/bindings/media/i2c/adv7180.yaml b/Documentation/devicetree/bindings/media/i2c/adv7180.yaml deleted file mode 100644 index 9ee1483775f60..0000000000000 --- a/Documentation/devicetree/bindings/media/i2c/adv7180.yaml +++ /dev/null @@ -1,189 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/media/i2c/adv7180.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Analog Devices ADV7180 analog video decoder family - -maintainers: - - Lars-Peter Clausen - -description: - The adv7180 family devices are used to capture analog video to different - digital interfaces like MIPI CSI-2 or parallel video. - -properties: - compatible: - items: - - enum: - - adi,adv7180 - - adi,adv7180cp - - adi,adv7180st - - adi,adv7182 - - adi,adv7280 - - adi,adv7280-m - - adi,adv7281 - - adi,adv7281-m - - adi,adv7281-ma - - adi,adv7282 - - adi,adv7282-m - - reg: - maxItems: 1 - - powerdown-gpios: - maxItems: 1 - - reset-gpios: - maxItems: 1 - - adv,force-bt656-4: - deprecated: true - description: - Indicates that the output is a BT.656-4 compatible stream. - type: boolean - - adi,force-bt656-4: - description: - Indicates that the output is a BT.656-4 compatible stream. - type: boolean - - interrupts: - items: - - description: The GPIO connected to the INTRQ pin. - - port: - $ref: /schemas/graph.yaml#/$defs/port-base - unevaluatedProperties: false - - properties: - endpoint: - $ref: /schemas/media/video-interfaces.yaml# - unevaluatedProperties: false - - ports: true - -additionalProperties: false - -required: - - compatible - - reg - -allOf: - - if: - properties: - compatible: - enum: - - adi,adv7180 - - adi,adv7182 - - adi,adv7280 - - adi,adv7280-m - - adi,adv7281 - - adi,adv7281-m - - adi,adv7281-ma - - adi,adv7282 - - adi,adv7282-m - then: - required: - - port - - - if: - properties: - compatible: - contains: - const: adi,adv7180cp - then: - properties: - ports: - $ref: /schemas/graph.yaml#/properties/ports - properties: - port@3: - $ref: /schemas/graph.yaml#/properties/port - description: Output port - - patternProperties: - "^port@[0-2]$": - $ref: /schemas/graph.yaml#/properties/port - description: Input port - - required: - - port@3 - - required: - - ports - - - if: - properties: - compatible: - contains: - const: adi,adv7180st - then: - properties: - ports: - $ref: /schemas/graph.yaml#/properties/ports - properties: - port@6: - $ref: /schemas/graph.yaml#/properties/port - description: Output port - - patternProperties: - "^port@[0-5]$": - $ref: /schemas/graph.yaml#/properties/port - description: Input port - - required: - - port@6 - - required: - - ports - -examples: - - | - i2c { - #address-cells = <1>; - #size-cells = <0>; - - composite-in@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin1ep>; - }; - }; - }; - - }; - - - | - i2c { - #address-cells = <1>; - #size-cells = <0>; - - composite-in@20 { - compatible = "adi,adv7180cp"; - reg = <0x20>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7180_in: endpoint { - remote-endpoint = <&composite_con_in>; - }; - }; - - port@3 { - reg = <3>; - adv7180_out: endpoint { - remote-endpoint = <&vin4_in>; - }; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/i2c/adv748x.yaml b/Documentation/devicetree/bindings/media/i2c/adv748x.yaml deleted file mode 100644 index d6353081402be..0000000000000 --- a/Documentation/devicetree/bindings/media/i2c/adv748x.yaml +++ /dev/null @@ -1,212 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/media/i2c/adv748x.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Analog Devices ADV748X video decoder with HDMI receiver - -maintainers: - - Kieran Bingham - - Niklas Söderlund - -description: - The ADV7481 and ADV7482 are multi format video decoders with an integrated - HDMI receiver. They can output CSI-2 on two independent outputs TXA and TXB - from three input sources HDMI, analog and TTL. - -properties: - compatible: - items: - - enum: - - adi,adv7481 - - adi,adv7482 - - reg: - minItems: 1 - maxItems: 12 - description: - The ADV748x has up to twelve 256-byte maps that can be accessed via the - main I2C ports. Each map has it own I2C address and acts as a standard - slave device on the I2C bus. The main address is mandatory, others are - optional and remain at default values if not specified. - - reg-names: - minItems: 1 - items: - - const: main - - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] - - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] - - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] - - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] - - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] - - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] - - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] - - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] - - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] - - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] - - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] - - interrupts: true - - interrupt-names: true - - ports: - $ref: /schemas/graph.yaml#/properties/ports - - patternProperties: - "^port@[0-7]$": - $ref: /schemas/graph.yaml#/properties/port - description: Input port nodes for analog inputs AIN[0-7]. - - properties: - port@8: - $ref: /schemas/graph.yaml#/properties/port - description: Input port node for HDMI. - - port@9: - $ref: /schemas/graph.yaml#/properties/port - description: Input port node for TTL. - - port@a: - $ref: /schemas/graph.yaml#/$defs/port-base - unevaluatedProperties: false - description: - Output port node, single endpoint describing the CSI-2 transmitter TXA. - - properties: - endpoint: - $ref: /schemas/media/video-interfaces.yaml# - unevaluatedProperties: false - - properties: - clock-lanes: - maxItems: 1 - - data-lanes: - minItems: 1 - maxItems: 4 - - required: - - clock-lanes - - data-lanes - - port@b: - $ref: /schemas/graph.yaml#/$defs/port-base - unevaluatedProperties: false - description: - Output port node, single endpoint describing the CSI-2 transmitter TXB. - - properties: - endpoint: - $ref: /schemas/media/video-interfaces.yaml# - unevaluatedProperties: false - - properties: - clock-lanes: - maxItems: 1 - - data-lanes: - maxItems: 1 - - required: - - clock-lanes - - data-lanes - -allOf: - - if: - properties: - compatible: - contains: - const: adi,adv7481 - then: - properties: - interrupts: - minItems: 1 - maxItems: 3 - - interrupt-names: - minItems: 1 - maxItems: 3 - items: - enum: [ intrq1, intrq2, intrq3 ] - else: - properties: - interrupts: - minItems: 1 - maxItems: 2 - - interrupt-names: - minItems: 1 - maxItems: 2 - items: - enum: [ intrq1, intrq2 ] - -additionalProperties: false - -required: - - compatible - - reg - - ports - -examples: - - | - #include - - i2c { - #address-cells = <1>; - #size-cells = <0>; - - video-receiver@70 { - compatible = "adi,adv7482"; - reg = <0x70 0x71 0x72 0x73 0x74 0x75 - 0x60 0x61 0x62 0x63 0x64 0x65>; - reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater", - "infoframe", "cbus", "cec", "sdp", "txa", "txb"; - - interrupt-parent = <&gpio6>; - interrupts = <30 IRQ_TYPE_LEVEL_LOW>, <31 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "intrq1", "intrq2"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@7 { - reg = <7>; - - adv7482_ain7: endpoint { - remote-endpoint = <&cvbs_in>; - }; - }; - - port@8 { - reg = <8>; - - adv7482_hdmi: endpoint { - remote-endpoint = <&hdmi_in>; - }; - }; - - port@a { - reg = <10>; - - adv7482_txa: endpoint { - clock-lanes = <0>; - data-lanes = <1 2 3 4>; - remote-endpoint = <&csi40_in>; - }; - }; - - port@b { - reg = <11>; - - adv7482_txb: endpoint { - clock-lanes = <0>; - data-lanes = <1>; - remote-endpoint = <&csi20_in>; - }; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/i2c/adv7604.yaml b/Documentation/devicetree/bindings/media/i2c/adv7604.yaml deleted file mode 100644 index 7589d377c6864..0000000000000 --- a/Documentation/devicetree/bindings/media/i2c/adv7604.yaml +++ /dev/null @@ -1,160 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/media/i2c/adv7604.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Analog Devices ADV7604/10/11/12 video decoder with HDMI receiver - -maintainers: - - Hans Verkuil - -description: - The ADV7604 and ADV7610/11/12 are multiformat video decoders with - an integrated HDMI receiver. The ADV7604 has four multiplexed HDMI inputs - and one analog input, and the ADV7610/11 have one HDMI input and no analog - input. The ADV7612 is similar to the ADV7610/11 but has 2 HDMI inputs. - - These device tree bindings support the ADV7610/11/12 only at the moment. - -properties: - compatible: - items: - - enum: - - adi,adv7610 - - adi,adv7611 - - adi,adv7612 - - reg: - minItems: 1 - maxItems: 13 - - reg-names: - minItems: 1 - items: - - const: main - - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] - - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] - - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] - - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] - - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] - - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] - - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] - - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] - - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] - - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] - - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] - - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] - - interrupts: - maxItems: 1 - - reset-gpios: - maxItems: 1 - - hpd-gpios: - minItems: 1 - description: - References to the GPIOs that control the HDMI hot-plug detection pins, - one per HDMI input. The active flag indicates the GPIO level that - enables hot-plug detection. - - default-input: - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [ 0, 1 ] - description: - Select which input is selected after reset. - - ports: true - -required: - - compatible - - reg - - ports - -additionalProperties: false - -allOf: - - if: - properties: - compatible: - contains: - const: adi,adv7611 - then: - properties: - ports: - $ref: /schemas/graph.yaml#/properties/ports - properties: - port@0: - $ref: /schemas/graph.yaml#/properties/port - description: Input port - - port@1: - $ref: /schemas/graph.yaml#/properties/port - description: Output port - - required: - - port@1 - - - if: - properties: - compatible: - contains: - const: adi,adv7612 - then: - properties: - ports: - $ref: /schemas/graph.yaml#/properties/ports - properties: - port@2: - $ref: /schemas/graph.yaml#/properties/port - description: Output port - - patternProperties: - "^port@[0-1]$": - $ref: /schemas/graph.yaml#/properties/port - description: Input port - - required: - - port@2 - -examples: - - | - #include - - i2c { - #address-cells = <1>; - #size-cells = <0>; - - hdmi_receiver@4c { - compatible = "adi,adv7611"; - /* - * The edid page will be accessible @ 0x66 on the I2C bus. All - * other maps will retain their default addresses. - */ - reg = <0x4c>, <0x66>; - reg-names = "main", "edid"; - - reset-gpios = <&ioexp 0 GPIO_ACTIVE_LOW>; - hpd-gpios = <&ioexp 2 GPIO_ACTIVE_HIGH>; - default-input = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - reg = <1>; - hdmi_in: endpoint { - remote-endpoint = <&ccdc_in>; - }; - }; - }; - - - }; - }; diff --git a/Documentation/devicetree/bindings/media/i2c/mt9v032.txt b/Documentation/devicetree/bindings/media/i2c/aptina,mt9v032.txt similarity index 100% rename from Documentation/devicetree/bindings/media/i2c/mt9v032.txt rename to Documentation/devicetree/bindings/media/i2c/aptina,mt9v032.txt diff --git a/Documentation/devicetree/bindings/media/i2c/imx219.yaml b/Documentation/devicetree/bindings/media/i2c/imx219.yaml deleted file mode 100644 index 07d088cf66e0b..0000000000000 --- a/Documentation/devicetree/bindings/media/i2c/imx219.yaml +++ /dev/null @@ -1,109 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/media/i2c/imx219.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Sony 1/4.0-Inch 8Mpixel CMOS Digital Image Sensor - -maintainers: - - Dave Stevenson - -description: |- - The Sony imx219 is a 1/4.0-inch CMOS active pixel digital image sensor - with an active array size of 3280H x 2464V. It is programmable through - I2C interface. The I2C address is fixed to 0x10 as per sensor data sheet. - Image data is sent through MIPI CSI-2, which is configured as either 2 or - 4 data lanes. - -properties: - compatible: - const: sony,imx219 - - reg: - description: I2C device address - maxItems: 1 - - clocks: - maxItems: 1 - - VDIG-supply: - description: - Digital I/O voltage supply, 1.8 volts - - VANA-supply: - description: - Analog voltage supply, 2.8 volts - - VDDL-supply: - description: - Digital core voltage supply, 1.2 volts - - reset-gpios: - maxItems: 1 - description: |- - Reference to the GPIO connected to the xclr pin, if any. - Must be released (set high) after all supplies are applied. - - port: - $ref: /schemas/graph.yaml#/$defs/port-base - additionalProperties: false - - properties: - endpoint: - $ref: /schemas/media/video-interfaces.yaml# - unevaluatedProperties: false - - properties: - data-lanes: - description: |- - The sensor supports either two-lane, or four-lane operation. - If this property is omitted four-lane operation is assumed. - For two-lane operation the property must be set to <1 2>. - items: - - const: 1 - - const: 2 - - clock-noncontinuous: true - link-frequencies: true - - required: - - link-frequencies - -required: - - compatible - - reg - - clocks - - VANA-supply - - VDIG-supply - - VDDL-supply - - port - -additionalProperties: false - -examples: - - | - i2c { - #address-cells = <1>; - #size-cells = <0>; - - imx219: sensor@10 { - compatible = "sony,imx219"; - reg = <0x10>; - clocks = <&imx219_clk>; - VANA-supply = <&imx219_vana>; /* 2.8v */ - VDIG-supply = <&imx219_vdig>; /* 1.8v */ - VDDL-supply = <&imx219_vddl>; /* 1.2v */ - - port { - imx219_0: endpoint { - remote-endpoint = <&csi1_ep>; - data-lanes = <1 2>; - clock-noncontinuous; - link-frequencies = /bits/ 64 <456000000>; - }; - }; - }; - }; - -... diff --git a/Documentation/devicetree/bindings/media/i2c/max2175.txt b/Documentation/devicetree/bindings/media/i2c/maxim,max2175.txt similarity index 100% rename from Documentation/devicetree/bindings/media/i2c/max2175.txt rename to Documentation/devicetree/bindings/media/i2c/maxim,max2175.txt diff --git a/Documentation/devicetree/bindings/media/i2c/mt9m111.txt b/Documentation/devicetree/bindings/media/i2c/micron,mt9m111.txt similarity index 100% rename from Documentation/devicetree/bindings/media/i2c/mt9m111.txt rename to Documentation/devicetree/bindings/media/i2c/micron,mt9m111.txt diff --git a/Documentation/devicetree/bindings/media/i2c/tda1997x.txt b/Documentation/devicetree/bindings/media/i2c/nxp,tda1997x.txt similarity index 100% rename from Documentation/devicetree/bindings/media/i2c/tda1997x.txt rename to Documentation/devicetree/bindings/media/i2c/nxp,tda1997x.txt diff --git a/Documentation/devicetree/bindings/media/i2c/mt9m001.txt b/Documentation/devicetree/bindings/media/i2c/onnn,mt9m001.txt similarity index 100% rename from Documentation/devicetree/bindings/media/i2c/mt9m001.txt rename to Documentation/devicetree/bindings/media/i2c/onnn,mt9m001.txt diff --git a/Documentation/devicetree/bindings/media/i2c/ovti,ov02e10.yaml b/Documentation/devicetree/bindings/media/i2c/ovti,ov02e10.yaml new file mode 100644 index 0000000000000..03d476bcf8058 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/ovti,ov02e10.yaml @@ -0,0 +1,152 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (c) 2025 Linaro Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/ovti,ov02e10.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Omnivision OV02E10 CMOS Sensor + +maintainers: + - Bryan O'Donoghue + +description: | + The Omnivision OV02E10 and OV02C10 sensors are 2 megapixel, CMOS image sensors which support: + - Automatic black level calibration (ABLC) + - Programmable controls for frame rate, mirror and flip, binning, cropping + and windowing + - OVO2C10 + - 10 bit RAW Bayer 1920x1080 60 fps 2-lane @ 800 Mbps/lane + - 10 bit RAW Bayer 1920x1080 60 fps 1-lane @ 1500 Mbps/lane + - 10 bit RAW Bayer 1280x720 60 fps cropped 1-lane @ 960 Mbps/lane + - 10 bit RGB/BW 640x480 60 fps bin2 or skip2 1-lane @ 800 Mbps/lane + - 10 bit RGB/BW 480x270 60 fps bin4 or skip4 1-lane @ 800 Mbps/lane + - OV02E10 + - 10 bit RAW Bayer 1920x1088 60 fps 2-lane @ 720 Mbps/lane + - 10 bit RAW Bayer 1280x1080 60 fps 2-lane @ 720 Mbps/lane + - 10 bit Quad Bayer 960x540 60 fps 2-lane 360 Mbps/lane + - 8 bit Quad Bayer 480x270 1/3/5/10 fps sub2 288 Mbps/lane + - 8 bit Quad Bayer 232x132 1/3/5/10 fps sub4 144 Mbps/lane + - Dynamic defect pixel cancellation + - Standard SCCB command interface + +allOf: + - $ref: /schemas/media/video-interface-devices.yaml# + +properties: + compatible: + enum: + - ovti,ov02c10 + - ovti,ov02e10 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + avdd-supply: + description: Analogue circuit voltage supply. + + dovdd-supply: + description: I/O circuit voltage supply. + + dvdd-supply: + description: Digital circuit voltage supply. + + reset-gpios: + description: Active low GPIO connected to XSHUTDOWN pad of the sensor. + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + additionalProperties: false + + properties: + data-lanes: + items: + - const: 1 + - const: 2 + link-frequencies: true + remote-endpoint: true + + required: + - data-lanes + - link-frequencies + - remote-endpoint + +required: + - compatible + - reg + - clocks + - port + +unevaluatedProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + ov02e10: camera@10 { + compatible = "ovti,ov02e10"; + reg = <0x10>; + + reset-gpios = <&tlmm 237 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_rgb_defaultt>; + + clocks = <&ov02e10_clk>; + + assigned-clocks = <&ov02e10_clk>; + assigned-clock-parents = <&ov02e10_clk_parent>; + assigned-clock-rates = <19200000>; + + avdd-supply = <&vreg_l7b_2p8>; + dvdd-supply = <&vreg_l7b_1p8>; + dovdd-supply = <&vreg_l3m_1p8>; + + port { + ov02e10_ep: endpoint { + remote-endpoint = <&csiphy4_ep>; + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <400000000>; + }; + }; + }; + + ov02c10: camera@36 { + compatible = "ovti,ov02c10"; + reg = <0x36>; + + reset-gpios = <&tlmm 237 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_rgb_defaultt>; + + clocks = <&ov02c10_clk>; + + assigned-clocks = <&ov02c10_clk>; + assigned-clock-parents = <&ov02c10_clk_parent>; + assigned-clock-rates = <19200000>; + + avdd-supply = <&vreg_l7b_2p8>; + dvdd-supply = <&vreg_l7b_1p8>; + dovdd-supply = <&vreg_l3m_1p8>; + + port { + ov02c10_ep: endpoint { + remote-endpoint = <&csiphy4_ep>; + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <400000000>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/media/i2c/ov2640.txt b/Documentation/devicetree/bindings/media/i2c/ovti,ov2640.txt similarity index 100% rename from Documentation/devicetree/bindings/media/i2c/ov2640.txt rename to Documentation/devicetree/bindings/media/i2c/ovti,ov2640.txt diff --git a/Documentation/devicetree/bindings/media/i2c/ov2659.txt b/Documentation/devicetree/bindings/media/i2c/ovti,ov2659.txt similarity index 100% rename from Documentation/devicetree/bindings/media/i2c/ov2659.txt rename to Documentation/devicetree/bindings/media/i2c/ovti,ov2659.txt diff --git a/Documentation/devicetree/bindings/media/i2c/ov7670.txt b/Documentation/devicetree/bindings/media/i2c/ovti,ov7670.txt similarity index 100% rename from Documentation/devicetree/bindings/media/i2c/ov7670.txt rename to Documentation/devicetree/bindings/media/i2c/ovti,ov7670.txt diff --git a/Documentation/devicetree/bindings/media/i2c/ov7740.txt b/Documentation/devicetree/bindings/media/i2c/ovti,ov7740.txt similarity index 100% rename from Documentation/devicetree/bindings/media/i2c/ov7740.txt rename to Documentation/devicetree/bindings/media/i2c/ovti,ov7740.txt diff --git a/Documentation/devicetree/bindings/media/i2c/ov9650.txt b/Documentation/devicetree/bindings/media/i2c/ovti,ov9650.txt similarity index 100% rename from Documentation/devicetree/bindings/media/i2c/ov9650.txt rename to Documentation/devicetree/bindings/media/i2c/ovti,ov9650.txt diff --git a/Documentation/devicetree/bindings/media/i2c/sony,imx219.yaml b/Documentation/devicetree/bindings/media/i2c/sony,imx219.yaml new file mode 100644 index 0000000000000..38c3759bcd9f5 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/sony,imx219.yaml @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/sony,imx219.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sony 1/4.0-Inch 8Mpixel CMOS Digital Image Sensor + +maintainers: + - Dave Stevenson + +description: |- + The Sony imx219 is a 1/4.0-inch CMOS active pixel digital image sensor + with an active array size of 3280H x 2464V. It is programmable through + I2C interface. The I2C address is fixed to 0x10 as per sensor data sheet. + Image data is sent through MIPI CSI-2, which is configured as either 2 or + 4 data lanes. + +allOf: + - $ref: /schemas/media/video-interface-devices.yaml# + +properties: + compatible: + const: sony,imx219 + + reg: + description: I2C device address + maxItems: 1 + + clocks: + maxItems: 1 + + VDIG-supply: + description: + Digital I/O voltage supply, 1.8 volts + + VANA-supply: + description: + Analog voltage supply, 2.8 volts + + VDDL-supply: + description: + Digital core voltage supply, 1.2 volts + + reset-gpios: + maxItems: 1 + description: |- + Reference to the GPIO connected to the xclr pin, if any. + Must be released (set high) after all supplies are applied. + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + description: |- + The sensor supports either two-lane, or four-lane operation. + If this property is omitted four-lane operation is assumed. + For two-lane operation the property must be set to <1 2>. + items: + - const: 1 + - const: 2 + + clock-noncontinuous: true + link-frequencies: true + + required: + - link-frequencies + +required: + - compatible + - reg + - clocks + - VANA-supply + - VDIG-supply + - VDDL-supply + - port + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + imx219: sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + clocks = <&imx219_clk>; + VANA-supply = <&imx219_vana>; /* 2.8v */ + VDIG-supply = <&imx219_vdig>; /* 1.8v */ + VDDL-supply = <&imx219_vddl>; /* 1.2v */ + + port { + imx219_0: endpoint { + remote-endpoint = <&csi1_ep>; + data-lanes = <1 2>; + clock-noncontinuous; + link-frequencies = /bits/ 64 <456000000>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/media/i2c/sony,imx290.yaml b/Documentation/devicetree/bindings/media/i2c/sony,imx290.yaml index fa69bd21c8da4..990acf89af8fc 100644 --- a/Documentation/devicetree/bindings/media/i2c/sony,imx290.yaml +++ b/Documentation/devicetree/bindings/media/i2c/sony,imx290.yaml @@ -136,7 +136,7 @@ examples: port { imx290_ep: endpoint { data-lanes = <1 2 3 4>; - link-frequencies = /bits/ 64 <445500000>; + link-frequencies = /bits/ 64 <222750000 148500000>; remote-endpoint = <&csiphy0_ep>; }; }; diff --git a/Documentation/devicetree/bindings/media/i2c/sony,imx415.yaml b/Documentation/devicetree/bindings/media/i2c/sony,imx415.yaml index 34962c5c70065..7c11e871dca67 100644 --- a/Documentation/devicetree/bindings/media/i2c/sony,imx415.yaml +++ b/Documentation/devicetree/bindings/media/i2c/sony,imx415.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Sony IMX415 CMOS Image Sensor maintainers: - - Michael Riesch + - Michael Riesch description: |- The Sony IMX415 is a diagonal 6.4 mm (Type 1/2.8) CMOS active pixel type diff --git a/Documentation/devicetree/bindings/media/i2c/st,vd55g1.yaml b/Documentation/devicetree/bindings/media/i2c/st,vd55g1.yaml new file mode 100644 index 0000000000000..3c071e6fbea61 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/st,vd55g1.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (c) 2025 STMicroelectronics SA. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/st,vd55g1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics VD55G1 Global Shutter Image Sensor + +maintainers: + - Benjamin Mugnier + - Sylvain Petinot + +description: |- + The STMicroelectronics VD55G1 is a global shutter image sensor with an active + array size of 804H x 704V. It is programmable through I2C interface. The I2C + address is fixed to 0x10. + + Image data is sent through MIPI CSI-2, which is configured as only 1 data + lane. The sensor provides 4 GPIOS that can be used for external LED signal + (synchronized with sensor integration periods). + +allOf: + - $ref: /schemas/media/video-interface-devices.yaml# + +properties: + compatible: + const: st,vd55g1 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + vcore-supply: + description: Digital core power supply (1.15V) + + vddio-supply: + description: Digital IO power supply (1.8V) + + vana-supply: + description: Analog power supply (2.8V) + + reset-gpios: + description: Sensor reset active low GPIO (XSHUTDOWN) + maxItems: 1 + + st,leds: + description: + List sensor's GPIOs used to control strobe light sources during exposure + time. The numbers identify the sensor pin on which the illumination + system is connected. GPIOs are active-high. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 4 + items: + minimum: 0 + maximum: 3 + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + items: + - const: 1 + + link-frequencies: + maxItems: 1 + items: + minimum: 125000000 + maximum: 600000000 + + lane-polarities: + minItems: 1 + maxItems: 2 + + required: + - data-lanes + - link-frequencies + +required: + - compatible + - reg + - clocks + - vcore-supply + - vddio-supply + - vana-supply + - reset-gpios + - port + +unevaluatedProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + camera-sensor@10 { + compatible = "st,vd55g1"; + reg = <0x10>; + + clocks = <&camera_clk_12M>; + + vcore-supply = <&camera_vcore_v1v15>; + vddio-supply = <&camera_vddio_v1v8>; + vana-supply = <&camera_vana_v2v8>; + + reset-gpios = <&gpio 5 GPIO_ACTIVE_LOW>; + st,leds = <2>; + + orientation = <2>; + rotation = <0>; + + port { + endpoint { + data-lanes = <1>; + link-frequencies = /bits/ 64 <600000000>; + remote-endpoint = <&csiphy0_ep>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/i2c/st,vd56g3.yaml b/Documentation/devicetree/bindings/media/i2c/st,vd56g3.yaml new file mode 100644 index 0000000000000..c6673b8539dbc --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/st,vd56g3.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (c) 2024 STMicroelectronics SA. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/st,vd56g3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics VD56G3 Global Shutter Image Sensor + +maintainers: + - Benjamin Mugnier + - Sylvain Petinot + +description: |- + The STMicroelectronics VD56G3 is a 1.5 M pixel global shutter image sensor + with an active array size of 1124 x 1364 (portrait orientation). It is + programmable through I2C, the address is fixed to 0x10. The sensor output is + available via CSI-2, which is configured as either 1 or 2 data lanes. The + sensor provides 8 GPIOS that can be used for external LED signal + (synchronized with sensor integration periods) + +allOf: + - $ref: /schemas/media/video-interface-devices.yaml# + +properties: + compatible: + enum: + - st,vd56g3 + - st,vd66gy + description: + Two variants are availables; VD56G3 is a monochrome sensor while VD66GY + is a colour variant. + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + vcore-supply: + description: Digital core power supply (1.15V) + + vddio-supply: + description: Digital IO power supply (1.8V) + + vana-supply: + description: Analog power supply (2.8V) + + reset-gpios: + description: Sensor reset active low GPIO (XSHUTDOWN) + maxItems: 1 + + st,leds: + description: + List sensor's GPIOs used to control strobe light sources during exposure + time. The numbers identify the sensor pin on which the illumination system + is connected. GPIOs are active-high. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 8 + items: + minimum: 0 + maximum: 7 + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 2 + items: + enum: [1, 2] + + link-frequencies: + maxItems: 1 + items: + enum: [402000000, 750000000] + + lane-polarities: + minItems: 1 + maxItems: 3 + description: Any lane can be inverted or not. + + required: + - data-lanes + - link-frequencies + +required: + - compatible + - reg + - clocks + - vcore-supply + - vddio-supply + - vana-supply + - reset-gpios + - port + +unevaluatedProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + camera-sensor@10 { + compatible = "st,vd56g3"; + reg = <0x10>; + + clocks = <&camera_clk_12M>; + + vcore-supply = <&camera_vcore_v1v15>; + vddio-supply = <&camera_vddio_v1v8>; + vana-supply = <&camera_vana_v2v8>; + + reset-gpios = <&gpio 5 GPIO_ACTIVE_LOW>; + st,leds = <6>; + + orientation = <2>; + rotation = <0>; + + port { + endpoint { + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <402000000>; + remote-endpoint = <&csiphy0_ep>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/i2c/ti,ds90ub953.yaml b/Documentation/devicetree/bindings/media/i2c/ti,ds90ub953.yaml index 2030366994d18..2e129bf573b79 100644 --- a/Documentation/devicetree/bindings/media/i2c/ti,ds90ub953.yaml +++ b/Documentation/devicetree/bindings/media/i2c/ti,ds90ub953.yaml @@ -38,6 +38,13 @@ properties: '#clock-cells': const: 0 + reg: + maxItems: 1 + description: + The strap I2C address of the serializer. Can be used by the deserializer + to communicate over back-channel when the forward-channel is not yet + active. + ports: $ref: /schemas/graph.yaml#/properties/ports @@ -81,51 +88,57 @@ examples: - | #include - serializer { - compatible = "ti,ds90ub953-q1"; + link { + #address-cells = <1>; + #size-cells = <0>; + + serializer@18 { + compatible = "ti,ds90ub953-q1"; + reg = <0x18>; - gpio-controller; - #gpio-cells = <2>; + gpio-controller; + #gpio-cells = <2>; - #clock-cells = <0>; + #clock-cells = <0>; - ports { - #address-cells = <1>; - #size-cells = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; - port@0 { - reg = <0>; - ub953_in: endpoint { - clock-lanes = <0>; - data-lanes = <1 2 3 4>; - remote-endpoint = <&sensor_out>; + port@0 { + reg = <0>; + ub953_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_out>; + }; }; - }; - port@1 { - reg = <1>; - endpoint { - remote-endpoint = <&deser_fpd_in>; + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&deser_fpd_in>; + }; }; }; - }; - i2c { - #address-cells = <1>; - #size-cells = <0>; + i2c { + #address-cells = <1>; + #size-cells = <0>; - sensor@1a { - compatible = "sony,imx274"; - reg = <0x1a>; + sensor@1a { + compatible = "sony,imx274"; + reg = <0x1a>; - reset-gpios = <&serializer 0 GPIO_ACTIVE_LOW>; + reset-gpios = <&serializer 0 GPIO_ACTIVE_LOW>; - clocks = <&serializer>; - clock-names = "inck"; + clocks = <&serializer>; + clock-names = "inck"; - port { - sensor_out: endpoint { - remote-endpoint = <&ub953_in>; + port { + sensor_out: endpoint { + remote-endpoint = <&ub953_in>; + }; }; }; }; diff --git a/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml b/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml index 0b71e6f911a88..4dcbd2b039a58 100644 --- a/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml +++ b/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml @@ -68,6 +68,12 @@ properties: description: The link number maxItems: 1 + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + i2c-alias: $ref: /schemas/types.yaml#/definitions/uint32 description: @@ -107,7 +113,8 @@ properties: maximum: 14 description: Manual EQ level - serializer: + patternProperties: + '^serializer(@[0-9a-f]+)*$': type: object description: FPD-Link Serializer node @@ -115,7 +122,6 @@ properties: - reg - i2c-alias - ti,rx-mode - - serializer ports: $ref: /schemas/graph.yaml#/properties/ports @@ -309,13 +315,17 @@ examples: /* Link 0 has DS90UB953 serializer and IMX274 sensor */ link@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; i2c-alias = <0x44>; ti,rx-mode = <3>; - serializer1: serializer { + serializer1: serializer@30 { compatible = "ti,ds90ub953-q1"; + reg = <0x30>; gpio-controller; #gpio-cells = <2>; diff --git a/Documentation/devicetree/bindings/media/i2c/ths8200.txt b/Documentation/devicetree/bindings/media/i2c/ti,ths8200.txt similarity index 100% rename from Documentation/devicetree/bindings/media/i2c/ths8200.txt rename to Documentation/devicetree/bindings/media/i2c/ti,ths8200.txt diff --git a/Documentation/devicetree/bindings/media/i2c/tvp514x.txt b/Documentation/devicetree/bindings/media/i2c/ti,tvp514x.txt similarity index 100% rename from Documentation/devicetree/bindings/media/i2c/tvp514x.txt rename to Documentation/devicetree/bindings/media/i2c/ti,tvp514x.txt diff --git a/Documentation/devicetree/bindings/media/i2c/tvp5150.txt b/Documentation/devicetree/bindings/media/i2c/ti,tvp5150.txt similarity index 100% rename from Documentation/devicetree/bindings/media/i2c/tvp5150.txt rename to Documentation/devicetree/bindings/media/i2c/ti,tvp5150.txt diff --git a/Documentation/devicetree/bindings/media/i2c/tvp7002.txt b/Documentation/devicetree/bindings/media/i2c/ti,tvp7002.txt similarity index 100% rename from Documentation/devicetree/bindings/media/i2c/tvp7002.txt rename to Documentation/devicetree/bindings/media/i2c/ti,tvp7002.txt diff --git a/Documentation/devicetree/bindings/media/i2c/tc358743.txt b/Documentation/devicetree/bindings/media/i2c/toshiba,tc358743.txt similarity index 100% rename from Documentation/devicetree/bindings/media/i2c/tc358743.txt rename to Documentation/devicetree/bindings/media/i2c/toshiba,tc358743.txt diff --git a/Documentation/devicetree/bindings/media/imx.txt b/Documentation/devicetree/bindings/media/imx.txt deleted file mode 100644 index 77f4b0a7fd2b0..0000000000000 --- a/Documentation/devicetree/bindings/media/imx.txt +++ /dev/null @@ -1,53 +0,0 @@ -Freescale i.MX Media Video Device -================================= - -Video Media Controller node ---------------------------- - -This is the media controller node for video capture support. It is a -virtual device that lists the camera serial interface nodes that the -media device will control. - -Required properties: -- compatible : "fsl,imx-capture-subsystem"; -- ports : Should contain a list of phandles pointing to camera - sensor interface ports of IPU devices - -example: - -capture-subsystem { - compatible = "fsl,imx-capture-subsystem"; - ports = <&ipu1_csi0>, <&ipu1_csi1>; -}; - - -mipi_csi2 node --------------- - -This is the device node for the MIPI CSI-2 Receiver core in the i.MX -SoC. This is a Synopsys Designware MIPI CSI-2 host controller core -combined with a D-PHY core mixed into the same register block. In -addition this device consists of an i.MX-specific "CSI2IPU gasket" -glue logic, also controlled from the same register block. The CSI2IPU -gasket demultiplexes the four virtual channel streams from the host -controller's 32-bit output image bus onto four 16-bit parallel busses -to the i.MX IPU CSIs. - -Required properties: -- compatible : "fsl,imx6-mipi-csi2"; -- reg : physical base address and length of the register set; -- clocks : the MIPI CSI-2 receiver requires three clocks: hsi_tx - (the D-PHY clock), video_27m (D-PHY PLL reference - clock), and eim_podf; -- clock-names : must contain "dphy", "ref", "pix"; -- port@* : five port nodes must exist, containing endpoints - connecting to the source and sink devices according to - of_graph bindings. The first port is an input port, - connecting with a MIPI CSI-2 source, and ports 1 - through 4 are output ports connecting with parallel - bus sink endpoint nodes and correspond to the four - MIPI CSI-2 virtual channel outputs. - -Optional properties: -- interrupts : must contain two level-triggered interrupts, - in order: 100 and 101; diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml index 03f31b0090855..40fda59fa8a80 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml @@ -16,8 +16,12 @@ description: properties: compatible: - enum: - - mediatek,mt8195-mdp3-fg + oneOf: + - enum: + - mediatek,mt8195-mdp3-fg + - items: + - const: mediatek,mt8188-mdp3-fg + - const: mediatek,mt8195-mdp3-fg reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml index d4609bba65787..d9f926c20220d 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml @@ -16,8 +16,12 @@ description: properties: compatible: - enum: - - mediatek,mt8195-mdp3-hdr + oneOf: + - enum: + - mediatek,mt8195-mdp3-hdr + - items: + - const: mediatek,mt8188-mdp3-hdr + - const: mediatek,mt8195-mdp3-hdr reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml index f5676bec43266..8124c39d73e9a 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml @@ -20,6 +20,7 @@ properties: - mediatek,mt8183-mdp3-rsz - items: - enum: + - mediatek,mt8188-mdp3-rsz - mediatek,mt8195-mdp3-rsz - const: mediatek,mt8183-mdp3-rsz diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml index d815bea29154b..1d8e7e202c427 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml @@ -16,8 +16,12 @@ description: properties: compatible: - enum: - - mediatek,mt8195-mdp3-stitch + oneOf: + - enum: + - mediatek,mt8195-mdp3-stitch + - items: + - const: mediatek,mt8188-mdp3-stitch + - const: mediatek,mt8195-mdp3-stitch reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml index 14ea556d4f82a..6cff7c073ce47 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml @@ -17,8 +17,12 @@ description: properties: compatible: - enum: - - mediatek,mt8195-mdp3-tcc + oneOf: + - enum: + - mediatek,mt8195-mdp3-tcc + - items: + - const: mediatek,mt8188-mdp3-tcc + - const: mediatek,mt8195-mdp3-tcc reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml index 8ab7f2d8e148f..cdfa273247385 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml @@ -16,8 +16,12 @@ description: properties: compatible: - enum: - - mediatek,mt8195-mdp3-tdshp + oneOf: + - enum: + - mediatek,mt8195-mdp3-tdshp + - items: + - const: mediatek,mt8188-mdp3-tdshp + - const: mediatek,mt8195-mdp3-tdshp reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml index 53a6793384025..b6269f4f9fd65 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml @@ -20,6 +20,7 @@ properties: - mediatek,mt8183-mdp3-wrot - items: - enum: + - mediatek,mt8188-mdp3-wrot - mediatek,mt8195-mdp3-wrot - const: mediatek,mt8183-mdp3-wrot diff --git a/Documentation/devicetree/bindings/media/qcom,msm8916-camss.yaml b/Documentation/devicetree/bindings/media/qcom,msm8916-camss.yaml index 3469a43f00d41..7c8e0a905d89e 100644 --- a/Documentation/devicetree/bindings/media/qcom,msm8916-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,msm8916-camss.yaml @@ -93,6 +93,10 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -112,6 +116,10 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes diff --git a/Documentation/devicetree/bindings/media/qcom,msm8953-camss.yaml b/Documentation/devicetree/bindings/media/qcom,msm8953-camss.yaml index 8856fba385b11..6d776b0ca7114 100644 --- a/Documentation/devicetree/bindings/media/qcom,msm8953-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,msm8953-camss.yaml @@ -112,6 +112,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -131,6 +136,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -150,6 +160,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes diff --git a/Documentation/devicetree/bindings/media/qcom,msm8996-camss.yaml b/Documentation/devicetree/bindings/media/qcom,msm8996-camss.yaml index 644646de338a4..a2025952fe95b 100644 --- a/Documentation/devicetree/bindings/media/qcom,msm8996-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,msm8996-camss.yaml @@ -115,6 +115,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -134,6 +139,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -153,6 +163,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -172,6 +187,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes diff --git a/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml b/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml index 83c4a5d95f020..bfd8b1ad47312 100644 --- a/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml @@ -18,7 +18,12 @@ allOf: properties: compatible: - const: qcom,sc7180-venus + oneOf: + - items: + - enum: + - qcom,qcs615-venus + - const: qcom,sc7180-venus + - const: qcom,sc7180-venus power-domains: minItems: 2 diff --git a/Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.yaml index 9936f01324177..d195f1bfb23d5 100644 --- a/Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.yaml @@ -143,6 +143,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - clock-lanes - data-lanes @@ -166,6 +171,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - clock-lanes - data-lanes @@ -189,6 +199,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - clock-lanes - data-lanes @@ -212,6 +227,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - clock-lanes - data-lanes diff --git a/Documentation/devicetree/bindings/media/qcom,sdm660-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sdm660-camss.yaml index 68d8670557f55..6e6ad8390e444 100644 --- a/Documentation/devicetree/bindings/media/qcom,sdm660-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sdm660-camss.yaml @@ -121,6 +121,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -140,6 +145,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -159,6 +169,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -178,6 +193,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes diff --git a/Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml index 289494f561e58..82bf4689d3300 100644 --- a/Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml @@ -108,6 +108,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -127,6 +132,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -146,6 +156,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -165,6 +180,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes diff --git a/Documentation/devicetree/bindings/media/qcom,sm8250-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8250-camss.yaml index a372d991e6523..ebf68ff4ab961 100644 --- a/Documentation/devicetree/bindings/media/qcom,sm8250-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sm8250-camss.yaml @@ -128,6 +128,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - clock-lanes - data-lanes @@ -151,6 +156,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - clock-lanes - data-lanes @@ -174,6 +184,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - clock-lanes - data-lanes @@ -197,6 +212,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - clock-lanes - data-lanes @@ -220,6 +240,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - clock-lanes - data-lanes @@ -243,6 +268,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - clock-lanes - data-lanes diff --git a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml index e424ea84c211f..c79bf2101812d 100644 --- a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml @@ -14,12 +14,17 @@ description: The iris video processing unit is a video encode and decode accelerator present on Qualcomm platforms. -allOf: - - $ref: qcom,venus-common.yaml# - properties: compatible: - const: qcom,sm8550-iris + oneOf: + - items: + - enum: + - qcom,sa8775p-iris + - const: qcom,sm8550-iris + - enum: + - qcom,qcs8300-iris + - qcom,sm8550-iris + - qcom,sm8650-iris power-domains: maxItems: 4 @@ -49,11 +54,15 @@ properties: - const: video-mem resets: - maxItems: 1 + minItems: 1 + maxItems: 3 reset-names: + minItems: 1 items: - const: bus + - const: xo + - const: core iommus: maxItems: 2 @@ -75,6 +84,26 @@ required: - iommus - dma-coherent +allOf: + - $ref: qcom,venus-common.yaml# + - if: + properties: + compatible: + enum: + - qcom,sm8650-iris + then: + properties: + resets: + minItems: 3 + reset-names: + minItems: 3 + else: + properties: + resets: + maxItems: 1 + reset-names: + maxItems: 1 + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml new file mode 100644 index 0000000000000..113565cf2a991 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml @@ -0,0 +1,367 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,x1e80100-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm X1E80100 Camera Subsystem (CAMSS) + +maintainers: + - Bryan O'Donoghue + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,x1e80100-camss + + reg: + maxItems: 17 + + reg-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csid_wrapper + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy4 + - const: csitpg0 + - const: csitpg1 + - const: csitpg2 + - const: vfe0 + - const: vfe1 + - const: vfe_lite0 + - const: vfe_lite1 + + clocks: + maxItems: 29 + + clock-names: + items: + - const: camnoc_nrt_axi + - const: camnoc_rt_axi + - const: core_ahb + - const: cpas_ahb + - const: cpas_fast_ahb + - const: cpas_vfe0 + - const: cpas_vfe1 + - const: cpas_vfe_lite + - const: cphy_rx_clk_src + - const: csid + - const: csid_csiphy_rx + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy4 + - const: csiphy4_timer + - const: gcc_axi_hf + - const: gcc_axi_sf + - const: vfe0 + - const: vfe0_fast_ahb + - const: vfe1 + - const: vfe1_fast_ahb + - const: vfe_lite + - const: vfe_lite_ahb + - const: vfe_lite_cphy_rx + - const: vfe_lite_csid + + interrupts: + maxItems: 13 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy4 + - const: vfe0 + - const: vfe1 + - const: vfe_lite0 + - const: vfe_lite1 + + interconnects: + maxItems: 4 + + interconnect-names: + items: + - const: ahb + - const: hf_mnoc + - const: sf_mnoc + - const: sf_icp_mnoc + + iommus: + maxItems: 8 + + power-domains: + items: + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. + - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller. + + power-domain-names: + items: + - const: ife0 + - const: ife1 + - const: top + + vdd-csiphy-0p8-supply: + description: + Phandle to a 0.8V regulator supply to a PHY. + + vdd-csiphy-1p2-supply: + description: + Phandle to 1.8V regulator supply to a PHY. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + patternProperties: + "^port@[0-3]+$": + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + + description: + Input port for receiving CSI data from a CSIPHY. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - interconnects + - interconnect-names + - iommus + - power-domains + - power-domain-names + - vdd-csiphy-0p8-supply + - vdd-csiphy-1p2-supply + - ports + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + camss: isp@acb6000 { + compatible = "qcom,x1e80100-camss"; + + reg = <0 0x0acb7000 0 0x2000>, + <0 0x0acb9000 0 0x2000>, + <0 0x0acbb000 0 0x2000>, + <0 0x0acc6000 0 0x1000>, + <0 0x0acca000 0 0x1000>, + <0 0x0acb6000 0 0x1000>, + <0 0x0ace4000 0 0x1000>, + <0 0x0ace6000 0 0x1000>, + <0 0x0ace8000 0 0x1000>, + <0 0x0acec000 0 0x4000>, + <0 0x0acf6000 0 0x1000>, + <0 0x0acf7000 0 0x1000>, + <0 0x0acf8000 0 0x1000>, + <0 0x0ac62000 0 0x4000>, + <0 0x0ac71000 0 0x4000>, + <0 0x0acc7000 0 0x2000>, + <0 0x0accb000 0 0x2000>; + + reg-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csid_wrapper", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy4", + "csitpg0", + "csitpg1", + "csitpg2", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + + clock-names = "camnoc_nrt_axi", + "camnoc_rt_axi", + "core_ahb", + "cpas_ahb", + "cpas_fast_ahb", + "cpas_vfe0", + "cpas_vfe1", + "cpas_vfe_lite", + "cphy_rx_clk_src", + "csid", + "csid_csiphy_rx", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy4", + "csiphy4_timer", + "gcc_axi_hf", + "gcc_axi_sf", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + + interrupt-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy4", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + interconnect-names = "ahb", + "hf_mnoc", + "sf_mnoc", + "sf_icp_mnoc"; + + iommus = <&apps_smmu 0x800 0x60>, + <&apps_smmu 0x860 0x60>, + <&apps_smmu 0x1800 0x60>, + <&apps_smmu 0x1860 0x60>, + <&apps_smmu 0x18e0 0x00>, + <&apps_smmu 0x1980 0x20>, + <&apps_smmu 0x1900 0x00>, + <&apps_smmu 0x19a0 0x20>; + + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, + <&camcc CAM_CC_IFE_1_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + + power-domain-names = "ife0", + "ife1", + "top"; + + vdd-csiphy-0p8-supply = <&csiphy_0p8_supply>; + vdd-csiphy-1p2-supply = <&csiphy_1p2_supply>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + csiphy_ep0: endpoint { + clock-lanes = <7>; + data-lanes = <0 1>; + remote-endpoint = <&sensor_ep>; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/renesas,fcp.yaml b/Documentation/devicetree/bindings/media/renesas,fcp.yaml index f94dacd962782..7bf1266223e82 100644 --- a/Documentation/devicetree/bindings/media/renesas,fcp.yaml +++ b/Documentation/devicetree/bindings/media/renesas,fcp.yaml @@ -30,14 +30,24 @@ properties: - renesas,r9a07g043u-fcpvd # RZ/G2UL - renesas,r9a07g044-fcpvd # RZ/G2{L,LC} - renesas,r9a07g054-fcpvd # RZ/V2L + - renesas,r9a09g057-fcpvd # RZ/V2H(P) - const: renesas,fcpv # Generic FCP for VSP fallback reg: maxItems: 1 - clocks: true + clocks: + minItems: 1 + items: + - description: Main clock + - description: Register access clock + - description: Video clock - clock-names: true + clock-names: + items: + - const: aclk + - const: pclk + - const: vclk iommus: maxItems: 1 @@ -66,18 +76,11 @@ allOf: - renesas,r9a07g043u-fcpvd - renesas,r9a07g044-fcpvd - renesas,r9a07g054-fcpvd + - renesas,r9a09g057-fcpvd then: properties: clocks: - items: - - description: Main clock - - description: Register access clock - - description: Video clock - clock-names: - items: - - const: aclk - - const: pclk - - const: vclk + minItems: 3 required: - clock-names else: diff --git a/Documentation/devicetree/bindings/media/renesas,isp.yaml b/Documentation/devicetree/bindings/media/renesas,isp.yaml index c4de4555b7535..d25e020f5e5ec 100644 --- a/Documentation/devicetree/bindings/media/renesas,isp.yaml +++ b/Documentation/devicetree/bindings/media/renesas,isp.yaml @@ -25,19 +25,55 @@ properties: - renesas,r8a779h0-isp # V4M - const: renesas,rcar-gen4-isp # Generic R-Car Gen4 reg: - maxItems: 1 + minItems: 1 + maxItems: 2 + + reg-names: + minItems: 1 + items: + - const: cs + - const: core interrupts: - maxItems: 1 + minItems: 1 + maxItems: 2 + + interrupt-names: + minItems: 1 + items: + - const: cs + - const: core clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: cs + - const: core power-domains: maxItems: 1 resets: - maxItems: 1 + minItems: 1 + maxItems: 2 + + reset-names: + minItems: 1 + items: + - const: cs + - const: core + + renesas,vspx: + $ref: /schemas/types.yaml#/definitions/phandle + description: + A phandle to the companion VSPX responsible for the Streaming Bridge + functionality. The Streaming Bridge is responsible for feeding image + and configuration data to the ISP when operating in memory-to-memory + mode. ports: $ref: /schemas/graph.yaml#/properties/ports @@ -103,10 +139,14 @@ properties: required: - compatible - reg + - reg-names - interrupts + - interrupt-names - clocks + - clock-names - power-domains - resets + - reset-names - ports additionalProperties: false @@ -119,11 +159,18 @@ examples: isp1: isp@fed20000 { compatible = "renesas,r8a779a0-isp", "renesas,rcar-gen4-isp"; - reg = <0xfed20000 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 613>; + reg = <0xfed20000 0x10000>, <0xfee00000 0x100000>; + reg-names = "cs", "core"; + interrupts = , + ; + interrupt-names = "cs", "core"; + clocks = <&cpg CPG_MOD 613>, <&cpg CPG_MOD 17>; + clock-names = "cs", "core"; power-domains = <&sysc R8A779A0_PD_A3ISP01>; - resets = <&cpg 613>; + resets = <&cpg 613>, <&cpg 17>; + reset-names = "cs", "core"; + + renesas,vspx = <&vspx1>; ports { #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml b/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml index bc1245127025e..47e18690fa570 100644 --- a/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml +++ b/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml @@ -17,24 +17,43 @@ description: properties: compatible: - items: - - enum: - - renesas,r9a07g043-cru # RZ/G2UL - - renesas,r9a07g044-cru # RZ/G2{L,LC} - - renesas,r9a07g054-cru # RZ/V2L - - const: renesas,rzg2l-cru + oneOf: + - items: + - enum: + - renesas,r9a07g043-cru # RZ/G2UL + - renesas,r9a07g044-cru # RZ/G2{L,LC} + - renesas,r9a07g054-cru # RZ/V2L + - const: renesas,rzg2l-cru + - const: renesas,r9a09g047-cru # RZ/G3E reg: maxItems: 1 interrupts: - maxItems: 3 + oneOf: + - items: + - description: CRU Interrupt for image_conv + - description: CRU Interrupt for image_conv_err + - description: CRU AXI master error interrupt + - items: + - description: CRU Interrupt for image_conv + - description: CRU AXI master error interrupt + - description: CRU Video Data AXI Master Address 0 Write End interrupt + - description: CRU Statistics data AXI master addr 0 write end interrupt + - description: CRU Video statistics data AXI master addr 0 write end interrupt interrupt-names: - items: - - const: image_conv - - const: image_conv_err - - const: axi_mst_err + oneOf: + - items: + - const: image_conv + - const: image_conv_err + - const: axi_mst_err + - items: + - const: image_conv + - const: axi_mst_err + - const: vd_addr_wend + - const: sd_addr_wend + - const: vsd_addr_wend clocks: items: @@ -109,6 +128,10 @@ allOf: - renesas,r9a07g054-cru then: properties: + interrupts: + maxItems: 3 + interrupt-names: + maxItems: 3 ports: required: - port@0 @@ -122,10 +145,30 @@ allOf: - renesas,r9a07g043-cru then: properties: + interrupts: + maxItems: 3 + interrupt-names: + maxItems: 3 ports: properties: port@0: false + required: + - port@1 + - if: + properties: + compatible: + contains: + const: renesas,r9a09g047-cru + then: + properties: + interrupts: + minItems: 5 + interrupt-names: + minItems: 5 + ports: + properties: + port@0: false required: - port@1 diff --git a/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml b/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml index 7faa12fecd5bb..c5c511c9f0db2 100644 --- a/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml +++ b/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml @@ -17,12 +17,17 @@ description: properties: compatible: - items: - - enum: - - renesas,r9a07g043-csi2 # RZ/G2UL - - renesas,r9a07g044-csi2 # RZ/G2{L,LC} - - renesas,r9a07g054-csi2 # RZ/V2L - - const: renesas,rzg2l-csi2 + oneOf: + - items: + - enum: + - renesas,r9a07g043-csi2 # RZ/G2UL + - renesas,r9a07g044-csi2 # RZ/G2{L,LC} + - renesas,r9a07g054-csi2 # RZ/V2L + - const: renesas,rzg2l-csi2 + - items: + - const: renesas,r9a09g047-csi2 # RZ/G3E + - const: renesas,r9a09g057-csi2 + - const: renesas,r9a09g057-csi2 # RZ/V2H(P) reg: maxItems: 1 @@ -31,16 +36,24 @@ properties: maxItems: 1 clocks: - items: - - description: Internal clock for connecting CRU and MIPI - - description: CRU Main clock - - description: CRU Register access clock + oneOf: + - items: + - description: Internal clock for connecting CRU and MIPI + - description: CRU Main clock + - description: CRU Register access clock + - items: + - description: CRU Main clock + - description: CRU Register access clock clock-names: - items: - - const: system - - const: video - - const: apb + oneOf: + - items: + - const: system + - const: video + - const: apb + - items: + - const: video + - const: apb power-domains: maxItems: 1 @@ -48,7 +61,7 @@ properties: resets: items: - description: CRU_PRESETN reset terminal - - description: CRU_CMN_RSTB reset terminal + - description: D-PHY reset (CRU_CMN_RSTB or CRU_n_S_RESETN) reset-names: items: @@ -101,6 +114,25 @@ required: - reset-names - ports +allOf: + - if: + properties: + compatible: + contains: + const: renesas,r9a09g057-csi2 + then: + properties: + clocks: + maxItems: 2 + clock-names: + maxItems: 2 + else: + properties: + clocks: + minItems: 3 + clock-names: + minItems: 3 + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/media/renesas,vsp1.yaml b/Documentation/devicetree/bindings/media/renesas,vsp1.yaml index 1a03e67462a4f..fcf7219b1f40a 100644 --- a/Documentation/devicetree/bindings/media/renesas,vsp1.yaml +++ b/Documentation/devicetree/bindings/media/renesas,vsp1.yaml @@ -25,6 +25,7 @@ properties: - enum: - renesas,r9a07g043u-vsp2 # RZ/G2UL - renesas,r9a07g054-vsp2 # RZ/V2L + - renesas,r9a09g057-vsp2 # RZ/V2H(P) - const: renesas,r9a07g044-vsp2 # RZ/G2L fallback reg: @@ -33,8 +34,18 @@ properties: interrupts: maxItems: 1 - clocks: true - clock-names: true + clocks: + minItems: 1 + items: + - description: Main clock + - description: Register access clock + - description: Video clock + + clock-names: + items: + - const: aclk + - const: pclk + - const: vclk power-domains: maxItems: 1 @@ -78,15 +89,7 @@ allOf: then: properties: clocks: - items: - - description: Main clock - - description: Register access clock - - description: Video clock - clock-names: - items: - - const: aclk - - const: pclk - - const: vclk + minItems: 3 required: - clock-names else: diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml index 2f36ac23604c5..0762e0ff66ef0 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml @@ -33,6 +33,7 @@ properties: - mediatek,mt2712-smi-common - mediatek,mt6779-smi-common - mediatek,mt6795-smi-common + - mediatek,mt6893-smi-common - mediatek,mt8167-smi-common - mediatek,mt8173-smi-common - mediatek,mt8183-smi-common diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml index 2381660b324cb..2e7fac4b50945 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml @@ -21,6 +21,7 @@ properties: - mediatek,mt2712-smi-larb - mediatek,mt6779-smi-larb - mediatek,mt6795-smi-larb + - mediatek,mt6893-smi-larb - mediatek,mt8167-smi-larb - mediatek,mt8173-smi-larb - mediatek,mt8183-smi-larb diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas,rzg3e-xspi.yaml b/Documentation/devicetree/bindings/memory-controllers/renesas,rzg3e-xspi.yaml new file mode 100644 index 0000000000000..2bfe63ec62dcb --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/renesas,rzg3e-xspi.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/renesas,rzg3e-xspi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Expanded Serial Peripheral Interface (xSPI) + +maintainers: + - Biju Das + +description: | + Renesas xSPI allows a SPI flash connected to the SoC to be accessed via + the memory-mapping or the manual command mode. + + The flash chip itself should be represented by a subnode of the XSPI node. + The flash interface is selected based on the "compatible" property of this + subnode: + - "jedec,spi-nor"; + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +properties: + compatible: + const: renesas,r9a09g047-xspi # RZ/G3E + + reg: + items: + - description: xSPI registers + - description: direct mapping area + + reg-names: + items: + - const: regs + - const: dirmap + + interrupts: + items: + - description: Interrupt pulse signal by factors excluding errors + - description: Interrupt pulse signal by error factors + + interrupt-names: + items: + - const: pulse + - const: err_pulse + + clocks: + items: + - description: AHB clock + - description: AXI clock + - description: SPI clock + - description: Double speed SPI clock + + clock-names: + items: + - const: ahb + - const: axi + - const: spi + - const: spix2 + + power-domains: + maxItems: 1 + + resets: + items: + - description: Hardware reset + - description: AXI reset + + reset-names: + items: + - const: hresetn + - const: aresetn + + renesas,xspi-cs-addr-sys: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + Phandle to the system controller (sys) that allows to configure + xSPI CS0 and CS1 addresses. + +patternProperties: + "flash@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + contains: + const: jedec,spi-nor + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + - resets + - reset-names + - '#address-cells' + - '#size-cells' + +unevaluatedProperties: false + +examples: + - | + #include + #include + + spi@11030000 { + compatible = "renesas,r9a09g047-xspi"; + reg = <0x11030000 0x10000>, <0x20000000 0x10000000>; + reg-names = "regs", "dirmap"; + interrupts = , + ; + interrupt-names = "pulse", "err_pulse"; + clocks = <&cpg CPG_MOD 0x9f>, <&cpg CPG_MOD 0xa0>, + <&cpg CPG_CORE 9>, <&cpg CPG_MOD 0xa1>; + clock-names = "ahb", "axi", "spi", "spix2"; + power-domains = <&cpg>; + resets = <&cpg 0xa3>, <&cpg 0xa4>; + reset-names = "hresetn", "aresetn"; + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/st,stm32mp25-omm.yaml b/Documentation/devicetree/bindings/memory-controllers/st,stm32mp25-omm.yaml new file mode 100644 index 0000000000000..344878db88188 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/st,stm32mp25-omm.yaml @@ -0,0 +1,226 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/st,stm32mp25-omm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STM32 Octo Memory Manager (OMM) + +maintainers: + - Patrice Chotard + +description: | + The STM32 Octo Memory Manager is a low-level interface that enables an + efficient OCTOSPI pin assignment with a full I/O matrix (before alternate + function map) and multiplex of single/dual/quad/octal SPI interfaces over + the same bus. It Supports up to: + - Two single/dual/quad/octal SPI interfaces + - Two ports for pin assignment + +properties: + compatible: + const: st,stm32mp25-omm + + "#address-cells": + const: 2 + + "#size-cells": + const: 1 + + ranges: + description: | + Reflects the memory layout per OSPI instance. + Format: + 0 + minItems: 2 + maxItems: 2 + + reg: + items: + - description: OMM registers + - description: OMM memory map area + + reg-names: + items: + - const: regs + - const: memory_map + + memory-region: + description: + Memory region shared between the 2 OCTOSPI instance. + One or two phandle to a node describing a memory mapped region + depending of child number. + minItems: 1 + maxItems: 2 + + memory-region-names: + description: + Identify to which OSPI instance the memory region belongs to. + items: + enum: [ospi1, ospi2] + minItems: 1 + maxItems: 2 + + clocks: + maxItems: 3 + + clock-names: + items: + - const: omm + - const: ospi1 + - const: ospi2 + + resets: + maxItems: 3 + + reset-names: + items: + - const: omm + - const: ospi1 + - const: ospi2 + + access-controllers: + maxItems: 1 + + power-domains: + maxItems: 1 + + st,syscfg-amcr: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + The Address Mapping Control Register (AMCR) is used to split the 256MB + memory map area shared between the 2 OSPI instance. The Octo Memory + Manager sets the AMCR depending of the memory-region configuration. + The memory split bitmask description is: + - 000: OCTOSPI1 (256 Mbytes), OCTOSPI2 unmapped + - 001: OCTOSPI1 (192 Mbytes), OCTOSPI2 (64 Mbytes) + - 010: OCTOSPI1 (128 Mbytes), OCTOSPI2 (128 Mbytes) + - 011: OCTOSPI1 (64 Mbytes), OCTOSPI2 (192 Mbytes) + - 1xx: OCTOSPI1 unmapped, OCTOSPI2 (256 Mbytes) + items: + - items: + - description: phandle to syscfg + - description: register offset within syscfg + - description: register bitmask for memory split + + st,omm-req2ack-ns: + description: + In multiplexed mode (MUXEN = 1), this field defines the time in + nanoseconds between two transactions. + default: 0 + + st,omm-cssel-ovr: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Configure the chip select selector override for the 2 OCTOSPIs. + - 0: OCTOSPI1 chip select send to NCS1 OCTOSPI2 chip select send to NCS1 + - 1: OCTOSPI1 chip select send to NCS2 OCTOSPI2 chip select send to NCS1 + - 2: OCTOSPI1 chip select send to NCS1 OCTOSPI2 chip select send to NCS2 + - 3: OCTOSPI1 chip select send to NCS2 OCTOSPI2 chip select send to NCS2 + minimum: 0 + maximum: 3 + default: 0 + + st,omm-mux: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Configure the muxing between the 2 OCTOSPIs busses and the 2 output ports. + - 0: direct mode + - 1: mux OCTOSPI1 and OCTOSPI2 to port 1 + - 2: swapped mode + - 3: mux OCTOSPI1 and OCTOSPI2 to port 2 + minimum: 0 + maximum: 3 + default: 0 + +patternProperties: + ^spi@[0-9]: + type: object + $ref: /schemas/spi/st,stm32mp25-ospi.yaml# + description: Required spi child node + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - clocks + - clock-names + - resets + - reset-names + - st,syscfg-amcr + - ranges + +additionalProperties: false + +examples: + - | + #include + #include + #include + ommanager@40500000 { + compatible = "st,stm32mp25-omm"; + reg = <0x40500000 0x400>, <0x60000000 0x10000000>; + reg-names = "regs", "memory_map"; + ranges = <0 0 0x40430000 0x400>, + <1 0 0x40440000 0x400>; + memory-region = <&mm_ospi1>, <&mm_ospi2>; + memory-region-names = "ospi1", "ospi2"; + pinctrl-0 = <&ospi_port1_clk_pins_a + &ospi_port1_io03_pins_a + &ospi_port1_cs0_pins_a>; + pinctrl-1 = <&ospi_port1_clk_sleep_pins_a + &ospi_port1_io03_sleep_pins_a + &ospi_port1_cs0_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + clocks = <&rcc CK_BUS_OSPIIOM>, + <&scmi_clk CK_SCMI_OSPI1>, + <&scmi_clk CK_SCMI_OSPI2>; + clock-names = "omm", "ospi1", "ospi2"; + resets = <&rcc OSPIIOM_R>, + <&scmi_reset RST_SCMI_OSPI1>, + <&scmi_reset RST_SCMI_OSPI2>; + reset-names = "omm", "ospi1", "ospi2"; + access-controllers = <&rifsc 111>; + power-domains = <&CLUSTER_PD>; + #address-cells = <2>; + #size-cells = <1>; + st,syscfg-amcr = <&syscfg 0x2c00 0x7>; + st,omm-req2ack-ns = <0>; + st,omm-mux = <0>; + st,omm-cssel-ovr = <0>; + + spi@0 { + compatible = "st,stm32mp25-ospi"; + reg = <0 0 0x400>; + memory-region = <&mm_ospi1>; + interrupts = ; + dmas = <&hpdma 2 0x62 0x00003121 0x0>, + <&hpdma 2 0x42 0x00003112 0x0>; + dma-names = "tx", "rx"; + clocks = <&scmi_clk CK_SCMI_OSPI1>; + resets = <&scmi_reset RST_SCMI_OSPI1>, <&scmi_reset RST_SCMI_OSPI1DLL>; + access-controllers = <&rifsc 74>; + power-domains = <&CLUSTER_PD>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-dlyb = <&syscfg 0x1000>; + }; + + spi@1 { + compatible = "st,stm32mp25-ospi"; + reg = <1 0 0x400>; + memory-region = <&mm_ospi1>; + interrupts = ; + dmas = <&hpdma 3 0x62 0x00003121 0x0>, + <&hpdma 3 0x42 0x00003112 0x0>; + dma-names = "tx", "rx"; + clocks = <&scmi_clk CK_KER_OSPI2>; + resets = <&scmi_reset RST_SCMI_OSPI2>, <&scmi_reset RST_SCMI_OSPI1DLL>; + access-controllers = <&rifsc 75>; + power-domains = <&CLUSTER_PD>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-dlyb = <&syscfg 0x1000>; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml index c800d5e53b651..5eccd10d95ce5 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml +++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml @@ -66,8 +66,15 @@ patternProperties: - compatible '^interrupt-controller@[0-9a-f]+$': - description: See Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2xxx-scu-ic.txt type: object + additionalProperties: true + properties: + compatible: + contains: + enum: + - aspeed,ast2500-scu-ic + - aspeed,ast2600-scu-ic0 + - aspeed,ast2600-scu-ic1 '^silicon-id@[0-9a-f]+$': description: Unique hardware silicon identifiers within the SoC diff --git a/Documentation/devicetree/bindings/mfd/maxim,max77759.yaml b/Documentation/devicetree/bindings/mfd/maxim,max77759.yaml new file mode 100644 index 0000000000000..525de9ab3c2b7 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/maxim,max77759.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/maxim,max77759.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim Integrated MAX77759 PMIC for USB Type-C applications + +maintainers: + - André Draszik + +description: | + This is a part of device tree bindings for the MAX77759 companion Power + Management IC for USB Type-C applications. + + The MAX77759 includes Battery Charger, Fuel Gauge, temperature sensors, USB + Type-C Port Controller (TCPC), NVMEM, and a GPIO expander. + +properties: + compatible: + const: maxim,max77759 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + reg: + maxItems: 1 + + gpio: + $ref: /schemas/gpio/maxim,max77759-gpio.yaml + + nvmem-0: + $ref: /schemas/nvmem/maxim,max77759-nvmem.yaml + +required: + - compatible + - interrupts + - reg + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@66 { + compatible = "maxim,max77759"; + reg = <0x66>; + interrupts-extended = <&gpa8 3 IRQ_TYPE_LEVEL_LOW>; + + interrupt-controller; + #interrupt-cells = <2>; + + gpio { + compatible = "maxim,max77759-gpio"; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + nvmem-0 { + compatible = "maxim,max77759-nvmem"; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + reboot-mode@0 { + reg = <0x0 0x4>; + }; + + boot-reason@4 { + reg = <0x4 0x4>; + }; + + shutdown-user-flag@8 { + reg = <0x8 0x1>; + }; + + rsoc@10 { + reg = <0xa 0x2>; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml index 7e7225aadae32..14ae3f00ef7e0 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml @@ -41,6 +41,7 @@ properties: - qcom,sm8450-tcsr - qcom,tcsr-apq8064 - qcom,tcsr-apq8084 + - qcom,tcsr-ipq5018 - qcom,tcsr-ipq5332 - qcom,tcsr-ipq5424 - qcom,tcsr-ipq6018 diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml index a85137add6689..471373ad0cfb6 100644 --- a/Documentation/devicetree/bindings/mips/cpus.yaml +++ b/Documentation/devicetree/bindings/mips/cpus.yaml @@ -50,6 +50,7 @@ properties: device_type: true allOf: + - $ref: /schemas/opp/opp-v1.yaml# - if: properties: compatible: @@ -68,7 +69,7 @@ required: - compatible - reg -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/misc/ti,fpc202.yaml b/Documentation/devicetree/bindings/misc/ti,fpc202.yaml new file mode 100644 index 0000000000000..a8cb10f2d0df3 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/ti,fpc202.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/ti,fpc202.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI FPC202 dual port controller with expanded IOs + +maintainers: + - Romain Gantois + +allOf: + - $ref: /schemas/i2c/i2c-atr.yaml# + +properties: + compatible: + const: ti,fpc202 + + reg: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 2 + + enable-gpios: + description: + Specifier for the GPIO connected to the EN pin. + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + "^i2c@[0-1]$": + $ref: /schemas/i2c/i2c-controller.yaml# + description: Downstream device ports 0 and 1 + + properties: + reg: + maxItems: 1 + description: + Downstream port ID + + required: + - "#address-cells" + - "#size-cells" + - reg + + unevaluatedProperties: false + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + - "#address-cells" + - "#size-cells" + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + i2c-atr@f { + compatible = "ti,fpc202"; + reg = <0xf>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml index 9075add020bf0..8e79de97b242a 100644 --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml @@ -38,6 +38,15 @@ allOf: - items: - const: clk_out_sd1 - const: clk_in_sd1 + - if: + properties: + compatible: + contains: + const: renesas,rzn1-sdhci + then: + properties: + interrupts: + minItems: 2 properties: compatible: @@ -45,6 +54,10 @@ properties: - const: arasan,sdhci-8.9a # generic Arasan SDHCI 8.9a PHY - const: arasan,sdhci-4.9a # generic Arasan SDHCI 4.9a PHY - const: arasan,sdhci-5.1 # generic Arasan SDHCI 5.1 PHY + - items: + - const: renesas,r9a06g032-sdhci # Renesas RZ/N1D SoC + - const: renesas,rzn1-sdhci # Renesas RZ/N1 family + - const: arasan,sdhci-8.9a - items: - const: rockchip,rk3399-sdhci-5.1 # rk3399 eMMC PHY - const: arasan,sdhci-5.1 @@ -109,7 +122,14 @@ properties: - const: gate interrupts: - maxItems: 1 + minItems: 1 + maxItems: 2 + + interrupt-names: + minItems: 1 + items: + - const: int + - const: wakeup phys: maxItems: 1 diff --git a/Documentation/devicetree/bindings/mmc/fsl,esdhc.yaml b/Documentation/devicetree/bindings/mmc/fsl,esdhc.yaml index b86ffb53b18b5..62087cf920df8 100644 --- a/Documentation/devicetree/bindings/mmc/fsl,esdhc.yaml +++ b/Documentation/devicetree/bindings/mmc/fsl,esdhc.yaml @@ -24,6 +24,7 @@ properties: - fsl,t1040-esdhc - fsl,t4240-esdhc - fsl,ls1012a-esdhc + - fsl,ls1021a-esdhc - fsl,ls1028a-esdhc - fsl,ls1088a-esdhc - fsl,ls1043a-esdhc diff --git a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml index 3f48d8292d5be..ee2ddef363690 100644 --- a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml @@ -52,9 +52,14 @@ properties: - const: core - const: axi + dma-coherent: true + interrupts: maxItems: 1 + iommus: + maxItems: 1 + marvell,pad-type: $ref: /schemas/types.yaml#/definitions/string enum: @@ -142,7 +147,7 @@ properties: This property provides the re-tuning counter. allOf: - - $ref: mmc-controller.yaml# + - $ref: sdhci-common.yaml# - if: properties: compatible: @@ -164,26 +169,6 @@ allOf: marvell,pad-type: false - - if: - properties: - compatible: - contains: - enum: - - marvell,armada-cp110-sdhci - - marvell,armada-ap807-sdhci - - marvell,armada-ap806-sdhci - - then: - properties: - clocks: - minItems: 2 - - clock-names: - items: - - const: core - - const: axi - - required: - compatible - reg diff --git a/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt b/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt deleted file mode 100644 index f064528effed3..0000000000000 --- a/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt +++ /dev/null @@ -1,29 +0,0 @@ -* Microchip PIC32 SDHCI Controller - -This file documents differences between the core properties in mmc.txt -and the properties used by the sdhci-pic32 driver. - -Required properties: -- compatible: Should be "microchip,pic32mzda-sdhci" -- interrupts: Should contain interrupt -- clock-names: Should be "base_clk", "sys_clk". - See: Documentation/devicetree/bindings/resource-names.txt -- clocks: Phandle to the clock. - See: Documentation/devicetree/bindings/clock/clock-bindings.txt -- pinctrl-names: A pinctrl state names "default" must be defined. -- pinctrl-0: Phandle referencing pin configuration of the SDHCI controller. - See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - -Example: - - sdhci@1f8ec000 { - compatible = "microchip,pic32mzda-sdhci"; - reg = <0x1f8ec000 0x100>; - interrupts = <191 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rootclk REF4CLK>, <&rootclk PB5CLK>; - clock-names = "base_clk", "sys_clk"; - bus-width = <4>; - cap-sd-highspeed; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhc1>; - }; diff --git a/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.yaml b/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.yaml new file mode 100644 index 0000000000000..ca0ca7df9ee99 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/microchip,sdhci-pic32.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PIC32 SDHI Controller + +description: + The Microchip PIC32 family of microcontrollers (MCUs) includes models with + Secure Digital Host Controller Interface (SDHCI) controllers, allowing them + to interface with Secure Digital (SD) cards. This interface is used for reading, + writing, and managing data on SD cards, enabling storage and data transfer + capabilities in embedded systems. + +allOf: + - $ref: mmc-controller.yaml + +maintainers: + - Ulf Hansson + +properties: + compatible: + const: microchip,pic32mzda-sdhci + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: base_clk + - const: sys_clk + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - pinctrl-names + - pinctrl-0 + +unevaluatedProperties: false + +examples: + - | + #include + #include + mmc@1f8ec000 { + compatible = "microchip,pic32mzda-sdhci"; + reg = <0x1f8ec000 0x100>; + interrupts = <191 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rootclk REF4CLK>, <&rootclk PB5CLK>; + clock-names = "base_clk", "sys_clk"; + bus-width = <4>; + cap-sd-highspeed; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhc1>; + }; +... diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml index 0debccbd6519c..6dd26ad314916 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml @@ -32,6 +32,7 @@ properties: - const: mediatek,mt2701-mmc - items: - enum: + - mediatek,mt6893-mmc - mediatek,mt8186-mmc - mediatek,mt8188-mmc - mediatek,mt8192-mmc @@ -299,6 +300,7 @@ allOf: properties: compatible: enum: + - mediatek,mt6893-mmc - mediatek,mt8186-mmc - mediatek,mt8188-mmc - mediatek,mt8195-mmc diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml index 773baa6c2656c..7563623876fc0 100644 --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml @@ -69,7 +69,9 @@ properties: - renesas,sdhi-r9a09g011 # RZ/V2M - const: renesas,rzg2l-sdhi - items: - - const: renesas,sdhi-r9a09g047 # RZ/G3E + - enum: + - renesas,sdhi-r9a09g047 # RZ/G3E + - renesas,sdhi-r9a09g056 # RZ/V2N - const: renesas,sdhi-r9a09g057 # RZ/V2H(P) reg: diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml index eed9063e9bb35..2b2cbce2458b7 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -60,6 +60,7 @@ properties: - qcom,sm6125-sdhci - qcom,sm6350-sdhci - qcom,sm6375-sdhci + - qcom,sm7150-sdhci - qcom,sm8150-sdhci - qcom,sm8250-sdhci - qcom,sm8350-sdhci diff --git a/Documentation/devicetree/bindings/mmc/sdhci.txt b/Documentation/devicetree/bindings/mmc/sdhci.txt deleted file mode 100644 index 0e9923a64024f..0000000000000 --- a/Documentation/devicetree/bindings/mmc/sdhci.txt +++ /dev/null @@ -1,13 +0,0 @@ -The properties specific for SD host controllers. For properties shared by MMC -host controllers refer to the mmc[1] bindings. - - [1] Documentation/devicetree/bindings/mmc/mmc.txt - -Optional properties: -- sdhci-caps-mask: The sdhci capabilities register is incorrect. This 64bit - property corresponds to the bits in the sdhci capability register. If the bit - is on in the mask then the bit is incorrect in the register and should be - turned off, before applying sdhci-caps. -- sdhci-caps: The sdhci capabilities register is incorrect. This 64bit - property corresponds to the bits in the sdhci capability register. If the - bit is on in the property then the bit should be turned on. diff --git a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml index e6e604072d3c6..f882219a0a26a 100644 --- a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml @@ -19,6 +19,9 @@ properties: - rockchip,rk3562-dwcmshc - rockchip,rk3576-dwcmshc - const: rockchip,rk3588-dwcmshc + - items: + - const: sophgo,sg2044-dwcmshc + - const: sophgo,sg2042-dwcmshc - enum: - rockchip,rk3568-dwcmshc - rockchip,rk3588-dwcmshc @@ -117,10 +120,6 @@ allOf: required: - power-domains - else: - properties: - power-domains: false - unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml new file mode 100644 index 0000000000000..13d9382058fbc --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/spacemit,sdhci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT SDHCI Controller + +maintainers: + - Yixun Lan + +allOf: + - $ref: mmc-controller.yaml# + +properties: + compatible: + const: spacemit,k1-sdhci + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: core clock, used by internal controller + - description: io clock, output for SD, SDIO, eMMC device + + clock-names: + items: + - const: core + - const: io + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + mmc@d4281000 { + compatible = "spacemit,k1-sdhci"; + reg = <0xd4281000 0x200>; + interrupts = <101>; + interrupt-parent = <&plic>; + clocks = <&clk_apmu 10>, <&clk_apmu 13>; + clock-names = "core", "io"; + }; diff --git a/Documentation/devicetree/bindings/mmc/vt8500-sdmmc.txt b/Documentation/devicetree/bindings/mmc/vt8500-sdmmc.txt deleted file mode 100644 index d7fb6abb3eb8c..0000000000000 --- a/Documentation/devicetree/bindings/mmc/vt8500-sdmmc.txt +++ /dev/null @@ -1,23 +0,0 @@ -* Wondermedia WM8505/WM8650 SD/MMC Host Controller - -This file documents differences between the core properties described -by mmc.txt and the properties used by the wmt-sdmmc driver. - -Required properties: -- compatible: Should be "wm,wm8505-sdhc". -- interrupts: Two interrupts are required - regular irq and dma irq. - -Optional properties: -- sdon-inverted: SD_ON bit is inverted on the controller - -Examples: - -sdhc@d800a000 { - compatible = "wm,wm8505-sdhc"; - reg = <0xd800a000 0x1000>; - interrupts = <20 21>; - clocks = <&sdhc>; - bus-width = <4>; - sdon-inverted; -}; - diff --git a/Documentation/devicetree/bindings/mmc/wm,wm8505-sdhc.yaml b/Documentation/devicetree/bindings/mmc/wm,wm8505-sdhc.yaml new file mode 100644 index 0000000000000..5b55174e90883 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/wm,wm8505-sdhc.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/wm,wm8505-sdhc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: WonderMedia SoC SDHCI Controller + +maintainers: + - Alexey Charkov + +allOf: + - $ref: mmc-controller.yaml# + +properties: + compatible: + oneOf: + - const: wm,wm8505-sdhc + - items: + - const: wm,wm8650-sdhc + - const: wm,wm8505-sdhc + - items: + - const: wm,wm8750-sdhc + - const: wm,wm8505-sdhc + - items: + - const: wm,wm8850-sdhc + - const: wm,wm8505-sdhc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + items: + - description: SDMMC controller interrupt + - description: SDMMC controller DMA interrupt + + sdon-inverted: + type: boolean + description: All chips before (not including) WM8505 rev. A2 treated their + "clock stop" bit (register offset 0x08 a.k.a. SDMMC_BUSMODE, bit 0x10) + as "set 1 to disable SD clock", while all the later versions treated it + as "set 0 to disable SD clock". Set this property for later versions of + wm,wm8505-sdhc. On wm,wm8650-sdhc and later this property is implied and + does not need to be set explicitly + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + mmc@d800a000 { + compatible = "wm,wm8505-sdhc"; + reg = <0xd800a000 0x1000>; + interrupts = <20>, <21>; + clocks = <&sdhc>; + bus-width = <4>; + sdon-inverted; + }; diff --git a/Documentation/devicetree/bindings/net/aeonsemi,as21xxx.yaml b/Documentation/devicetree/bindings/net/aeonsemi,as21xxx.yaml new file mode 100644 index 0000000000000..69eb29dc4d7b8 --- /dev/null +++ b/Documentation/devicetree/bindings/net/aeonsemi,as21xxx.yaml @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/aeonsemi,as21xxx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aeonsemi AS21XXX Ethernet PHY + +maintainers: + - Christian Marangi + +description: | + Aeonsemi AS21xxx Ethernet PHYs requires a firmware to be loaded to actually + work. The same firmware is compatible with various PHYs of the same family. + + A PHY with not firmware loaded will be exposed on the MDIO bus with ID + 0x7500 0x7500 or 0x7500 0x9410 on C45 registers. + + This can be done and is implemented by OEM in 2 different way: + - Attached SPI flash directly to the PHY with the firmware. The PHY + will self load the firmware in the presence of this configuration. + - Manually provided firmware loaded from a file in the filesystem. + + Each PHY can support up to 5 LEDs. + + AS2xxx PHY Name logic: + + AS21x1xxB1 + ^ ^^ + | |J: Supports SyncE/PTP + | |P: No SyncE/PTP support + | 1: Supports 2nd Serdes + | 2: Not 2nd Serdes support + 0: 10G, 5G, 2.5G + 5: 5G, 2.5G + 2: 2.5G + +allOf: + - $ref: ethernet-phy.yaml# + +select: + properties: + compatible: + contains: + enum: + - ethernet-phy-id7500.9410 + - ethernet-phy-id7500.9402 + - ethernet-phy-id7500.9412 + - ethernet-phy-id7500.9422 + - ethernet-phy-id7500.9432 + - ethernet-phy-id7500.9442 + - ethernet-phy-id7500.9452 + - ethernet-phy-id7500.9462 + - ethernet-phy-id7500.9472 + - ethernet-phy-id7500.9482 + - ethernet-phy-id7500.9492 + required: + - compatible + +properties: + reg: + maxItems: 1 + + firmware-name: + description: specify the name of PHY firmware to load + maxItems: 1 + +required: + - compatible + - reg + +if: + properties: + compatible: + contains: + const: ethernet-phy-id7500.9410 +then: + required: + - firmware-name +else: + properties: + firmware-name: false + +unevaluatedProperties: false + +examples: + - | + #include + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@1f { + compatible = "ethernet-phy-id7500.9410", + "ethernet-phy-ieee802.3-c45"; + + reg = <31>; + firmware-name = "as21x1x_fw.bin"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <0>; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + default-state = "keep"; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml b/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml index 0fdd112654177..6d22131ac2f9e 100644 --- a/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml +++ b/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml @@ -57,6 +57,16 @@ properties: - const: hsi-mac - const: xfp-mac + memory-region: + items: + - description: QDMA0 buffer memory + - description: QDMA1 buffer memory + + memory-region-names: + items: + - const: qdma0-buf + - const: qdma1-buf + "#address-cells": const: 1 @@ -140,6 +150,9 @@ examples: , ; + memory-region = <&qdma0_buf>, <&qdma1_buf>; + memory-region-names = "qdma0-buf", "qdma1-buf"; + airoha,npu = <&npu>; #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml index 7fe0352dff0f8..7b6a2fde81753 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml @@ -23,6 +23,7 @@ properties: - allwinner,sun20i-d1-emac - allwinner,sun50i-h6-emac - allwinner,sun50i-h616-emac0 + - allwinner,sun55i-a523-emac0 - const: allwinner,sun50i-a64-emac reg: diff --git a/Documentation/devicetree/bindings/net/bluetooth/nxp,88w8987-bt.yaml b/Documentation/devicetree/bindings/net/bluetooth/nxp,88w8987-bt.yaml index d02e9dd847eff..3ab60c70286f5 100644 --- a/Documentation/devicetree/bindings/net/bluetooth/nxp,88w8987-bt.yaml +++ b/Documentation/devicetree/bindings/net/bluetooth/nxp,88w8987-bt.yaml @@ -48,6 +48,18 @@ properties: description: The GPIO number of the NXP chipset used for BT_WAKE_IN. + interrupts: + maxItems: 1 + description: + Host wakeup by falling edge interrupt on this pin which is + connected to BT_WAKE_OUT pin of the NXP chipset. + + interrupt-names: + items: + - const: wakeup + + wakeup-source: true + nxp,wakeout-pin: $ref: /schemas/types.yaml#/definitions/uint8 description: @@ -61,6 +73,7 @@ unevaluatedProperties: false examples: - | #include + #include serial { bluetooth { compatible = "nxp,88w8987-bt"; @@ -70,5 +83,9 @@ examples: nxp,wakein-pin = /bits/ 8 <18>; nxp,wakeout-pin = /bits/ 8 <19>; local-bd-address = [66 55 44 33 22 11]; + interrupt-parent = <&gpio>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "wakeup"; + wakeup-source; }; }; diff --git a/Documentation/devicetree/bindings/net/brcm,asp-v2.0.yaml b/Documentation/devicetree/bindings/net/brcm,asp-v2.0.yaml index 660e2ca42daf5..a3db6d594c8c9 100644 --- a/Documentation/devicetree/bindings/net/brcm,asp-v2.0.yaml +++ b/Documentation/devicetree/bindings/net/brcm,asp-v2.0.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/net/brcm,asp-v2.0.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Broadcom ASP 2.0 Ethernet controller +title: Broadcom ASP Ethernet controller maintainers: - Justin Chen @@ -15,6 +15,10 @@ description: Broadcom Ethernet controller first introduced with 72165 properties: compatible: oneOf: + - items: + - enum: + - brcm,bcm74110-asp + - const: brcm,asp-v3.0 - items: - enum: - brcm,bcm74165b0-asp @@ -23,10 +27,6 @@ properties: - enum: - brcm,bcm74165-asp - const: brcm,asp-v2.1 - - items: - - enum: - - brcm,bcm72165-asp - - const: brcm,asp-v2.0 "#address-cells": const: 1 @@ -39,11 +39,9 @@ properties: ranges: true interrupts: - minItems: 1 items: - description: RX/TX interrupt - - description: Port 0 Wake-on-LAN - - description: Port 1 Wake-on-LAN + - description: Wake-on-LAN interrupt clocks: maxItems: 1 @@ -106,16 +104,17 @@ examples: #include ethernet@9c00000 { - compatible = "brcm,bcm72165-asp", "brcm,asp-v2.0"; + compatible = "brcm,bcm74165-asp", "brcm,asp-v2.1"; reg = <0x9c00000 0x1fff14>; - interrupts = ; + interrupts-extended = <&intc GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <&aon_pm_l2_intc 14>; ranges = <0x0 0x9c00000 0x1fff14>; clocks = <&scmi 14>; #address-cells = <1>; #size-cells = <1>; mdio@c614 { - compatible = "brcm,asp-v2.0-mdio"; + compatible = "brcm,asp-v2.1-mdio"; reg = <0xc614 0x8>; reg-names = "mdio"; #address-cells = <1>; @@ -127,7 +126,7 @@ examples: }; mdio@ce14 { - compatible = "brcm,asp-v2.0-mdio"; + compatible = "brcm,asp-v2.1-mdio"; reg = <0xce14 0x8>; reg-names = "mdio"; #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/net/brcm,unimac-mdio.yaml b/Documentation/devicetree/bindings/net/brcm,unimac-mdio.yaml index 63bee5b542f50..43516dd357b8c 100644 --- a/Documentation/devicetree/bindings/net/brcm,unimac-mdio.yaml +++ b/Documentation/devicetree/bindings/net/brcm,unimac-mdio.yaml @@ -22,9 +22,9 @@ properties: - brcm,genet-mdio-v3 - brcm,genet-mdio-v4 - brcm,genet-mdio-v5 - - brcm,asp-v2.0-mdio - brcm,asp-v2.1-mdio - brcm,asp-v2.2-mdio + - brcm,asp-v3.0-mdio - brcm,unimac-mdio - brcm,bcm6846-mdio diff --git a/Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml b/Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml index 144a3785132c3..ec0c2168e4b9e 100644 --- a/Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml +++ b/Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml @@ -16,9 +16,7 @@ properties: - nxp,sja1000 - technologic,sja1000 - items: - - enum: - - renesas,r9a06g032-sja1000 # RZ/N1D - - renesas,r9a06g033-sja1000 # RZ/N1S + - const: renesas,r9a06g032-sja1000 # RZ/N1D - const: renesas,rzn1-sja1000 # RZ/N1 reg: diff --git a/Documentation/devicetree/bindings/net/can/renesas,rcar-canfd.yaml b/Documentation/devicetree/bindings/net/can/renesas,rcar-canfd.yaml index f6884f6e59e74..f4ac21c684278 100644 --- a/Documentation/devicetree/bindings/net/can/renesas,rcar-canfd.yaml +++ b/Documentation/devicetree/bindings/net/can/renesas,rcar-canfd.yaml @@ -42,19 +42,80 @@ properties: - renesas,r9a07g054-canfd # RZ/V2L - const: renesas,rzg2l-canfd # RZ/G2L family + - const: renesas,r9a09g047-canfd # RZ/G3E + reg: maxItems: 1 - interrupts: true + interrupts: + oneOf: + - items: + - description: Channel interrupt + - description: Global interrupt + - items: + - description: CAN global error interrupt + - description: CAN receive FIFO interrupt + - description: CAN0 error interrupt + - description: CAN0 transmit interrupt + - description: CAN0 transmit/receive FIFO receive completion interrupt + - description: CAN1 error interrupt + - description: CAN1 transmit interrupt + - description: CAN1 transmit/receive FIFO receive completion interrupt + - description: CAN2 error interrupt + - description: CAN2 transmit interrupt + - description: CAN2 transmit/receive FIFO receive completion interrupt + - description: CAN3 error interrupt + - description: CAN3 transmit interrupt + - description: CAN3 transmit/receive FIFO receive completion interrupt + - description: CAN4 error interrupt + - description: CAN4 transmit interrupt + - description: CAN4 transmit/receive FIFO receive completion interrupt + - description: CAN5 error interrupt + - description: CAN5 transmit interrupt + - description: CAN5 transmit/receive FIFO receive completion interrupt + minItems: 8 + + interrupt-names: + oneOf: + - items: + - const: ch_int + - const: g_int + - items: + - const: g_err + - const: g_recc + - const: ch0_err + - const: ch0_rec + - const: ch0_trx + - const: ch1_err + - const: ch1_rec + - const: ch1_trx + - const: ch2_err + - const: ch2_rec + - const: ch2_trx + - const: ch3_err + - const: ch3_rec + - const: ch3_trx + - const: ch4_err + - const: ch4_rec + - const: ch4_trx + - const: ch5_err + - const: ch5_rec + - const: ch5_trx + minItems: 8 clocks: maxItems: 3 clock-names: - items: - - const: fck - - const: canfd - - const: can_clk + oneOf: + - items: + - const: fck + - const: canfd + - const: can_clk + - items: + - const: fck + - const: ram_clk + - const: can_clk power-domains: maxItems: 1 @@ -117,52 +178,77 @@ allOf: then: properties: interrupts: - items: - - description: CAN global error interrupt - - description: CAN receive FIFO interrupt - - description: CAN0 error interrupt - - description: CAN0 transmit interrupt - - description: CAN0 transmit/receive FIFO receive completion interrupt - - description: CAN1 error interrupt - - description: CAN1 transmit interrupt - - description: CAN1 transmit/receive FIFO receive completion interrupt + maxItems: 8 interrupt-names: - items: - - const: g_err - - const: g_recc - - const: ch0_err - - const: ch0_rec - - const: ch0_trx - - const: ch1_err - - const: ch1_rec - - const: ch1_trx + maxItems: 8 resets: + minItems: 2 maxItems: 2 reset-names: - items: - - const: rstp_n - - const: rstc_n + minItems: 2 + maxItems: 2 required: - reset-names - else: + + - if: + properties: + compatible: + contains: + enum: + - renesas,rcar-gen3-canfd + - renesas,rcar-gen4-canfd + then: properties: interrupts: - items: - - description: Channel interrupt - - description: Global interrupt + minItems: 2 + maxItems: 2 interrupt-names: - items: - - const: ch_int - - const: g_int + minItems: 2 + maxItems: 2 resets: maxItems: 1 + - if: + properties: + compatible: + contains: + const: renesas,r9a09g047-canfd + then: + properties: + interrupts: + minItems: 20 + + interrupt-names: + minItems: 20 + + resets: + minItems: 2 + maxItems: 2 + + reset-names: + minItems: 2 + maxItems: 2 + + required: + - reset-names + + - if: + properties: + compatible: + contains: + enum: + - renesas,rcar-gen3-canfd + - renesas,rzg2l-canfd + then: + patternProperties: + "^channel[2-7]$": false + - if: properties: compatible: @@ -171,16 +257,15 @@ allOf: then: patternProperties: "^channel[4-7]$": false - else: - if: - not: - properties: - compatible: - contains: - const: renesas,rcar-gen4-canfd - then: - patternProperties: - "^channel[2-7]$": false + + - if: + properties: + compatible: + contains: + const: renesas,r9a09g047-canfd + then: + patternProperties: + "^channel[6-7]$": false unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index ea979bcae1d6e..51205f9f29856 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -96,6 +96,10 @@ properties: Built-in switch of the Airoha EN7581 SoC const: airoha,en7581-switch + - description: + Built-in switch of the Airoha AN7583 SoC + const: airoha,an7583-switch + reg: maxItems: 1 @@ -291,6 +295,7 @@ allOf: enum: - mediatek,mt7988-switch - airoha,en7581-switch + - airoha,an7583-switch then: $ref: "#/$defs/mt7530-dsa-port" properties: diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml index a2d4c626f659a..7cbf11bbe99ca 100644 --- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml @@ -16,30 +16,6 @@ properties: label: description: Human readable label on a port of a box. - local-mac-address: - description: - Specifies the MAC address that was assigned to the network device. - $ref: /schemas/types.yaml#/definitions/uint8-array - minItems: 6 - maxItems: 6 - - mac-address: - description: - Specifies the MAC address that was last used by the boot - program; should be used in cases where the MAC address assigned - to the device by the boot program is different from the - local-mac-address property. - $ref: /schemas/types.yaml#/definitions/uint8-array - minItems: 6 - maxItems: 6 - - max-frame-size: - $ref: /schemas/types.yaml#/definitions/uint32 - description: - Maximum transfer unit (IEEE defined MTU), rather than the - maximum frame size (there\'s contradiction in the Devicetree - Specification). - max-speed: $ref: /schemas/types.yaml#/definitions/uint32 description: @@ -195,7 +171,7 @@ properties: description: Link speed. $ref: /schemas/types.yaml#/definitions/uint32 - enum: [10, 100, 1000, 2500, 10000] + enum: [10, 100, 1000, 2500, 5000, 10000] full-duplex: $ref: /schemas/types.yaml#/definitions/flag @@ -260,6 +236,7 @@ dependencies: pcs-handle-names: [pcs-handle] allOf: + - $ref: /schemas/net/network-class.yaml# - if: properties: phy-mode: diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml index 824bbe4333b7e..71e2cd32580f2 100644 --- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml @@ -238,6 +238,16 @@ properties: peak-to-peak specified in ANSI X3.263. When omitted, the PHYs default will be left as is. + mac-termination-ohms: + maximum: 200 + description: + The xMII signals need series termination on the driver side to match both + the output driver impedance and the line characteristic impedance, to + prevent reflections and EMI problems. Select a resistance value which is + supported by the builtin resistors of the PHY, otherwise the resistors may + have to be placed on board. When omitted, the PHYs default will be left as + is. + leds: type: object diff --git a/Documentation/devicetree/bindings/net/network-class.yaml b/Documentation/devicetree/bindings/net/network-class.yaml new file mode 100644 index 0000000000000..06461fb92eb84 --- /dev/null +++ b/Documentation/devicetree/bindings/net/network-class.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/network-class.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Network Class Common Properties + +maintainers: + - Devicetree Specification Mailing List + +properties: + address-bits: + description: + Specifies number of address bits required to address the device + described by this node, e.g. size of the MAC address. + default: 48 + const: 48 + + local-mac-address: + description: + Specifies MAC address that was assigned to the network device described by + the node containing this property. + $ref: /schemas/types.yaml#/definitions/uint8-array + minItems: 6 + maxItems: 6 + + mac-address: + description: + Specifies the MAC address that was last used by the boot program. This + property should be used in cases where the MAC address assigned to the + device by the boot program is different from the + local-mac-address property. This property shall be used only if the value + differs from local-mac-address property value. + $ref: /schemas/types.yaml#/definitions/uint8-array + minItems: 6 + maxItems: 6 + + max-frame-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Maximum transfer unit (IEEE defined MTU), rather than the + maximum frame size (there\'s contradiction in the Devicetree + Specification). + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/net/renesas,r9a09g057-gbeth.yaml b/Documentation/devicetree/bindings/net/renesas,r9a09g057-gbeth.yaml new file mode 100644 index 0000000000000..c498a9999289f --- /dev/null +++ b/Documentation/devicetree/bindings/net/renesas,r9a09g057-gbeth.yaml @@ -0,0 +1,203 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/renesas,r9a09g057-gbeth.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GBETH glue layer for Renesas RZ/V2H(P) (and similar SoCs) + +maintainers: + - Lad Prabhakar + +select: + properties: + compatible: + contains: + enum: + - renesas,r9a09g056-gbeth + - renesas,r9a09g057-gbeth + - renesas,rzv2h-gbeth + required: + - compatible + +properties: + compatible: + items: + - enum: + - renesas,r9a09g056-gbeth # RZ/V2N + - renesas,r9a09g057-gbeth # RZ/V2H(P) + - const: renesas,rzv2h-gbeth + - const: snps,dwmac-5.20 + + reg: + maxItems: 1 + + clocks: + items: + - description: CSR clock + - description: AXI system clock + - description: PTP clock + - description: TX clock + - description: RX clock + - description: TX clock phase-shifted by 180 degrees + - description: RX clock phase-shifted by 180 degrees + + clock-names: + items: + - const: stmmaceth + - const: pclk + - const: ptp_ref + - const: tx + - const: rx + - const: tx-180 + - const: rx-180 + + interrupts: + minItems: 11 + + interrupt-names: + items: + - const: macirq + - const: eth_wake_irq + - const: eth_lpi + - const: rx-queue-0 + - const: rx-queue-1 + - const: rx-queue-2 + - const: rx-queue-3 + - const: tx-queue-0 + - const: tx-queue-1 + - const: tx-queue-2 + - const: tx-queue-3 + + resets: + items: + - description: AXI power-on system reset + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - interrupt-names + - resets + +allOf: + - $ref: snps,dwmac.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + ethernet@15c30000 { + compatible = "renesas,r9a09g057-gbeth", "renesas,rzv2h-gbeth", "snps,dwmac-5.20"; + reg = <0x15c30000 0x10000>; + clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, + <&ptp_clock>, <&cpg CPG_MOD 0xb8>, + <&cpg CPG_MOD 0xb9>, <&cpg CPG_MOD 0xba>, + <&cpg CPG_MOD 0xbb>; + clock-names = "stmmaceth", "pclk", "ptp_ref", + "tx", "rx", "tx-180", "rx-180"; + resets = <&cpg 0xb0>; + interrupts = , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", + "rx-queue-0", "rx-queue-1", "rx-queue-2", + "rx-queue-3", "tx-queue-0", "tx-queue-1", + "tx-queue-2", "tx-queue-3"; + phy-mode = "rgmii-id"; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + rx-fifo-depth = <8192>; + tx-fifo-depth = <8192>; + snps,fixed-burst; + snps,force_thresh_dma_mode; + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,txpbl = <32>; + snps,rxpbl = <32>; + phy-handle = <&phy0>; + + stmmac_axi_setup: stmmac-axi-config { + snps,lpi_en; + snps,wr_osr_lmt = <0xf>; + snps,rd_osr_lmt = <0xf>; + snps,blen = <16 8 4 0 0 0 0>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml index 78b3030dc56d2..90b79283e228b 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -75,6 +75,7 @@ properties: - qcom,sm8150-ethqos - renesas,r9a06g032-gmac - renesas,rzn1-gmac + - renesas,rzv2h-gbeth - rockchip,px30-gmac - rockchip,rk3128-gmac - rockchip,rk3228-gmac @@ -114,19 +115,25 @@ properties: interrupts: minItems: 1 - items: - - description: Combined signal for various interrupt events - - description: The interrupt to manage the remote wake-up packet detection - - description: The interrupt that occurs when Rx exits the LPI state - - description: The interrupt that occurs when HW safety error triggered + maxItems: 11 interrupt-names: minItems: 1 + maxItems: 11 items: - - const: macirq - - enum: [eth_wake_irq, eth_lpi, sfty] - - enum: [eth_wake_irq, eth_lpi, sfty] - - enum: [eth_wake_irq, eth_lpi, sfty] + oneOf: + - description: Combined signal for various interrupt events + const: macirq + - description: The interrupt to manage the remote wake-up packet detection + const: eth_wake_irq + - description: The interrupt that occurs when Rx exits the LPI state + const: eth_lpi + - description: The interrupt that occurs when HW safety error triggered + const: sfty + - description: Per channel receive completion interrupt + pattern: '^rx-queue-[0-3]$' + - description: Per channel transmit completion interrupt + pattern: '^tx-queue-[0-3]$' clocks: minItems: 1 @@ -703,7 +710,7 @@ examples: }; }; - mdio0 { + mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; diff --git a/Documentation/devicetree/bindings/net/ti,dp83822.yaml b/Documentation/devicetree/bindings/net/ti,dp83822.yaml index 50c24248df266..28a0bddb9af94 100644 --- a/Documentation/devicetree/bindings/net/ti,dp83822.yaml +++ b/Documentation/devicetree/bindings/net/ti,dp83822.yaml @@ -122,6 +122,9 @@ properties: - free-running - recovered + mac-termination-ohms: + enum: [43, 44, 46, 48, 50, 53, 55, 58, 61, 65, 69, 73, 78, 84, 91, 99] + required: - reg @@ -137,6 +140,7 @@ examples: rx-internal-delay-ps = <1>; tx-internal-delay-ps = <1>; ti,gpio2-clk-out = "xi"; + mac-termination-ohms = <43>; }; }; diff --git a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml index b11894fbaec47..7b3d948f187df 100644 --- a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml +++ b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml @@ -143,6 +143,8 @@ properties: label: description: label associated with this port + fixed-link: true + ti,mac-only: $ref: /schemas/types.yaml#/definitions/flag description: diff --git a/Documentation/devicetree/bindings/net/vertexcom-mse102x.yaml b/Documentation/devicetree/bindings/net/vertexcom-mse102x.yaml index 4158673f723c9..8359de7ad272e 100644 --- a/Documentation/devicetree/bindings/net/vertexcom-mse102x.yaml +++ b/Documentation/devicetree/bindings/net/vertexcom-mse102x.yaml @@ -63,7 +63,7 @@ examples: compatible = "vertexcom,mse1021"; reg = <0>; interrupt-parent = <&gpio>; - interrupts = <23 IRQ_TYPE_EDGE_RISING>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; spi-cpha; spi-cpol; spi-max-frequency = <7142857>; diff --git a/Documentation/devicetree/bindings/net/via,vt8500-rhine.yaml b/Documentation/devicetree/bindings/net/via,vt8500-rhine.yaml new file mode 100644 index 0000000000000..e663d5a2f0147 --- /dev/null +++ b/Documentation/devicetree/bindings/net/via,vt8500-rhine.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/via,vt8500-rhine.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: VIA Rhine 10/100 Network Controller + +description: + VIA's Ethernet controller integrated into VIA VT8500, + WonderMedia WM8950 and related SoCs + +maintainers: + - Alexey Charkov + +allOf: + - $ref: ethernet-controller.yaml# + +properties: + compatible: + const: via,vt8500-rhine + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + ethernet@d8004000 { + compatible = "via,vt8500-rhine"; + reg = <0xd8004000 0x100>; + interrupts = <10>; + }; diff --git a/Documentation/devicetree/bindings/net/via-rhine.txt b/Documentation/devicetree/bindings/net/via-rhine.txt deleted file mode 100644 index 334eca2bf937c..0000000000000 --- a/Documentation/devicetree/bindings/net/via-rhine.txt +++ /dev/null @@ -1,17 +0,0 @@ -* VIA Rhine 10/100 Network Controller - -Required properties: -- compatible : Should be "via,vt8500-rhine" for integrated - Rhine controllers found in VIA VT8500, WonderMedia WM8950 - and similar. These are listed as 1106:3106 rev. 0x84 on the - virtual PCI bus under vendor-provided kernels -- reg : Address and length of the io space -- interrupts : Should contain the controller interrupt line - -Examples: - -ethernet@d8004000 { - compatible = "via,vt8500-rhine"; - reg = <0xd8004000 0x100>; - interrupts = <10>; -}; diff --git a/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml b/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml index a3607d55ef367..7c8100e59a6cd 100644 --- a/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml +++ b/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml @@ -16,7 +16,7 @@ description: binding. allOf: - - $ref: ieee80211.yaml# + - $ref: /schemas/net/wireless/wireless-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath12k.yaml b/Documentation/devicetree/bindings/net/wireless/qcom,ath12k.yaml index 9e557cb838c7a..dc68dd59988fc 100644 --- a/Documentation/devicetree/bindings/net/wireless/qcom,ath12k.yaml +++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath12k.yaml @@ -21,6 +21,12 @@ properties: reg: maxItems: 1 + firmware-name: + maxItems: 1 + description: + If present, a board or platform specific string used to lookup + usecase-specific firmware files for the device. + vddaon-supply: description: VDD_AON supply regulator handle diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ipq5332-wifi.yaml b/Documentation/devicetree/bindings/net/wireless/qcom,ipq5332-wifi.yaml new file mode 100644 index 0000000000000..363a0ecb6ad97 --- /dev/null +++ b/Documentation/devicetree/bindings/net/wireless/qcom,ipq5332-wifi.yaml @@ -0,0 +1,315 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/wireless/qcom,ipq5332-wifi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies ath12k wireless devices (AHB) + +maintainers: + - Jeff Johnson + +description: + Qualcomm Technologies IEEE 802.11be AHB devices. + +properties: + compatible: + enum: + - qcom,ipq5332-wifi + + reg: + maxItems: 1 + + clocks: + items: + - description: XO clock used for copy engine + + clock-names: + items: + - const: xo + + interrupts: + items: + - description: Fatal interrupt + - description: Ready interrupt + - description: Spawn acknowledge interrupt + - description: Stop acknowledge interrupt + - description: misc-pulse1 interrupt events + - description: misc-latch interrupt events + - description: sw exception interrupt events + - description: interrupt event for ring CE0 + - description: interrupt event for ring CE1 + - description: interrupt event for ring CE2 + - description: interrupt event for ring CE3 + - description: interrupt event for ring CE4 + - description: interrupt event for ring CE5 + - description: interrupt event for ring CE6 + - description: interrupt event for ring CE7 + - description: interrupt event for ring CE8 + - description: interrupt event for ring CE9 + - description: interrupt event for ring CE10 + - description: interrupt event for ring CE11 + - description: interrupt event for ring host2wbm-desc-feed + - description: interrupt event for ring host2reo-re-injection + - description: interrupt event for ring host2reo-command + - description: interrupt event for ring host2rxdma-monitor-ring1 + - description: interrupt event for ring reo2ost-exception + - description: interrupt event for ring wbm2host-rx-release + - description: interrupt event for ring reo2host-status + - description: interrupt event for ring reo2host-destination-ring4 + - description: interrupt event for ring reo2host-destination-ring3 + - description: interrupt event for ring reo2host-destination-ring2 + - description: interrupt event for ring reo2host-destination-ring1 + - description: interrupt event for ring rxdma2host-monitor-destination-mac3 + - description: interrupt event for ring rxdma2host-monitor-destination-mac2 + - description: interrupt event for ring rxdma2host-monitor-destination-mac1 + - description: interrupt event for ring host2rxdma-host-buf-ring-mac3 + - description: interrupt event for ring host2rxdma-host-buf-ring-mac2 + - description: interrupt event for ring host2rxdma-host-buf-ring-mac1 + - description: interrupt event for ring host2tcl-input-ring4 + - description: interrupt event for ring host2tcl-input-ring3 + - description: interrupt event for ring host2tcl-input-ring2 + - description: interrupt event for ring host2tcl-input-ring1 + - description: interrupt event for ring wbm2host-tx-completions-ring4 + - description: interrupt event for ring wbm2host-tx-completions-ring3 + - description: interrupt event for ring wbm2host-tx-completions-ring2 + - description: interrupt event for ring wbm2host-tx-completions-ring1 + - description: interrupt event for ring host2tx-monitor-ring1 + - description: interrupt event for ring txmon2host-monitor-destination-mac3 + - description: interrupt event for ring txmon2host-monitor-destination-mac2 + - description: interrupt event for ring txmon2host-monitor-destination-mac1 + - description: interrupt event for umac-reset + + interrupt-names: + items: + - const: fatal + - const: ready + - const: spawn + - const: stop-ack + - const: misc-pulse1 + - const: misc-latch + - const: sw-exception + - const: ce0 + - const: ce1 + - const: ce2 + - const: ce3 + - const: ce4 + - const: ce5 + - const: ce6 + - const: ce7 + - const: ce8 + - const: ce9 + - const: ce10 + - const: ce11 + - const: host2wbm-desc-feed + - const: host2reo-re-injection + - const: host2reo-command + - const: host2rxdma-monitor-ring1 + - const: reo2ost-exception + - const: wbm2host-rx-release + - const: reo2host-status + - const: reo2host-destination-ring4 + - const: reo2host-destination-ring3 + - const: reo2host-destination-ring2 + - const: reo2host-destination-ring1 + - const: rxdma2host-monitor-destination-mac3 + - const: rxdma2host-monitor-destination-mac2 + - const: rxdma2host-monitor-destination-mac1 + - const: host2rxdma-host-buf-ring-mac3 + - const: host2rxdma-host-buf-ring-mac2 + - const: host2rxdma-host-buf-ring-mac1 + - const: host2tcl-input-ring4 + - const: host2tcl-input-ring3 + - const: host2tcl-input-ring2 + - const: host2tcl-input-ring1 + - const: wbm2host-tx-completions-ring4 + - const: wbm2host-tx-completions-ring3 + - const: wbm2host-tx-completions-ring2 + - const: wbm2host-tx-completions-ring1 + - const: host2tx-monitor-ring1 + - const: txmon2host-monitor-destination-mac3 + - const: txmon2host-monitor-destination-mac2 + - const: txmon2host-monitor-destination-mac1 + - const: umac-reset + + memory-region: + description: + Memory regions used by the ath12k firmware. + items: + - description: Q6 memory region + - description: m3 dump memory region + - description: Q6 caldata memory region + - description: Multi Link Operation (MLO) Global memory region + + memory-region-names: + items: + - const: q6-region + - const: m3-dump + - const: q6-caldb + - const: mlo-global-mem + + qcom,calibration-variant: + $ref: /schemas/types.yaml#/definitions/string + description: + String to uniquely identify variant of the calibration data for designs + with colliding bus and device ids + + qcom,rproc: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the Qualcomm Hexagon DSP(q6 remote processor), which is utilized + for offloading WiFi processing tasks, this q6 remote processor operates in + conjunction with WiFi. + + qcom,smem-states: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: States used by the AP to signal the remote processor + items: + - description: Shutdown WCSS pd + - description: Stop WCSS pd + - description: Spawn WCSS pd + + qcom,smem-state-names: + description: + Names of the states used by the AP to signal the remote processor + items: + - const: shutdown + - const: stop + - const: spawn + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - interrupt-names + - memory-region + - memory-region-names + - qcom,rproc + - qcom,smem-states + - qcom,smem-state-names + +additionalProperties: false + +examples: + - | + #include + #include + + wifi0: wifi@c000000 { + compatible = "qcom,ipq5332-wifi"; + reg = <0x0c000000 0x1000000>; + clocks = <&gcc GCC_XO_CLK>; + clock-names = "xo"; + interrupts-extended = <&wcss_smp2p_in 8 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 9 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 12 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 11 IRQ_TYPE_NONE>, + <&intc GIC_SPI 559 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 560 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 561 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 422 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 423 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 424 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 425 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 426 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 427 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 428 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 429 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 430 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 431 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 432 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 433 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 491 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 495 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 493 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 544 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 457 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 497 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 454 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 453 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 452 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 451 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 488 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 488 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 484 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 554 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 554 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 549 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 507 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 500 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 499 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 498 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 450 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 449 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 447 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 543 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 486 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 486 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 482 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 419 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "fatal", + "ready", + "spawn", + "stop-ack", + "misc-pulse1", + "misc-latch", + "sw-exception", + "ce0", + "ce1", + "ce2", + "ce3", + "ce4", + "ce5", + "ce6", + "ce7", + "ce8", + "ce9", + "ce10", + "ce11", + "host2wbm-desc-feed", + "host2reo-re-injection", + "host2reo-command", + "host2rxdma-monitor-ring1", + "reo2ost-exception", + "wbm2host-rx-release", + "reo2host-status", + "reo2host-destination-ring4", + "reo2host-destination-ring3", + "reo2host-destination-ring2", + "reo2host-destination-ring1", + "rxdma2host-monitor-destination-mac3", + "rxdma2host-monitor-destination-mac2", + "rxdma2host-monitor-destination-mac1", + "host2rxdma-host-buf-ring-mac3", + "host2rxdma-host-buf-ring-mac2", + "host2rxdma-host-buf-ring-mac1", + "host2tcl-input-ring4", + "host2tcl-input-ring3", + "host2tcl-input-ring2", + "host2tcl-input-ring1", + "wbm2host-tx-completions-ring4", + "wbm2host-tx-completions-ring3", + "wbm2host-tx-completions-ring2", + "wbm2host-tx-completions-ring1", + "host2tx-monitor-ring1", + "txmon2host-monitor-destination-mac3", + "txmon2host-monitor-destination-mac2", + "txmon2host-monitor-destination-mac1", + "umac-reset"; + + memory-region = <&q6_region>, <&m3_dump>, <&q6_caldb>, <&mlo_mem>; + memory-region-names = "q6-region", "m3-dump", "q6-caldb", "mlo-global-mem"; + qcom,calibration-variant = "RDP441_1"; + qcom,rproc = <&q6v5_wcss>; + qcom,smem-states = <&wcss_smp2p_out 8>, + <&wcss_smp2p_out 9>, + <&wcss_smp2p_out 10>; + qcom,smem-state-names = "shutdown", + "stop", + "spawn"; + }; diff --git a/Documentation/devicetree/bindings/net/wireless/silabs,wfx.yaml b/Documentation/devicetree/bindings/net/wireless/silabs,wfx.yaml index 84e5659e50ef3..6c0888ae4c4e1 100644 --- a/Documentation/devicetree/bindings/net/wireless/silabs,wfx.yaml +++ b/Documentation/devicetree/bindings/net/wireless/silabs,wfx.yaml @@ -71,15 +71,12 @@ properties: "Platform Data Set" in Silabs jargon). Default depends of "compatible" string. For "silabs,wf200", the default is 'wf200.pds'. - local-mac-address: true - - mac-address: true - required: - compatible - reg allOf: + - $ref: /schemas/net/wireless/wireless-controller.yaml# - $ref: /schemas/spi/spi-peripheral-props.yaml# unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/net/wireless/wireless-controller.yaml b/Documentation/devicetree/bindings/net/wireless/wireless-controller.yaml new file mode 100644 index 0000000000000..7379f6c1aa05c --- /dev/null +++ b/Documentation/devicetree/bindings/net/wireless/wireless-controller.yaml @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/wireless/wireless-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Wireless Controller Common Properties + +maintainers: + - Lorenzo Bianconi + +properties: + $nodename: + pattern: "^wifi(@.*)?$" + +allOf: + - $ref: ieee80211.yaml# + - $ref: /schemas/net/network-class.yaml# + +additionalProperties: true + +... + diff --git a/Documentation/devicetree/bindings/numa.txt b/Documentation/devicetree/bindings/numa.txt deleted file mode 100644 index 42f282c2f3cc4..0000000000000 --- a/Documentation/devicetree/bindings/numa.txt +++ /dev/null @@ -1,319 +0,0 @@ -============================================================================== -NUMA binding description. -============================================================================== - -============================================================================== -1 - Introduction -============================================================================== - -Systems employing a Non Uniform Memory Access (NUMA) architecture contain -collections of hardware resources including processors, memory, and I/O buses, -that comprise what is commonly known as a NUMA node. -Processor accesses to memory within the local NUMA node is generally faster -than processor accesses to memory outside of the local NUMA node. -DT defines interfaces that allow the platform to convey NUMA node -topology information to OS. - -============================================================================== -2 - numa-node-id -============================================================================== - -For the purpose of identification, each NUMA node is associated with a unique -token known as a node id. For the purpose of this binding -a node id is a 32-bit integer. - -A device node is associated with a NUMA node by the presence of a -numa-node-id property which contains the node id of the device. - -Example: - /* numa node 0 */ - numa-node-id = <0>; - - /* numa node 1 */ - numa-node-id = <1>; - -============================================================================== -3 - distance-map -============================================================================== - -The optional device tree node distance-map describes the relative -distance (memory latency) between all numa nodes. - -- compatible : Should at least contain "numa-distance-map-v1". - -- distance-matrix - This property defines a matrix to describe the relative distances - between all numa nodes. - It is represented as a list of node pairs and their relative distance. - - Note: - 1. Each entry represents distance from first node to second node. - The distances are equal in either direction. - 2. The distance from a node to self (local distance) is represented - with value 10 and all internode distance should be represented with - a value greater than 10. - 3. distance-matrix should have entries in lexicographical ascending - order of nodes. - 4. There must be only one device node distance-map which must - reside in the root node. - 5. If the distance-map node is not present, a default - distance-matrix is used. - -Example: - 4 nodes connected in mesh/ring topology as below, - - 0_______20______1 - | | - | | - 20 20 - | | - | | - |_______________| - 3 20 2 - - if relative distance for each hop is 20, - then internode distance would be, - 0 -> 1 = 20 - 1 -> 2 = 20 - 2 -> 3 = 20 - 3 -> 0 = 20 - 0 -> 2 = 40 - 1 -> 3 = 40 - - and dt presentation for this distance matrix is, - - distance-map { - compatible = "numa-distance-map-v1"; - distance-matrix = <0 0 10>, - <0 1 20>, - <0 2 40>, - <0 3 20>, - <1 0 20>, - <1 1 10>, - <1 2 20>, - <1 3 40>, - <2 0 40>, - <2 1 20>, - <2 2 10>, - <2 3 20>, - <3 0 20>, - <3 1 40>, - <3 2 20>, - <3 3 10>; - }; - -============================================================================== -4 - Empty memory nodes -============================================================================== - -Empty memory nodes, which no memory resides in, are allowed. There are no -device nodes for these empty memory nodes. However, the NUMA node IDs and -distance maps are still valid and memory may be added into them through -hotplug afterwards. - -Example: - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - numa-node-id = <0>; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x80000000>; - numa-node-id = <1>; - }; - - /* Empty memory node 2 and 3 */ - distance-map { - compatible = "numa-distance-map-v1"; - distance-matrix = <0 0 10>, - <0 1 20>, - <0 2 40>, - <0 3 20>, - <1 0 20>, - <1 1 10>, - <1 2 20>, - <1 3 40>, - <2 0 40>, - <2 1 20>, - <2 2 10>, - <2 3 20>, - <3 0 20>, - <3 1 40>, - <3 2 20>, - <3 3 10>; - }; - -============================================================================== -5 - Example dts -============================================================================== - -Dual socket system consists of 2 boards connected through ccn bus and -each board having one socket/soc of 8 cpus, memory and pci bus. - - memory@c00000 { - device_type = "memory"; - reg = <0x0 0xc00000 0x0 0x80000000>; - /* node 0 */ - numa-node-id = <0>; - }; - - memory@10000000000 { - device_type = "memory"; - reg = <0x100 0x0 0x0 0x80000000>; - /* node 1 */ - numa-node-id = <1>; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x0>; - enable-method = "psci"; - /* node 0 */ - numa-node-id = <0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x1>; - enable-method = "psci"; - numa-node-id = <0>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x2>; - enable-method = "psci"; - numa-node-id = <0>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x3>; - enable-method = "psci"; - numa-node-id = <0>; - }; - cpu@4 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x4>; - enable-method = "psci"; - numa-node-id = <0>; - }; - cpu@5 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x5>; - enable-method = "psci"; - numa-node-id = <0>; - }; - cpu@6 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x6>; - enable-method = "psci"; - numa-node-id = <0>; - }; - cpu@7 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x7>; - enable-method = "psci"; - numa-node-id = <0>; - }; - cpu@8 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x8>; - enable-method = "psci"; - /* node 1 */ - numa-node-id = <1>; - }; - cpu@9 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x9>; - enable-method = "psci"; - numa-node-id = <1>; - }; - cpu@a { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0xa>; - enable-method = "psci"; - numa-node-id = <1>; - }; - cpu@b { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0xb>; - enable-method = "psci"; - numa-node-id = <1>; - }; - cpu@c { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0xc>; - enable-method = "psci"; - numa-node-id = <1>; - }; - cpu@d { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0xd>; - enable-method = "psci"; - numa-node-id = <1>; - }; - cpu@e { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0xe>; - enable-method = "psci"; - numa-node-id = <1>; - }; - cpu@f { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0xf>; - enable-method = "psci"; - numa-node-id = <1>; - }; - }; - - pcie0: pcie0@848000000000 { - compatible = "arm,armv8"; - device_type = "pci"; - bus-range = <0 255>; - #size-cells = <2>; - #address-cells = <3>; - reg = <0x8480 0x00000000 0 0x10000000>; /* Configuration space */ - ranges = <0x03000000 0x8010 0x00000000 0x8010 0x00000000 0x70 0x00000000>; - /* node 0 */ - numa-node-id = <0>; - }; - - pcie1: pcie1@948000000000 { - compatible = "arm,armv8"; - device_type = "pci"; - bus-range = <0 255>; - #size-cells = <2>; - #address-cells = <3>; - reg = <0x9480 0x00000000 0 0x10000000>; /* Configuration space */ - ranges = <0x03000000 0x9010 0x00000000 0x9010 0x00000000 0x70 0x00000000>; - /* node 1 */ - numa-node-id = <1>; - }; - - distance-map { - compatible = "numa-distance-map-v1"; - distance-matrix = <0 0 10>, - <0 1 20>, - <1 1 10>; - }; diff --git a/Documentation/devicetree/bindings/nvmem/maxim,max77759-nvmem.yaml b/Documentation/devicetree/bindings/nvmem/maxim,max77759-nvmem.yaml new file mode 100644 index 0000000000000..1e3bd44330073 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/maxim,max77759-nvmem.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/maxim,max77759-nvmem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim Integrated MAX77759 Non Volatile Memory + +maintainers: + - André Draszik + +description: | + This module is part of the MAX77759 PMIC. For additional information, see + Documentation/devicetree/bindings/mfd/maxim,max77759.yaml. + + The MAX77759 is a PMIC integrating, amongst others, Non Volatile Memory + (NVMEM) with 30 bytes of storage which can be used by software to store + information or communicate with a boot loader. + +properties: + compatible: + const: maxim,max77759-nvmem + + wp-gpios: false + +required: + - compatible + +allOf: + - $ref: nvmem.yaml# + +unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/opp/opp-v1.yaml b/Documentation/devicetree/bindings/opp/opp-v1.yaml index 07e26c2678153..61c080e508597 100644 --- a/Documentation/devicetree/bindings/opp/opp-v1.yaml +++ b/Documentation/devicetree/bindings/opp/opp-v1.yaml @@ -18,9 +18,21 @@ description: |+ This binding only supports voltage-frequency pairs. -select: true +deprecated: true properties: + clock-latency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The latency in nanoseconds for clock changes. Use OPP tables for new + designs instead. + + voltage-tolerance: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 10 + description: + The voltage tolerance in percent. Use OPP tables for new designs instead. + operating-points: $ref: /schemas/types.yaml#/definitions/uint32-matrix items: @@ -28,8 +40,12 @@ properties: - description: Frequency in kHz - description: Voltage for OPP in uV +dependencies: + clock-latency: [ operating-points ] + voltage-tolerance: [ operating-points ] additionalProperties: true + examples: - | cpus { diff --git a/Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml b/Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml new file mode 100644 index 0000000000000..a27ba7b663d45 --- /dev/null +++ b/Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/opp/opp-v2-qcom-adreno.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Adreno compatible OPP supply + +description: + Adreno GPUs present in Qualcomm's Snapdragon chipsets uses an OPP specific + ACD related information tailored for the specific chipset. This binding + provides the information needed to describe such a hardware value. + +maintainers: + - Rob Clark + +allOf: + - $ref: opp-v2-base.yaml# + +properties: + compatible: + contains: + const: operating-points-v2-adreno + +patternProperties: + '^opp-[0-9]+$': + type: object + additionalProperties: false + + properties: + opp-hz: true + + opp-level: true + + opp-peak-kBps: true + + opp-supported-hw: true + + qcom,opp-acd-level: + description: | + A positive value representing the ACD (Adaptive Clock Distribution, + a fancy name for clk throttling during voltage droop) level associated + with this OPP node. This value is shared to a co-processor inside GPU + (called Graphics Management Unit a.k.a GMU) during wake up. It may not + be present for some OPPs and GMU will disable ACD while transitioning + to that OPP. This value encodes a voltage threshold, delay cycles & + calibration margins which are identified by characterization of the + SoC. So, it doesn't have any unit. This data is passed to GMU firmware + via 'HFI_H2F_MSG_ACD' packet. + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - opp-hz + - opp-level + +required: + - compatible + +additionalProperties: false + +examples: + - | + #include + + gpu_opp_table: opp-table { + compatible = "operating-points-v2-adreno", "operating-points-v2"; + + opp-687000000 { + opp-hz = /bits/ 64 <687000000>; + opp-level = ; + opp-peak-kBps = <8171875>; + qcom,opp-acd-level = <0x882e5ffd>; + }; + + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + opp-level = ; + opp-peak-kBps = <6074219>; + qcom,opp-acd-level = <0xc0285ffd>; + }; + + opp-390000000 { + opp-hz = /bits/ 64 <390000000>; + opp-level = ; + opp-peak-kBps = <3000000>; + qcom,opp-acd-level = <0xc0285ffd>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-level = ; + opp-peak-kBps = <2136719>; + /* Intentionally left out qcom,opp-acd-level property here */ + }; + + }; diff --git a/Documentation/devicetree/bindings/pci/pci-ep.yaml b/Documentation/devicetree/bindings/pci/pci-ep.yaml index f75000e3093db..214caa4ec3d51 100644 --- a/Documentation/devicetree/bindings/pci/pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/pci-ep.yaml @@ -17,6 +17,24 @@ properties: $nodename: pattern: "^pcie-ep@" + iommu-map: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: Device ID (see msi-map) base + maximum: 0x7ffff + - description: phandle to IOMMU + - description: IOMMU specifier base (currently always 1 cell) + - description: Number of Device IDs + maximum: 0x80000 + + iommu-map-mask: + description: + A mask to be applied to each Device ID prior to being mapped to an + IOMMU specifier per the iommu-map property. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 0x7ffff + max-functions: description: Maximum number of functions that can be configured $ref: /schemas/types.yaml#/definitions/uint8 @@ -35,6 +53,56 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 enum: [ 1, 2, 3, 4 ] + msi-map: + description: | + Maps a Device ID to an MSI and associated MSI specifier data. + + A PCI Endpoint (EP) can use MSI as a doorbell function. This is achieved by + mapping the MSI controller's address into PCI BAR. The PCI Root Complex + can write to this BAR, triggering the EP to generate IRQ. This notifies + the EP-side driver of an event, eliminating the need for the driver to + continuously poll for status changes. + + However, the EP cannot rely on Requester ID (RID) because the RID is + determined by the PCI topology of the host system. Since the EP may be + connected to different PCI hosts, the RID can vary between systems and is + therefore not a reliable identifier. + + Each EP can support up to 8 physical functions and up to 65,536 virtual + functions. To uniquely identify each child device, a device ID is defined + as + - Bits [2:0] for the function number (func) + - Bits [18:3] for the virtual function index (vfunc) + + The resulting device ID is computed as: + + (func & 0x7) | (vfunc << 3) + + The property is an arbitrary number of tuples of + (device-id-base, msi, msi-base,length). + + Any Device ID id in the interval [id-base, id-base + length) is + associated with the listed MSI, with the MSI specifier + (id - id-base + msi-base). + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: The Device ID base matched by the entry + maximum: 0x7ffff + - description: phandle to msi-controller node + - description: (optional) The msi-specifier produced for the first + Device ID matched by the entry. Currently, msi-specifier is 0 or + 1 cells. + - description: The length of consecutive Device IDs following the + Device ID base + maximum: 0x80000 + + msi-map-mask: + description: A mask to be applied to each Device ID prior to being + mapped to an msi-specifier per the msi-map property. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 0x7ffff + num-lanes: description: maximum number of lanes $ref: /schemas/types.yaml#/definitions/uint32 diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml index 8eb50cad61d58..a6ef4797e5c59 100644 --- a/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml @@ -14,7 +14,12 @@ allOf: properties: compatible: - const: amlogic,pinctrl-a4 + oneOf: + - const: amlogic,pinctrl-a4 + - items: + - enum: + - amlogic,pinctrl-a5 + - const: amlogic,pinctrl-a4 "#address-cells": const: 2 @@ -65,6 +70,7 @@ patternProperties: patternProperties: "^group-[0-9a-z-]+$": type: object + unevaluatedProperties: false allOf: - $ref: /schemas/pinctrl/pincfg-node.yaml - $ref: /schemas/pinctrl/pinmux-node.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-iomuxc1.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-iomuxc1.yaml new file mode 100644 index 0000000000000..957918b73a93f --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-iomuxc1.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,imx7ulp-iomuxc1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX7ULP IOMUX Controller + +description: | + i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7 + ports and IOMUXC DDR for DDR interface. + + Note: This binding doc is only for the IOMUXC1 support in A7 Domain and it + only supports generic pin config. + + Please refer to fsl,imx-pinctrl.txt in this directory for common binding + part and usage. + +maintainers: + - Frank Li + +properties: + compatible: + const: fsl,imx7ulp-iomuxc1 + + reg: + maxItems: 1 + +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + Each entry consists of 5 integers which represents the mux + and config setting for one pin. The first 4 integers + are specified + using a PIN_FUNC_ID macro, which can be found in + imx7ulp-pinfunc.h in the device tree source folder. + The last integer CONFIG is the pad setting value like + pull-up on this pin. + + Please refer to i.MX7ULP Reference Manual for detailed + CONFIG settings. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "mux_conf_reg" indicates the offset of mux register. + - description: | + "input_reg" indicates the offset of select input register. + - description: | + "mux_mode" indicates the mux value to be applied. + - description: | + "input_val" indicates the select input value to be applied. + - description: | + CONFIG bits definition: + PAD_CTL_OBE (1 << 17) + PAD_CTL_IBE (1 << 16) + PAD_CTL_LK (1 << 16) + PAD_CTL_DSE_HI (1 << 6) + PAD_CTL_DSE_STD (0 << 6) + PAD_CTL_ODE (1 << 5) + PAD_CTL_PUSH_PULL (0 << 5) + PAD_CTL_SRE_SLOW (1 << 2) + PAD_CTL_SRE_STD (0 << 2) + PAD_CTL_PE (1 << 0) + + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + - reg + +allOf: + - $ref: pinctrl.yaml# + +unevaluatedProperties: false + +examples: + - | + pinctrl@40ac0000 { + compatible = "fsl,imx7ulp-iomuxc1"; + reg = <0x40ac0000 0x1000>; + + lpuart4grp { + fsl,pins = < + 0x000c 0x0248 0x4 0x1 0x1 + 0x0008 0x024c 0x4 0x1 0x1 + >; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt deleted file mode 100644 index bfa3703a74462..0000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt +++ /dev/null @@ -1,53 +0,0 @@ -* Freescale i.MX7ULP IOMUX Controller - -i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7 -ports and IOMUXC DDR for DDR interface. - -Note: -This binding doc is only for the IOMUXC1 support in A7 Domain and it only -supports generic pin config. - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding -part and usage. - -Required properties: -- compatible: "fsl,imx7ulp-iomuxc1". -- fsl,pins: Each entry consists of 5 integers which represents the mux - and config setting for one pin. The first 4 integers - are specified - using a PIN_FUNC_ID macro, which can be found in - imx7ulp-pinfunc.h in the device tree source folder. - The last integer CONFIG is the pad setting value like - pull-up on this pin. - - Please refer to i.MX7ULP Reference Manual for detailed - CONFIG settings. - -CONFIG bits definition: -PAD_CTL_OBE (1 << 17) -PAD_CTL_IBE (1 << 16) -PAD_CTL_LK (1 << 16) -PAD_CTL_DSE_HI (1 << 6) -PAD_CTL_DSE_STD (0 << 6) -PAD_CTL_ODE (1 << 5) -PAD_CTL_PUSH_PULL (0 << 5) -PAD_CTL_SRE_SLOW (1 << 2) -PAD_CTL_SRE_STD (0 << 2) -PAD_CTL_PE (1 << 0) - -Examples: -#include "imx7ulp-pinfunc.h" - -/* Pin Controller Node */ -iomuxc1: pinctrl@40ac0000 { - compatible = "fsl,imx7ulp-iomuxc1"; - reg = <0x40ac0000 0x1000>; - - /* Pin Configuration Node */ - pinctrl_lpuart4: lpuart4grp { - fsl,pins = < - IMX7ULP_PAD_PTC3__LPUART4_RX 0x1 - IMX7ULP_PAD_PTC2__LPUART4_TX 0x1 - >; - }; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,vf610-iomuxc.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,vf610-iomuxc.yaml new file mode 100644 index 0000000000000..3e13587df3107 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,vf610-iomuxc.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,vf610-iomuxc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Vybrid VF610 IOMUX Controller + +description: + Please refer to fsl,imx-pinctrl.txt in this directory for common binding part + and usage. + +maintainers: + - Frank Li + +properties: + compatible: + const: fsl,vf610-iomuxc + + reg: + maxItems: 1 + +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + two integers array, represents a group of pins mux and config setting. + The format is fsl,pins = , PIN_FUNC_ID is a pin + working on a specific function, CONFIG is the pad setting value such + as pull-up, speed, ode for this pin. Please refer to Vybrid VF610 + datasheet for the valid pad config settings. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: + PIN_FUN_ID refer to vf610-pinfunc.h in device tree source folder + for all available PIN_FUNC_ID for Vybrid VF610. + - description: | + CONFIG bits definition is + PAD_CTL_SPEED_LOW (1 << 12) + PAD_CTL_SPEED_MED (2 << 12) + PAD_CTL_SPEED_HIGH (3 << 12) + PAD_CTL_SRE_FAST (1 << 11) + PAD_CTL_SRE_SLOW (0 << 11) + PAD_CTL_ODE (1 << 10) + PAD_CTL_HYS (1 << 9) + PAD_CTL_DSE_DISABLE (0 << 6) + PAD_CTL_DSE_150ohm (1 << 6) + PAD_CTL_DSE_75ohm (2 << 6) + PAD_CTL_DSE_50ohm (3 << 6) + PAD_CTL_DSE_37ohm (4 << 6) + PAD_CTL_DSE_30ohm (5 << 6) + PAD_CTL_DSE_25ohm (6 << 6) + PAD_CTL_DSE_20ohm (7 << 6) + PAD_CTL_PUS_100K_DOWN (0 << 4) + PAD_CTL_PUS_47K_UP (1 << 4) + PAD_CTL_PUS_100K_UP (2 << 4) + PAD_CTL_PUS_22K_UP (3 << 4) + PAD_CTL_PKE (1 << 3) + PAD_CTL_PUE (1 << 2) + PAD_CTL_OBE_ENABLE (1 << 1) + PAD_CTL_IBE_ENABLE (1 << 0) + PAD_CTL_OBE_IBE_ENABLE (3 << 0) + + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + - reg + +allOf: + - $ref: pinctrl.yaml# + +unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,vf610-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,vf610-pinctrl.txt deleted file mode 100644 index ddcdeb697c292..0000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,vf610-pinctrl.txt +++ /dev/null @@ -1,41 +0,0 @@ -Freescale Vybrid VF610 IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,vf610-iomuxc" -- fsl,pins: two integers array, represents a group of pins mux and config - setting. The format is fsl,pins = , PIN_FUNC_ID is - a pin working on a specific function, CONFIG is the pad setting value - such as pull-up, speed, ode for this pin. Please refer to Vybrid VF610 - datasheet for the valid pad config settings. - -CONFIG bits definition: -PAD_CTL_SPEED_LOW (1 << 12) -PAD_CTL_SPEED_MED (2 << 12) -PAD_CTL_SPEED_HIGH (3 << 12) -PAD_CTL_SRE_FAST (1 << 11) -PAD_CTL_SRE_SLOW (0 << 11) -PAD_CTL_ODE (1 << 10) -PAD_CTL_HYS (1 << 9) -PAD_CTL_DSE_DISABLE (0 << 6) -PAD_CTL_DSE_150ohm (1 << 6) -PAD_CTL_DSE_75ohm (2 << 6) -PAD_CTL_DSE_50ohm (3 << 6) -PAD_CTL_DSE_37ohm (4 << 6) -PAD_CTL_DSE_30ohm (5 << 6) -PAD_CTL_DSE_25ohm (6 << 6) -PAD_CTL_DSE_20ohm (7 << 6) -PAD_CTL_PUS_100K_DOWN (0 << 4) -PAD_CTL_PUS_47K_UP (1 << 4) -PAD_CTL_PUS_100K_UP (2 << 4) -PAD_CTL_PUS_22K_UP (3 << 4) -PAD_CTL_PKE (1 << 3) -PAD_CTL_PUE (1 << 2) -PAD_CTL_OBE_ENABLE (1 << 1) -PAD_CTL_IBE_ENABLE (1 << 0) -PAD_CTL_OBE_IBE_ENABLE (3 << 0) - -Please refer to vf610-pinfunc.h in device tree source folder -for all available PIN_FUNC_ID for Vybrid VF610. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml index bccff08a5ba3f..b9680b896f12f 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml @@ -136,75 +136,44 @@ examples: #address-cells = <2>; #size-cells = <2>; - syscfg_pctl_a: syscfg-pctl-a@10005000 { - compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon"; - reg = <0 0x10005000 0 0x1000>; - }; - - syscfg_pctl_b: syscfg-pctl-b@1020c020 { - compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon"; - reg = <0 0x1020C020 0 0x1000>; - }; - pinctrl@1c20800 { - compatible = "mediatek,mt8135-pinctrl"; - reg = <0 0x1000B000 0 0x1000>; - mediatek,pctl-regmap = <&syscfg_pctl_a>, <&syscfg_pctl_b>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - ; - - i2c0_pins_a: i2c0-pins { - pins1 { - pinmux = , - ; - bias-disable; - }; - }; - - i2c1_pins_a: i2c1-pins { - pins { - pinmux = , - ; - bias-pull-up = ; + compatible = "mediatek,mt8135-pinctrl"; + reg = <0 0x1000B000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl_a>, <&syscfg_pctl_b>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + ; + + i2c0_pins_a: i2c0-pins { + pins1 { + pinmux = , + ; + bias-disable; + }; }; - }; - i2c2_pins_a: i2c2-pins { - pins1 { - pinmux = ; - bias-pull-down; + i2c1_pins_a: i2c1-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + }; }; - pins2 { - pinmux = ; - bias-pull-up; - }; - }; - - i2c3_pins_a: i2c3-pins { - pins1 { - pinmux = , - ; - bias-pull-up = ; - }; - - pins2 { - pinmux = , - ; - output-low; - bias-pull-up = ; - }; + i2c2_pins_a: i2c2-pins { + pins1 { + pinmux = ; + bias-pull-down; + }; - pins3 { - pinmux = , - ; - drive-strength = <32>; + pins2 { + pinmux = ; + bias-pull-up; + }; }; - }; }; }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml index 3bbc00df5548d..f4bab7a132d3c 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -245,9 +245,4 @@ examples: }; }; }; - - mmc0 { - pinctrl-0 = <&mmc0_pins_default>; - pinctrl-names = "default"; - }; }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6893-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6893-pinctrl.yaml new file mode 100644 index 0000000000000..fa189fe00624f --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6893-pinctrl.yaml @@ -0,0 +1,193 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6893-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6893 Pin Controller + +maintainers: + - AngeloGioacchino Del Regno + +description: + The MediaTek's MT6893 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt6893-pinctrl + + reg: + items: + - description: pin controller base + - description: rm group IO + - description: bm group IO + - description: lm group IO + - description: lb group IO + - description: rt group IO + - description: lt group IO + - description: tm group IO + - description: External Interrupt (EINT) controller base + + reg-names: + items: + - const: base + - const: rm + - const: bm + - const: lm + - const: lb + - const: rt + - const: lt + - const: tm + - const: eint + + gpio-controller: true + + '#gpio-cells': + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-line-names: true + + interrupts: + description: The interrupt outputs to sysirq + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +# PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^pins': + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + description: + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + + properties: + pinmux: + description: + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux are defined as macros in + arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h for this SoC. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + drive-strength-microamp: + enum: [125, 250, 500, 1000] + + bias-pull-down: + oneOf: + - type: boolean + - enum: [75000, 5000] + description: Pull down RSEL type resistance values (in ohms) + description: + For normal pull down type there is no need to specify a resistance + value, hence this can be specified as a boolean property. + For RSEL pull down type a resistance value (in ohms) can be added. + + bias-pull-up: + oneOf: + - type: boolean + - enum: [10000, 5000, 4000, 3000] + description: Pull up RSEL type resistance values (in ohms) + description: + For normal pull up type there is no need to specify a resistance + value, hence this can be specified as a boolean property. + For RSEL pull up type a resistance value (in ohms) can be added. + + bias-disable: true + + output-high: true + + output-low: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + #include + #define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) + #define PINMUX_GPIO99__FUNC_SCL0 (MTK_PIN_NO(99) | 1) + #define PINMUX_GPIO100__FUNC_SDA0 (MTK_PIN_NO(100) | 1) + + pio: pinctrl@10005000 { + compatible = "mediatek,mt6893-pinctrl"; + reg = <0x10005000 0x1000>, + <0x11c20000 0x0200>, + <0x11d10000 0x0200>, + <0x11e20000 0x0200>, + <0x11e70000 0x0200>, + <0x11ea0000 0x0200>, + <0x11f20000 0x0200>, + <0x11f30000 0x0200>, + <0x1100b000 0x1000>; + reg-names = "base", "rm", "bm", "lm", "lb", "rt", + "lt", "tm", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 220>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; + + gpio-pins { + pins { + pinmux = ; + bias-pull-up = <4000>; + drive-strength = <6>; + }; + }; + + i2c0-pins { + pins-bus { + pinmux = , + ; + bias-pull-down = <75000>; + drive-strength-microamp = <1000>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml index d74cae9d4d650..9acca85184fa2 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml @@ -366,34 +366,34 @@ examples: #size-cells = <2>; pio: pinctrl@10211000 { - compatible = "mediatek,mt7622-pinctrl"; - reg = <0 0x10211000 0 0x1000>; - gpio-controller; - #gpio-cells = <2>; - - pinctrl_eth_default: eth-pins { - mux-mdio { - groups = "mdc_mdio"; - function = "eth"; - drive-strength = <12>; + compatible = "mediatek,mt7622-pinctrl"; + reg = <0 0x10211000 0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + + pinctrl_eth_default: eth-pins { + mux-mdio { + groups = "mdc_mdio"; + function = "eth"; + drive-strength = <12>; + }; + + mux-gmac2 { + groups = "rgmii_via_gmac2"; + function = "eth"; + drive-strength = <12>; + }; + + mux-esw { + groups = "esw"; + function = "eth"; + drive-strength = <8>; + }; + + conf-mdio { + pins = "MDC"; + bias-pull-up; + }; }; - - mux-gmac2 { - groups = "rgmii_via_gmac2"; - function = "eth"; - drive-strength = <12>; - }; - - mux-esw { - groups = "esw"; - function = "eth"; - drive-strength = <8>; - }; - - conf-mdio { - pins = "MDC"; - bias-pull-up; - }; - }; }; }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml index 8507bd15f2431..464879274cae4 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml @@ -195,43 +195,43 @@ examples: #size-cells = <2>; pio: pinctrl@10005000 { - compatible = "mediatek,mt8183-pinctrl"; - reg = <0 0x10005000 0 0x1000>, - <0 0x11f20000 0 0x1000>, - <0 0x11e80000 0 0x1000>, - <0 0x11e70000 0 0x1000>, - <0 0x11e90000 0 0x1000>, - <0 0x11d30000 0 0x1000>, - <0 0x11d20000 0 0x1000>, - <0 0x11c50000 0 0x1000>, - <0 0x11f30000 0 0x1000>, - <0 0x1000b000 0 0x1000>; - reg-names = "iocfg0", "iocfg1", "iocfg2", - "iocfg3", "iocfg4", "iocfg5", - "iocfg6", "iocfg7", "iocfg8", - "eint"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 192>; - interrupt-controller; - interrupts = ; - #interrupt-cells = <2>; - - i2c0_pins_a: i2c0-pins { - pins1 { - pinmux = , - ; - mediatek,pull-up-adv = <3>; - drive-strength-microamp = <1000>; + compatible = "mediatek,mt8183-pinctrl"; + reg = <0 0x10005000 0 0x1000>, + <0 0x11f20000 0 0x1000>, + <0 0x11e80000 0 0x1000>, + <0 0x11e70000 0 0x1000>, + <0 0x11e90000 0 0x1000>, + <0 0x11d30000 0 0x1000>, + <0 0x11d20000 0 0x1000>, + <0 0x11c50000 0 0x1000>, + <0 0x11f30000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "iocfg0", "iocfg1", "iocfg2", + "iocfg3", "iocfg4", "iocfg5", + "iocfg6", "iocfg7", "iocfg8", + "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 192>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; + + i2c0_pins_a: i2c0-pins { + pins1 { + pinmux = , + ; + mediatek,pull-up-adv = <3>; + drive-strength-microamp = <1000>; + }; }; - }; - i2c1_pins_a: i2c1-pins { - pins { - pinmux = , - ; - mediatek,pull-down-adv = <2>; + i2c1_pins_a: i2c1-pins { + pins { + pinmux = , + ; + mediatek,pull-down-adv = <2>; + }; }; - }; }; }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml index 1686427eb8547..949dcd6fd847d 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml @@ -142,43 +142,43 @@ additionalProperties: false examples: - | - #include - #include - pio: pinctrl@10005000 { - compatible = "mediatek,mt8192-pinctrl"; - reg = <0x10005000 0x1000>, - <0x11c20000 0x1000>, - <0x11d10000 0x1000>, - <0x11d30000 0x1000>, - <0x11d40000 0x1000>, - <0x11e20000 0x1000>, - <0x11e70000 0x1000>, - <0x11ea0000 0x1000>, - <0x11f20000 0x1000>, - <0x11f30000 0x1000>, - <0x1000b000 0x1000>; - reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", - "iocfg_bl", "iocfg_br", "iocfg_lm", - "iocfg_lb", "iocfg_rt", "iocfg_lt", - "iocfg_tl", "eint"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 220>; - interrupt-controller; - interrupts = ; - #interrupt-cells = <2>; - - spi1-default-pins { - pins-cs-mosi-clk { - pinmux = , - , - ; - bias-disable; - }; - - pins-miso { - pinmux = ; - bias-pull-down; - }; - }; + #include + #include + pio: pinctrl@10005000 { + compatible = "mediatek,mt8192-pinctrl"; + reg = <0x10005000 0x1000>, + <0x11c20000 0x1000>, + <0x11d10000 0x1000>, + <0x11d30000 0x1000>, + <0x11d40000 0x1000>, + <0x11e20000 0x1000>, + <0x11e70000 0x1000>, + <0x11ea0000 0x1000>, + <0x11f20000 0x1000>, + <0x11f30000 0x1000>, + <0x1000b000 0x1000>; + reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", + "iocfg_bl", "iocfg_br", "iocfg_lm", + "iocfg_lb", "iocfg_rt", "iocfg_lt", + "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 220>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; + + spi1-default-pins { + pins-cs-mosi-clk { + pinmux = , + , + ; + bias-disable; }; + + pins-miso { + pinmux = ; + bias-pull-down; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8196-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8196-pinctrl.yaml new file mode 100644 index 0000000000000..9082bd625e2fe --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8196-pinctrl.yaml @@ -0,0 +1,236 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8196-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT8196 Pin Controller + +maintainers: + - Lei Xue + - Cathy Xu + +description: + The MediaTek's MT8196 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt8196-pinctrl + + reg: + items: + - description: gpio base + - description: rt group IO + - description: rm1 group IO + - description: rm2 group IO + - description: rb group IO + - description: bm1 group IO + - description: bm2 group IO + - description: bm3 group IO + - description: lt group IO + - description: lm1 group IO + - description: lm2 group IO + - description: lb1 group IO + - description: lb2 group IO + - description: tm1 group IO + - description: tm2 group IO + - description: tm3 group IO + - description: eint0 group IO + - description: eint1 group IO + - description: eint2 group IO + - description: eint3 group IO + - description: eint4 group IO + + reg-names: + items: + - const: base + - const: rt + - const: rm1 + - const: rm2 + - const: rb + - const: bm1 + - const: bm2 + - const: bm3 + - const: lt + - const: lm1 + - const: lm2 + - const: lb1 + - const: lb2 + - const: tm1 + - const: tm2 + - const: tm3 + - const: eint0 + - const: eint1 + - const: eint2 + - const: eint3 + - const: eint4 + + interrupts: + description: The interrupt outputs to sysirq. + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-controller: true + + '#gpio-cells': + description: + Number of cells in GPIO specifier, should be two. The first cell is the + pin number, the second cell is used to specify optional parameters which + are defined in . + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-line-names: true + +# PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^pins': + type: object + $ref: /schemas/pinctrl/pincfg-node.yaml + additionalProperties: false + description: + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + + properties: + pinmux: + description: + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h + directly, for this SoC. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + bias-pull-down: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: mt8196 pull down PUPD/R0/R1 type define value. + - enum: [75000, 5000] + description: mt8196 pull down RSEL type si unit value(ohm). + description: | + For pull down type is normal, it doesn't need add R1R0 define + and resistance value. + For pull down type is PUPD/R0/R1 type, it can add R1R0 define to + set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & + "MTK_PUPD_SET_R1R0_11" define in mt8196. + For pull down type is PD/RSEL, it can add resistance value(ohm) + to set different resistance by identifying property + "mediatek,rsel-resistance-in-si-unit". It can support resistance + value(ohm) "75000" & "5000" in mt8196. + + bias-pull-up: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: mt8196 pull up PUPD/R0/R1 type define value. + - enum: [1000, 1500, 2000, 3000, 4000, 5000, 75000] + description: mt8196 pull up RSEL type si unit value(ohm). + description: | + For pull up type is normal, it don't need add R1R0 define + and resistance value. + For pull up type is PUPD/R0/R1 type, it can add R1R0 define to + set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & + "MTK_PUPD_SET_R1R0_11" define in mt8196. + For pull up type is PU/RSEL, it can add resistance value(ohm) + to set different resistance by identifying property + "mediatek,rsel-resistance-in-si-unit". It can support resistance + value(ohm) "1000" & "1500" & "2000" & "3000" & "4000" & "5000" & + "75000" in mt8196. + + bias-disable: true + + output-high: true + + output-low: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + #include + #define PINMUX_GPIO99__FUNC_SCL0 (MTK_PIN_NO(99) | 1) + #define PINMUX_GPIO100__FUNC_SDA0 (MTK_PIN_NO(100) | 1) + + pio: pinctrl@1002d000 { + compatible = "mediatek,mt8196-pinctrl"; + reg = <0x1002d000 0x1000>, + <0x12000000 0x1000>, + <0x12020000 0x1000>, + <0x12040000 0x1000>, + <0x12060000 0x1000>, + <0x12820000 0x1000>, + <0x12840000 0x1000>, + <0x12860000 0x1000>, + <0x13000000 0x1000>, + <0x13020000 0x1000>, + <0x13040000 0x1000>, + <0x130f0000 0x1000>, + <0x13110000 0x1000>, + <0x13800000 0x1000>, + <0x13820000 0x1000>, + <0x13860000 0x1000>, + <0x12080000 0x1000>, + <0x12880000 0x1000>, + <0x13080000 0x1000>, + <0x13880000 0x1000>, + <0x1c54a000 0x1000>; + reg-names = "base", "rt", "rm1", "rm2", "rb" , "bm1", + "bm2", "bm3", "lt", "lm1", "lm2", "lb1", + "lb2", "tm1", "tm2", "tm3", "eint0", "eint1", + "eint2", "eint3", "eint4"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 271>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; + + i2c0-pins { + pins { + pinmux = , + ; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml index 1ce4b5df584ab..2791e578c1ded 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml @@ -110,7 +110,7 @@ examples: <0x03c00000 0x300000>; reg-names = "east", "west", "south"; interrupts = ; - gpio-ranges = <&tlmm 0 0 123>; + gpio-ranges = <&tlmm 0 0 124>; gpio-controller; #gpio-cells = <2>; interrupt-controller; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml index bb0d7132886a1..489b41dcc1793 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml @@ -106,7 +106,7 @@ examples: interrupts = ; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&tlmm 0 0 133>; + gpio-ranges = <&tlmm 0 0 134>; interrupt-controller; #interrupt-cells = <2>; diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index 768bb3c2b4561..5156d54b240b1 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -27,6 +27,7 @@ properties: - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} - renesas,r9a08g045-pinctrl # RZ/G3S - renesas,r9a09g047-pinctrl # RZ/G3E + - renesas,r9a09g056-pinctrl # RZ/V2N - renesas,r9a09g057-pinctrl # RZ/V2H(P) - items: @@ -145,6 +146,7 @@ allOf: contains: enum: - renesas,r9a09g047-pinctrl + - renesas,r9a09g056-pinctrl - renesas,r9a09g057-pinctrl then: properties: diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml index 816688580e334..aa882b5bfe97f 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml @@ -13,9 +13,7 @@ maintainers: properties: compatible: items: - - enum: - - renesas,r9a06g032-pinctrl # RZ/N1D - - renesas,r9a06g033-pinctrl # RZ/N1S + - const: renesas,r9a06g032-pinctrl # RZ/N1D - const: renesas,rzn1-pinctrl # Generic RZ/N1 reg: diff --git a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml index b01ecd83b71b5..d80e88aa07b45 100644 --- a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml @@ -17,6 +17,19 @@ properties: items: - description: pinctrl io memory base + clocks: + items: + - description: Functional Clock + - description: Bus Clock + + clock-names: + items: + - const: func + - const: bus + + resets: + maxItems: 1 + patternProperties: '-cfg$': type: object @@ -94,6 +107,8 @@ patternProperties: required: - compatible - reg + - clocks + - clock-names additionalProperties: false @@ -108,6 +123,9 @@ examples: pinctrl@d401e000 { compatible = "spacemit,k1-pinctrl"; reg = <0x0 0xd401e000 0x0 0x400>; + clocks = <&syscon_apbc 42>, + <&syscon_apbc 94>; + clock-names = "func", "bus"; uart0_2_cfg: uart0-2-cfg { uart0-2-pins { diff --git a/Documentation/devicetree/bindings/power/allwinner,sun50i-h6-prcm-ppu.yaml b/Documentation/devicetree/bindings/power/allwinner,sun50i-h6-prcm-ppu.yaml new file mode 100644 index 0000000000000..73a9b4d6220e6 --- /dev/null +++ b/Documentation/devicetree/bindings/power/allwinner,sun50i-h6-prcm-ppu.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/allwinner,sun50i-h6-prcm-ppu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner SoCs PRCM power domain controller + +maintainers: + - Andre Przywara + +description: + The Allwinner Power Reset Clock Management (PRCM) unit contains bits to + control a few power domains. + +properties: + compatible: + enum: + - allwinner,sun50i-h6-prcm-ppu + - allwinner,sun50i-h616-prcm-ppu + - allwinner,sun55i-a523-prcm-ppu + + reg: + maxItems: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + prcm_ppu: power-controller@7010210 { + compatible = "allwinner,sun50i-h616-prcm-ppu"; + reg = <0x7010210 0x10>; + #power-domain-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml index 591a080ca3ff0..9c7cc632abee2 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -25,6 +25,7 @@ properties: enum: - mediatek,mt6735-power-controller - mediatek,mt6795-power-controller + - mediatek,mt6893-power-controller - mediatek,mt8167-power-controller - mediatek,mt8173-power-controller - mediatek,mt8183-power-controller @@ -88,6 +89,7 @@ $defs: description: | Power domain index. Valid values are defined in: "include/dt-bindings/power/mt6795-power.h" - for MT8167 type power domain. + "include/dt-bindings/power/mediatek,mt6893-power.h" - for MT6893 type power domain. "include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain. "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain. "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain. diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index 655687369a238..1bf65f2a583ab 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -50,6 +50,7 @@ properties: - qcom,sdx55-rpmhpd - qcom,sdx65-rpmhpd - qcom,sdx75-rpmhpd + - qcom,sm4450-rpmhpd - qcom,sm6115-rpmpd - qcom,sm6125-rpmpd - qcom,sm6350-rpmhpd diff --git a/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml b/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml index 19d3093e6cd2f..ccd5558700943 100644 --- a/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml +++ b/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml @@ -21,7 +21,9 @@ description: |+ properties: compatible: - const: syscon-reboot + enum: + - syscon-reboot + - google,gs101-reboot mask: $ref: /schemas/types.yaml#/definitions/uint32 @@ -49,12 +51,6 @@ properties: priority: default: 192 -oneOf: - - required: - - offset - - required: - - reg - required: - compatible @@ -63,12 +59,29 @@ additionalProperties: false allOf: - $ref: restart-handler.yaml# - if: - not: - required: - - mask + properties: + compatible: + contains: + const: google,gs101-reboot then: - required: - - value + properties: + mask: false + offset: false + reg: false + value: false + + else: + if: + not: + required: + - mask + then: + required: + - value + + oneOf: + - required: [offset] + - required: [reg] examples: - | @@ -78,3 +91,8 @@ examples: offset = <0x0>; mask = <0x1>; }; + + - | + reboot { + compatible = "google,gs101-reboot"; + }; diff --git a/Documentation/devicetree/bindings/power/reset/toradex,smarc-ec.yaml b/Documentation/devicetree/bindings/power/reset/toradex,smarc-ec.yaml new file mode 100644 index 0000000000000..ffcd5f2c2bf6b --- /dev/null +++ b/Documentation/devicetree/bindings/power/reset/toradex,smarc-ec.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/reset/toradex,smarc-ec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toradex Embedded Controller + +maintainers: + - Emanuele Ghidoli + - Francesco Dolcini + +description: | + The Toradex Embedded Controller (EC) is used on Toradex SMARC modules, + primarily to manage power and reset functionalities. + + The EC provides the following functions: + - Reads the SMARC POWER_BTN# and RESET_IN# signals and controls the PMIC accordingly. + - Controls the SoC boot mode signals based on the SMARC BOOT_SEL# and FORCE_RECOV# inputs. + - Manages the CARRIER_STDBY# signal in response to relevant SoC signals. + + The EC runs a small firmware, factory programmed into its internal flash, and communicates over I2C. + It allows software to control power-off and reset functionalities of the module. + +properties: + compatible: + items: + - enum: + - toradex,smarc-imx95-ec + - toradex,smarc-imx8mp-ec + - const: toradex,smarc-ec + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + reset-controller@28 { + compatible = "toradex,smarc-imx95-ec", "toradex,smarc-ec"; + reg = <0x28>; + }; + }; diff --git a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml index ebab98987e492..f494b7710c099 100644 --- a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml @@ -40,6 +40,7 @@ properties: - rockchip,rk3366-power-controller - rockchip,rk3368-power-controller - rockchip,rk3399-power-controller + - rockchip,rk3562-power-controller - rockchip,rk3568-power-controller - rockchip,rk3576-power-controller - rockchip,rk3588-power-controller diff --git a/Documentation/devicetree/bindings/power/supply/bq24190.yaml b/Documentation/devicetree/bindings/power/supply/bq24190.yaml index 07adf88997b4e..307c99c077217 100644 --- a/Documentation/devicetree/bindings/power/supply/bq24190.yaml +++ b/Documentation/devicetree/bindings/power/supply/bq24190.yaml @@ -19,6 +19,7 @@ properties: - ti,bq24190 - ti,bq24192 - ti,bq24192i + - ti,bq24193 - ti,bq24196 - ti,bq24296 - ti,bq24297 diff --git a/Documentation/devicetree/bindings/power/supply/bq25980.yaml b/Documentation/devicetree/bindings/power/supply/bq25980.yaml index b70ce8d7f86c2..256adbef55ebf 100644 --- a/Documentation/devicetree/bindings/power/supply/bq25980.yaml +++ b/Documentation/devicetree/bindings/power/supply/bq25980.yaml @@ -87,28 +87,28 @@ unevaluatedProperties: false examples: - | bat: battery { - compatible = "simple-battery"; - constant-charge-current-max-microamp = <4000000>; - constant-charge-voltage-max-microvolt = <8400000>; - precharge-current-microamp = <160000>; - charge-term-current-microamp = <160000>; + compatible = "simple-battery"; + constant-charge-current-max-microamp = <4000000>; + constant-charge-voltage-max-microvolt = <8400000>; + precharge-current-microamp = <160000>; + charge-term-current-microamp = <160000>; }; #include #include i2c { - #address-cells = <1>; - #size-cells = <0>; - - bq25980: charger@65 { - compatible = "ti,bq25980"; - reg = <0x65>; - interrupt-parent = <&gpio1>; - interrupts = <16 IRQ_TYPE_EDGE_FALLING>; - ti,watchdog-timeout-ms = <0>; - ti,sc-ocp-limit-microamp = <2000000>; - ti,sc-ovp-limit-microvolt = <17800000>; - monitored-battery = <&bat>; - }; + #address-cells = <1>; + #size-cells = <0>; + + bq25980: charger@65 { + compatible = "ti,bq25980"; + reg = <0x65>; + interrupt-parent = <&gpio1>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; + ti,watchdog-timeout-ms = <0>; + ti,sc-ocp-limit-microamp = <2000000>; + ti,sc-ovp-limit-microvolt = <17800000>; + monitored-battery = <&bat>; + }; }; ... diff --git a/Documentation/devicetree/bindings/power/supply/ingenic,battery.yaml b/Documentation/devicetree/bindings/power/supply/ingenic,battery.yaml index 741022b4449da..cb04fb25d8ac0 100644 --- a/Documentation/devicetree/bindings/power/supply/ingenic,battery.yaml +++ b/Documentation/devicetree/bindings/power/supply/ingenic,battery.yaml @@ -48,14 +48,14 @@ examples: #include simple_battery: battery { - compatible = "simple-battery"; - voltage-min-design-microvolt = <3600000>; - voltage-max-design-microvolt = <4200000>; + compatible = "simple-battery"; + voltage-min-design-microvolt = <3600000>; + voltage-max-design-microvolt = <4200000>; }; ingenic-battery { - compatible = "ingenic,jz4740-battery"; - io-channels = <&adc INGENIC_ADC_BATTERY>; - io-channel-names = "battery"; - monitored-battery = <&simple_battery>; + compatible = "ingenic,jz4740-battery"; + io-channels = <&adc INGENIC_ADC_BATTERY>; + io-channel-names = "battery"; + monitored-battery = <&simple_battery>; }; diff --git a/Documentation/devicetree/bindings/power/supply/ltc4162-l.yaml b/Documentation/devicetree/bindings/power/supply/ltc4162-l.yaml index 06595a9536592..bc7ed7b220857 100644 --- a/Documentation/devicetree/bindings/power/supply/ltc4162-l.yaml +++ b/Documentation/devicetree/bindings/power/supply/ltc4162-l.yaml @@ -61,13 +61,13 @@ additionalProperties: false examples: - | i2c { - #address-cells = <1>; - #size-cells = <0>; - charger: battery-charger@68 { - compatible = "lltc,ltc4162-l"; - reg = <0x68>; - lltc,rsnsb-micro-ohms = <10000>; - lltc,rsnsi-micro-ohms = <16000>; - lltc,cell-count = <2>; - }; + #address-cells = <1>; + #size-cells = <0>; + charger: battery-charger@68 { + compatible = "lltc,ltc4162-l"; + reg = <0x68>; + lltc,rsnsb-micro-ohms = <10000>; + lltc,rsnsi-micro-ohms = <16000>; + lltc,cell-count = <2>; + }; }; diff --git a/Documentation/devicetree/bindings/power/supply/maxim,max77705.yaml b/Documentation/devicetree/bindings/power/supply/maxim,max77705.yaml index bce7fabbd9d3c..e3b84068993ba 100644 --- a/Documentation/devicetree/bindings/power/supply/maxim,max77705.yaml +++ b/Documentation/devicetree/bindings/power/supply/maxim,max77705.yaml @@ -37,8 +37,8 @@ examples: #include i2c { - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; charger@69 { compatible = "maxim,max77705-charger"; diff --git a/Documentation/devicetree/bindings/power/supply/maxim,max8971.yaml b/Documentation/devicetree/bindings/power/supply/maxim,max8971.yaml new file mode 100644 index 0000000000000..2244cc3d45a6f --- /dev/null +++ b/Documentation/devicetree/bindings/power/supply/maxim,max8971.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/supply/maxim,max8971.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim MAX8971 IC charger + +maintainers: + - Svyatoslav Ryhel + +description: + The MAX8971 is a compact, high-frequency, high-efficiency switch-mode charger + for a one-cell lithium-ion (Li+) battery. + +allOf: + - $ref: power-supply.yaml# + +properties: + compatible: + const: maxim,max8971 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + monitored-battery: true + + port: + description: + An optional port node to link the extcon device to detect type of plug. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + charger@35 { + compatible = "maxim,max8971"; + reg = <0x35>; + + interrupt-parent = <&gpio>; + interrupts = <74 IRQ_TYPE_LEVEL_LOW>; + + monitored-battery = <&battery>; + + port { + charger_input: endpoint { + remote-endpoint = <&extcon_output>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/power/supply/pegatron,chagall-ec.yaml b/Documentation/devicetree/bindings/power/supply/pegatron,chagall-ec.yaml new file mode 100644 index 0000000000000..defb0861e2688 --- /dev/null +++ b/Documentation/devicetree/bindings/power/supply/pegatron,chagall-ec.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/supply/pegatron,chagall-ec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Pegatron Chagall EC + +maintainers: + - Svyatoslav Ryhel + +description: + Pegatron Chagall EC is based on an 8-bit programmable microcontroller from + Infineon/Cypress Semiconductor, it communicates over I2C and is used in the + Pegatron Chagall tablet for fuel gauge and battery control functions. + +$ref: /schemas/power/supply/power-supply.yaml + +properties: + compatible: + const: pegatron,chagall-ec + + reg: + maxItems: 1 + + monitored-battery: true + power-supplies: true + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + embedded-controller@10 { + compatible = "pegatron,chagall-ec"; + reg = <0x10>; + + monitored-battery = <&battery>; + power-supplies = <&mains>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/power/supply/qcom,pmi8998-charger.yaml b/Documentation/devicetree/bindings/power/supply/qcom,pmi8998-charger.yaml index a0f9d49ff8fb6..90c7dc7632c58 100644 --- a/Documentation/devicetree/bindings/power/supply/qcom,pmi8998-charger.yaml +++ b/Documentation/devicetree/bindings/power/supply/qcom,pmi8998-charger.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm PMI8998/PM660 Switch-Mode Battery Charger "2" maintainers: - - Caleb Connolly + - Casey Connolly properties: compatible: diff --git a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt b/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt deleted file mode 100644 index 07256b7ffcaab..0000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt +++ /dev/null @@ -1,63 +0,0 @@ -* Power Management Controller - -Properties: -- compatible: "fsl,-pmc". - - "fsl,mpc8349-pmc" should be listed for any chip whose PMC is - compatible. "fsl,mpc8313-pmc" should also be listed for any chip - whose PMC is compatible, and implies deep-sleep capability. - - "fsl,mpc8548-pmc" should be listed for any chip whose PMC is - compatible. "fsl,mpc8536-pmc" should also be listed for any chip - whose PMC is compatible, and implies deep-sleep capability. - - "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is - compatible; all statements below that apply to "fsl,mpc8548-pmc" also - apply to "fsl,mpc8641d-pmc". - - Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these - bit assignments are indicated via the sleep specifier in each device's - sleep property. - -- reg: For devices compatible with "fsl,mpc8349-pmc", the first resource - is the PMC block, and the second resource is the Clock Configuration - block. - - For devices compatible with "fsl,mpc8548-pmc", the first resource - is a 32-byte block beginning with DEVDISR. - -- interrupts: For "fsl,mpc8349-pmc"-compatible devices, the first - resource is the PMC block interrupt. - -- fsl,mpc8313-wakeup-timer: For "fsl,mpc8313-pmc"-compatible devices, - this is a phandle to an "fsl,gtm" node on which timer 4 can be used as - a wakeup source from deep sleep. - -Sleep specifiers: - - fsl,mpc8349-pmc: Sleep specifiers consist of one cell. For each bit - that is set in the cell, the corresponding bit in SCCR will be saved - and cleared on suspend, and restored on resume. This sleep controller - supports disabling and resuming devices at any time. - - fsl,mpc8536-pmc: Sleep specifiers consist of three cells, the third of - which will be ORed into PMCDR upon suspend, and cleared from PMCDR - upon resume. The first two cells are as described for fsl,mpc8578-pmc. - This sleep controller only supports disabling devices during system - sleep, or permanently. - - fsl,mpc8548-pmc: Sleep specifiers consist of one or two cells, the - first of which will be ORed into DEVDISR (and the second into - DEVDISR2, if present -- this cell should be zero or absent if the - hardware does not have DEVDISR2) upon a request for permanent device - disabling. This sleep controller does not support configuring devices - to disable during system sleep (unless supported by another compatible - match), or dynamically. - -Example: - - power@b00 { - compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc"; - reg = <0xb00 0x100 0xa00 0x100>; - interrupts = <80 8>; - }; diff --git a/Documentation/devicetree/bindings/powerpc/fsl/pmc.yaml b/Documentation/devicetree/bindings/powerpc/fsl/pmc.yaml new file mode 100644 index 0000000000000..276ece7f01dba --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/pmc.yaml @@ -0,0 +1,152 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/powerpc/fsl/pmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Power Management Controller + +maintainers: + - J. Neuschäfer + +description: | + The Power Management Controller in several MPC8xxx SoCs helps save power by + controlling chip-wide low-power states as well as peripheral clock gating. + + Sleep of peripheral devices is configured by the `sleep` property, for + example `sleep = <&pmc 0x00000030>`. Any cells after the &pmc phandle are + called a sleep specifier. + + For "fsl,mpc8349-pmc", sleep specifiers consist of one cell. For each bit that + is set in the cell, the corresponding bit in SCCR will be saved and cleared + on suspend, and restored on resume. This sleep controller supports disabling + and resuming devices at any time. + + For "fsl,mpc8536-pmc", sleep specifiers consist of three cells, the third of + which will be ORed into PMCDR upon suspend, and cleared from PMCDR upon + resume. The first two cells are as described for fsl,mpc8548-pmc. This + sleep controller only supports disabling devices during system sleep, or + permanently. + + For "fsl,mpc8548-pmc" or "fsl,mpc8641d-pmc", Sleep specifiers consist of one + or two cells, the first of which will be ORed into DEVDISR (and the second + into DEVDISR2, if present -- this cell should be zero or absent if the + hardware does not have DEVDISR2) upon a request for permanent device + disabling. This sleep controller does not support configuring devices to + disable during system sleep (unless supported by another compatible match), + or dynamically. + +properties: + compatible: + oneOf: + - items: + - const: fsl,mpc8315-pmc + - const: fsl,mpc8313-pmc + - const: fsl,mpc8349-pmc + + - items: + - enum: + - fsl,mpc8313-pmc + - fsl,mpc8323-pmc + - fsl,mpc8360-pmc + - fsl,mpc8377-pmc + - fsl,mpc8378-pmc + - fsl,mpc8379-pmc + - const: fsl,mpc8349-pmc + + - items: + - const: fsl,p1022-pmc + - const: fsl,mpc8536-pmc + - const: fsl,mpc8548-pmc + + - items: + - enum: + - fsl,mpc8536-pmc + - fsl,mpc8568-pmc + - fsl,mpc8569-pmc + - const: fsl,mpc8548-pmc + + - enum: + - fsl,mpc8548-pmc + - fsl,mpc8641d-pmc + + description: | + "fsl,mpc8349-pmc" should be listed for any chip whose PMC is + compatible. "fsl,mpc8313-pmc" should also be listed for any chip + whose PMC is compatible, and implies deep-sleep capability. + + "fsl,mpc8548-pmc" should be listed for any chip whose PMC is + compatible. "fsl,mpc8536-pmc" should also be listed for any chip + whose PMC is compatible, and implies deep-sleep capability. + + "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is + compatible; all statements below that apply to "fsl,mpc8548-pmc" also + apply to "fsl,mpc8641d-pmc". + + Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these + bit assignments are indicated via the sleep specifier in each device's + sleep property. + + reg: + minItems: 1 + maxItems: 2 + + interrupts: + maxItems: 1 + + fsl,mpc8313-wakeup-timer: + $ref: /schemas/types.yaml#/definitions/phandle + description: + For "fsl,mpc8313-pmc"-compatible devices, this is a phandle to an + "fsl,gtm" node on which timer 4 can be used as a wakeup source from deep + sleep. + +allOf: + - if: + properties: + compatible: + contains: + const: fsl,mpc8349-pmc + then: + properties: + reg: + items: + - description: PMC block + - description: Clock Configuration block + + - if: + properties: + compatible: + contains: + enum: + - fsl,mpc8548-pmc + - fsl,mpc8641d-pmc + then: + properties: + reg: + items: + - description: 32-byte block beginning with DEVDISR + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + pmc: power@b00 { + compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc"; + reg = <0xb00 0x100>, <0xa00 0x100>; + interrupts = <80 IRQ_TYPE_LEVEL_LOW>; + }; + + - | + power@e0070 { + compatible = "fsl,mpc8548-pmc"; + reg = <0xe0070 0x20>; + }; + +... diff --git a/Documentation/devicetree/bindings/pwm/loongson,ls7a-pwm.yaml b/Documentation/devicetree/bindings/pwm/loongson,ls7a-pwm.yaml new file mode 100644 index 0000000000000..5d64fb40a0d62 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/loongson,ls7a-pwm.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/loongson,ls7a-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson PWM Controller + +maintainers: + - Binbin Zhou + +description: + The Loongson PWM has one pulse width output signal and one pulse input + signal to be measured. + It can be found on Loongson-2K series cpus and Loongson LS7A bridge chips. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + oneOf: + - const: loongson,ls7a-pwm + - items: + - enum: + - loongson,ls2k0500-pwm + - loongson,ls2k1000-pwm + - loongson,ls2k2000-pwm + - const: loongson,ls7a-pwm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + '#pwm-cells': + description: + The first cell must have a value of 0, which specifies the PWM output signal; + The second cell is the period in nanoseconds; + The third cell flag supported by this binding is PWM_POLARITY_INVERTED. + const: 3 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + + pwm@1fe22000 { + compatible = "loongson,ls2k1000-pwm", "loongson,ls7a-pwm"; + reg = <0x1fe22000 0x10>; + interrupt-parent = <&liointc0>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LOONGSON2_APB_CLK>; + #pwm-cells = <3>; + }; diff --git a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml index 195e4371196be..68ef30414325a 100644 --- a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml +++ b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml @@ -27,6 +27,7 @@ properties: - const: mediatek,mt8173-disp-pwm - items: - enum: + - mediatek,mt6893-disp-pwm - mediatek,mt8186-disp-pwm - mediatek,mt8188-disp-pwm - mediatek,mt8192-disp-pwm diff --git a/Documentation/devicetree/bindings/pwm/nxp,mc33xs2410.yaml b/Documentation/devicetree/bindings/pwm/nxp,mc33xs2410.yaml new file mode 100644 index 0000000000000..1729fe5c3dfb0 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/nxp,mc33xs2410.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/nxp,mc33xs2410.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: High-side switch MC33XS2410 + +maintainers: + - Dimitri Fedrau + +allOf: + - $ref: pwm.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + const: nxp,mc33xs2410 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 10000000 + + spi-cpha: true + + spi-cs-setup-delay-ns: + minimum: 100 + default: 100 + + spi-cs-hold-delay-ns: + minimum: 10 + default: 10 + + spi-cs-inactive-delay-ns: + minimum: 300 + default: 300 + + reset-gpios: + description: + GPIO connected to the active low reset pin. + maxItems: 1 + + "#pwm-cells": + const: 3 + + pwm-names: + items: + - const: di0 + - const: di1 + - const: di2 + - const: di3 + + pwms: + description: + Direct inputs(di0-3) are used to directly turn-on or turn-off the + outputs. + maxItems: 4 + + interrupts: + maxItems: 1 + + clocks: + description: + The external clock can be used if the internal clock doesn't meet + timing requirements over temperature and voltage operating range. + maxItems: 1 + + vdd-supply: + description: + Logic supply voltage + + vspi-supply: + description: + Supply voltage for SPI + + vpwr-supply: + description: + Power switch supply + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + #include + spi { + #address-cells = <1>; + #size-cells = <0>; + + pwm@0 { + compatible = "nxp,mc33xs2410"; + reg = <0x0>; + spi-max-frequency = <4000000>; + spi-cpha; + spi-cs-setup-delay-ns = <100>; + spi-cs-hold-delay-ns = <10>; + spi-cs-inactive-delay-ns = <300>; + reset-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; + #pwm-cells = <3>; + pwm-names = "di0", "di1", "di2", "di3"; + pwms = <&pwm0 0 1000000>, + <&pwm1 0 1000000>, + <&pwm2 0 1000000>, + <&pwm3 0 1000000>; + interrupt-parent = <&gpio0>; + interrupts = <31 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk_ext_fixed>; + vdd-supply = <®_3v3>; + vspi-supply = <®_3v3>; + vpwr-supply = <®_24v0>; + }; + }; diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml new file mode 100644 index 0000000000000..13b807765a307 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml @@ -0,0 +1,378 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/renesas,rzg2l-gpt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G2L General PWM Timer (GPT) + +maintainers: + - Biju Das + +description: | + RZ/G2L General PWM Timer (GPT) composed of 8 channels with 32-bit timer + (GPT32E). It supports the following functions + * 32 bits x 8 channels. + * Up-counting or down-counting (saw waves) or up/down-counting + (triangle waves) for each counter. + * Clock sources independently selectable for each channel. + * Two I/O pins per channel. + * Two output compare/input capture registers per channel. + * For the two output compare/input capture registers of each channel, + four registers are provided as buffer registers and are capable of + operating as comparison registers when buffering is not in use. + * In output compare operation, buffer switching can be at crests or + troughs, enabling the generation of laterally asymmetric PWM waveforms. + * Registers for setting up frame cycles in each channel (with capability + for generating interrupts at overflow or underflow) + * Generation of dead times in PWM operation. + * Synchronous starting, stopping and clearing counters for arbitrary + channels. + * Starting, stopping, clearing and up/down counters in response to input + level comparison. + * Starting, clearing, stopping and up/down counters in response to a + maximum of four external triggers. + * Output pin disable function by dead time error and detected + short-circuits between output pins. + * A/D converter start triggers can be generated (GPT32E0 to GPT32E3) + * Enables the noise filter for input capture and external trigger + operation. + + The below pwm channels are supported. + pwm0 - GPT32E0.GTIOC0A channel + pwm1 - GPT32E0.GTIOC0B channel + pwm2 - GPT32E1.GTIOC1A channel + pwm3 - GPT32E1.GTIOC1B channel + pwm4 - GPT32E2.GTIOC2A channel + pwm5 - GPT32E2.GTIOC2B channel + pwm6 - GPT32E3.GTIOC3A channel + pwm7 - GPT32E3.GTIOC3B channel + pwm8 - GPT32E4.GTIOC4A channel + pwm9 - GPT32E4.GTIOC4B channel + pwm10 - GPT32E5.GTIOC5A channel + pwm11 - GPT32E5.GTIOC5B channel + pwm12 - GPT32E6.GTIOC6A channel + pwm13 - GPT32E6.GTIOC6B channel + pwm14 - GPT32E7.GTIOC7A channel + pwm15 - GPT32E7.GTIOC7B channel + +properties: + compatible: + items: + - enum: + - renesas,r9a07g044-gpt # RZ/G2{L,LC} + - renesas,r9a07g054-gpt # RZ/V2L + - const: renesas,rzg2l-gpt + + reg: + maxItems: 1 + + '#pwm-cells': + const: 3 + + interrupts: + items: + - description: GPT32E0.GTCCRA input capture/compare match + - description: GPT32E0.GTCCRB input capture/compare + - description: GPT32E0.GTCCRC compare match + - description: GPT32E0.GTCCRD compare match + - description: GPT32E0.GTCCRE compare match + - description: GPT32E0.GTCCRF compare match + - description: GPT32E0.GTADTRA compare match + - description: GPT32E0.GTADTRB compare match + - description: GPT32E0.GTCNT overflow/GTPR compare match + - description: GPT32E0.GTCNT underflow + - description: GPT32E1.GTCCRA input capture/compare match + - description: GPT32E1.GTCCRB input capture/compare + - description: GPT32E1.GTCCRC compare match + - description: GPT32E1.GTCCRD compare match + - description: GPT32E1.GTCCRE compare match + - description: GPT32E1.GTCCRF compare match + - description: GPT32E1.GTADTRA compare match + - description: GPT32E1.GTADTRB compare match + - description: GPT32E1.GTCNT overflow/GTPR compare match + - description: GPT32E1.GTCNT underflow + - description: GPT32E2.GTCCRA input capture/compare match + - description: GPT32E2.GTCCRB input capture/compare + - description: GPT32E2.GTCCRC compare match + - description: GPT32E2.GTCCRD compare match + - description: GPT32E2.GTCCRE compare match + - description: GPT32E2.GTCCRF compare match + - description: GPT32E2.GTADTRA compare match + - description: GPT32E2.GTADTRB compare match + - description: GPT32E2.GTCNT overflow/GTPR compare match + - description: GPT32E2.GTCNT underflow + - description: GPT32E3.GTCCRA input capture/compare match + - description: GPT32E3.GTCCRB input capture/compare + - description: GPT32E3.GTCCRC compare match + - description: GPT32E3.GTCCRD compare match + - description: GPT32E3.GTCCRE compare match + - description: GPT32E3.GTCCRF compare match + - description: GPT32E3.GTADTRA compare match + - description: GPT32E3.GTADTRB compare match + - description: GPT32E3.GTCNT overflow/GTPR compare match + - description: GPT32E3.GTCNT underflow + - description: GPT32E4.GTCCRA input capture/compare match + - description: GPT32E4.GTCCRB input capture/compare + - description: GPT32E4.GTCCRC compare match + - description: GPT32E4.GTCCRD compare match + - description: GPT32E4.GTCCRE compare match + - description: GPT32E4.GTCCRF compare match + - description: GPT32E4.GTADTRA compare match + - description: GPT32E4.GTADTRB compare match + - description: GPT32E4.GTCNT overflow/GTPR compare match + - description: GPT32E4.GTCNT underflow + - description: GPT32E5.GTCCRA input capture/compare match + - description: GPT32E5.GTCCRB input capture/compare + - description: GPT32E5.GTCCRC compare match + - description: GPT32E5.GTCCRD compare match + - description: GPT32E5.GTCCRE compare match + - description: GPT32E5.GTCCRF compare match + - description: GPT32E5.GTADTRA compare match + - description: GPT32E5.GTADTRB compare match + - description: GPT32E5.GTCNT overflow/GTPR compare match + - description: GPT32E5.GTCNT underflow + - description: GPT32E6.GTCCRA input capture/compare match + - description: GPT32E6.GTCCRB input capture/compare + - description: GPT32E6.GTCCRC compare match + - description: GPT32E6.GTCCRD compare match + - description: GPT32E6.GTCCRE compare match + - description: GPT32E6.GTCCRF compare match + - description: GPT32E6.GTADTRA compare match + - description: GPT32E6.GTADTRB compare match + - description: GPT32E6.GTCNT overflow/GTPR compare match + - description: GPT32E6.GTCNT underflow + - description: GPT32E7.GTCCRA input capture/compare match + - description: GPT32E7.GTCCRB input capture/compare + - description: GPT32E7.GTCCRC compare match + - description: GPT32E7.GTCCRD compare match + - description: GPT32E7.GTCCRE compare match + - description: GPT32E7.GTCCRF compare match + - description: GPT32E7.GTADTRA compare match + - description: GPT32E7.GTADTRB compare match + - description: GPT32E7.GTCNT overflow/GTPR compare match + - description: GPT32E7.GTCNT underflow + + interrupt-names: + items: + - const: ccmpa0 + - const: ccmpb0 + - const: cmpc0 + - const: cmpd0 + - const: cmpe0 + - const: cmpf0 + - const: adtrga0 + - const: adtrgb0 + - const: ovf0 + - const: unf0 + - const: ccmpa1 + - const: ccmpb1 + - const: cmpc1 + - const: cmpd1 + - const: cmpe1 + - const: cmpf1 + - const: adtrga1 + - const: adtrgb1 + - const: ovf1 + - const: unf1 + - const: ccmpa2 + - const: ccmpb2 + - const: cmpc2 + - const: cmpd2 + - const: cmpe2 + - const: cmpf2 + - const: adtrga2 + - const: adtrgb2 + - const: ovf2 + - const: unf2 + - const: ccmpa3 + - const: ccmpb3 + - const: cmpc3 + - const: cmpd3 + - const: cmpe3 + - const: cmpf3 + - const: adtrga3 + - const: adtrgb3 + - const: ovf3 + - const: unf3 + - const: ccmpa4 + - const: ccmpb4 + - const: cmpc4 + - const: cmpd4 + - const: cmpe4 + - const: cmpf4 + - const: adtrga4 + - const: adtrgb4 + - const: ovf4 + - const: unf4 + - const: ccmpa5 + - const: ccmpb5 + - const: cmpc5 + - const: cmpd5 + - const: cmpe5 + - const: cmpf5 + - const: adtrga5 + - const: adtrgb5 + - const: ovf5 + - const: unf5 + - const: ccmpa6 + - const: ccmpb6 + - const: cmpc6 + - const: cmpd6 + - const: cmpe6 + - const: cmpf6 + - const: adtrga6 + - const: adtrgb6 + - const: ovf6 + - const: unf6 + - const: ccmpa7 + - const: ccmpb7 + - const: cmpc7 + - const: cmpd7 + - const: cmpe7 + - const: cmpf7 + - const: adtrga7 + - const: adtrgb7 + - const: ovf7 + - const: unf7 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - power-domains + - resets + +allOf: + - $ref: pwm.yaml# + +additionalProperties: false + +examples: + - | + #include + #include + + gpt: pwm@10048000 { + compatible = "renesas,r9a07g044-gpt", "renesas,rzg2l-gpt"; + reg = <0x10048000 0x800>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa0", "ccmpb0", "cmpc0", "cmpd0", + "cmpe0", "cmpf0", "adtrga0", "adtrgb0", + "ovf0", "unf0", + "ccmpa1", "ccmpb1", "cmpc1", "cmpd1", + "cmpe1", "cmpf1", "adtrga1", "adtrgb1", + "ovf1", "unf1", + "ccmpa2", "ccmpb2", "cmpc2", "cmpd2", + "cmpe2", "cmpf2", "adtrga2", "adtrgb2", + "ovf2", "unf2", + "ccmpa3", "ccmpb3", "cmpc3", "cmpd3", + "cmpe3", "cmpf3", "adtrga3", "adtrgb3", + "ovf3", "unf3", + "ccmpa4", "ccmpb4", "cmpc4", "cmpd4", + "cmpe4", "cmpf4", "adtrga4", "adtrgb4", + "ovf4", "unf4", + "ccmpa5", "ccmpb5", "cmpc5", "cmpd5", + "cmpe5", "cmpf5", "adtrga5", "adtrgb5", + "ovf5", "unf5", + "ccmpa6", "ccmpb6", "cmpc6", "cmpd6", + "cmpe6", "cmpf6", "adtrga6", "adtrgb6", + "ovf6", "unf6", + "ccmpa7", "ccmpb7", "cmpc7", "cmpd7", + "cmpe7", "cmpf7", "adtrga7", "adtrgb7", + "ovf7", "unf7"; + clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_GPT_RST_C>; + #pwm-cells = <3>; + }; diff --git a/Documentation/devicetree/bindings/pwm/via,vt8500-pwm.yaml b/Documentation/devicetree/bindings/pwm/via,vt8500-pwm.yaml new file mode 100644 index 0000000000000..d9146ad715ba7 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/via,vt8500-pwm.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/via,vt8500-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: VIA/Wondermedia VT8500/WM8xxx series SoC PWM controller + +maintainers: + - Alexey Charkov + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + items: + - const: via,vt8500-pwm + + reg: + maxItems: 1 + + '#pwm-cells': + const: 3 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + pwm1: pwm@d8220000 { + compatible = "via,vt8500-pwm"; + reg = <0xd8220000 0x1000>; + #pwm-cells = <3>; + clocks = <&clkpwm>; + }; diff --git a/Documentation/devicetree/bindings/pwm/vt8500-pwm.txt b/Documentation/devicetree/bindings/pwm/vt8500-pwm.txt deleted file mode 100644 index 4fba93ce1985a..0000000000000 --- a/Documentation/devicetree/bindings/pwm/vt8500-pwm.txt +++ /dev/null @@ -1,18 +0,0 @@ -VIA/Wondermedia VT8500/WM8xxx series SoC PWM controller - -Required properties: -- compatible: should be "via,vt8500-pwm" -- reg: physical base address and length of the controller's registers -- #pwm-cells: should be 3. See pwm.yaml in this directory for a description of - the cells format. The only third cell flag supported by this binding is - PWM_POLARITY_INVERTED. -- clocks: phandle to the PWM source clock - -Example: - -pwm1: pwm@d8220000 { - #pwm-cells = <3>; - compatible = "via,vt8500-pwm"; - reg = <0xd8220000 0x1000>; - clocks = <&clkpwm>; -}; diff --git a/Documentation/devicetree/bindings/regulator/adi,adp5055-regulator.yaml b/Documentation/devicetree/bindings/regulator/adi,adp5055-regulator.yaml new file mode 100644 index 0000000000000..9c4ead4c9fd19 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/adi,adp5055-regulator.yaml @@ -0,0 +1,157 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/adi,adp5055-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices ADP5055 Triple Buck Regulator + +maintainers: + - Alexis Czezar Torreno + +description: | + The ADP5055 combines three high performance buck regulator. The device enables + direct connection to high input voltages up to 18 V with no preregulators. + https://www.analog.com/media/en/technical-documentation/data-sheets/adp5055.pdf + +properties: + compatible: + enum: + - adi,adp5055 + + reg: + enum: + - 0x70 + - 0x71 + + adi,tset-us: + description: + Setting time used by the device. This is changed via soldering specific + resistor values on the CFG2 pin. + enum: [2600, 20800] + default: 2600 + + adi,ocp-blanking: + description: + If present, overcurrent protection (OCP) blanking for all regulator is on. + type: boolean + + adi,delay-power-good: + description: + Configures delay timer of the power good (PWRGD) pin. Delay is based on + Tset which can be 2.6 ms or 20.8 ms. + type: boolean + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + '^buck[0-2]$': + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + properties: + enable-gpios: + maxItems: 1 + description: + GPIO specifier to enable the GPIO control for each regulator. The + driver supports two modes of enable, hardware only (GPIOs) or software + only (Registers). Pure hardware enabling requires each regulator to + contain this property. If at least one regulator does not have this, + the driver automatically switches to software only mode. + + adi,dvs-limit-upper-microvolt: + description: + Configure the allowable upper side limit of the voltage output of each + regulator in microvolt. Relative to the default Vref trimming value. + Vref = 600 mV. Voltages are in 12 mV steps, value is autoadjusted. + Vout_high = Vref_trim + dvs-limit-upper. + minimum: 12000 + maximum: 192000 + default: 192000 + + adi,dvs-limit-lower-microvolt: + description: + Configure the allowable lower side limit of the voltage output of each + regulator in microvolt. Relative to the default Vref trimming value. + Vref = 600 mV. Voltages are in 12 mV steps, value is autoadjusted. + Vout_low = Vref_trim + dvs-limit-lower. + minimum: -190500 + maximum: -10500 + default: -190500 + + adi,fast-transient: + description: + Configures the fast transient sensitivity for each regulator. + "none" - No fast transient. + "3G_1.5%" - 1.5% window with 3*350uA/V + "5G_1.5%" - 1.5% window with 5*350uA/V + "5G_2.5%" - 2.5% window with 5*350uA/V + enum: [none, 3G_1.5%, 5G_1.5%, 5G_2.5%] + default: 5G_2.5% + + adi,mask-power-good: + description: + If present, masks individual regulators PWRGD signal to the external + PWRGD hardware pin. + type: boolean + + required: + - regulator-name + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + regulator@70 { + compatible = "adi,adp5055"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + adi,tset-us = <2600>; + adi,ocp-blanking; + adi,delay-power-good; + + buck0 { + regulator-name = "buck0"; + enable-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + adi,dvs-limit-upper-microvolt = <192000>; + adi,dvs-limit-lower-microvolt = <(-190500)>; + adi,fast-transient = "5G_2.5%"; + adi,mask-power-good; + }; + + buck1 { + regulator-name = "buck1"; + enable-gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; + adi,dvs-limit-upper-microvolt = <192000>; + adi,dvs-limit-lower-microvolt = <(-190500)>; + adi,fast-transient = "5G_2.5%"; + adi,mask-power-good; + }; + + buck2 { + regulator-name = "buck2"; + enable-gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; + adi,dvs-limit-upper-microvolt = <192000>; + adi,dvs-limit-lower-microvolt = <(-190500)>; + adi,fast-transient = "5G_2.5%"; + adi,mask-power-good; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/regulator/mediatek,mt6357-regulator.yaml b/Documentation/devicetree/bindings/regulator/mediatek,mt6357-regulator.yaml index 6327bb2f6ee08..698266c09e253 100644 --- a/Documentation/devicetree/bindings/regulator/mediatek,mt6357-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/mediatek,mt6357-regulator.yaml @@ -33,7 +33,7 @@ patternProperties: "^ldo-v(camio18|aud28|aux18|io18|io28|rf12|rf18|cn18|cn28|fe28)$": type: object - $ref: fixed-regulator.yaml# + $ref: regulator.yaml# unevaluatedProperties: false description: Properties for single fixed LDO regulator. @@ -112,7 +112,6 @@ examples: regulator-enable-ramp-delay = <220>; }; mt6357_vfe28_reg: ldo-vfe28 { - compatible = "regulator-fixed"; regulator-name = "vfe28"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; @@ -125,14 +124,12 @@ examples: regulator-enable-ramp-delay = <110>; }; mt6357_vrf18_reg: ldo-vrf18 { - compatible = "regulator-fixed"; regulator-name = "vrf18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-enable-ramp-delay = <110>; }; mt6357_vrf12_reg: ldo-vrf12 { - compatible = "regulator-fixed"; regulator-name = "vrf12"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; @@ -157,14 +154,12 @@ examples: regulator-enable-ramp-delay = <264>; }; mt6357_vcn28_reg: ldo-vcn28 { - compatible = "regulator-fixed"; regulator-name = "vcn28"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-enable-ramp-delay = <264>; }; mt6357_vcn18_reg: ldo-vcn18 { - compatible = "regulator-fixed"; regulator-name = "vcn18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -183,7 +178,6 @@ examples: regulator-enable-ramp-delay = <264>; }; mt6357_vcamio_reg: ldo-vcamio18 { - compatible = "regulator-fixed"; regulator-name = "vcamio"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -212,28 +206,24 @@ examples: regulator-always-on; }; mt6357_vaux18_reg: ldo-vaux18 { - compatible = "regulator-fixed"; regulator-name = "vaux18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-enable-ramp-delay = <264>; }; mt6357_vaud28_reg: ldo-vaud28 { - compatible = "regulator-fixed"; regulator-name = "vaud28"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-enable-ramp-delay = <264>; }; mt6357_vio28_reg: ldo-vio28 { - compatible = "regulator-fixed"; regulator-name = "vio28"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-enable-ramp-delay = <264>; }; mt6357_vio18_reg: ldo-vio18 { - compatible = "regulator-fixed"; regulator-name = "vio18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; diff --git a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml index 695ef38a7bb34..150e95c0d9bed 100644 --- a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml +++ b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml @@ -12,14 +12,20 @@ maintainers: properties: compatible: - enum: - - amlogic,meson8b-reset # Reset Controller on Meson8b and compatible SoCs - - amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible SoCs - - amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs - - amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs - - amlogic,meson-s4-reset # Reset Controller on S4 and compatible SoCs - - amlogic,c3-reset # Reset Controller on C3 and compatible SoCs - - amlogic,t7-reset + oneOf: + - enum: + - amlogic,meson8b-reset # Reset Controller on Meson8b and compatible SoCs + - amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible SoCs + - amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs + - amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs + - amlogic,meson-s4-reset # Reset Controller on S4 and compatible SoCs + - amlogic,c3-reset # Reset Controller on C3 and compatible SoCs + - amlogic,t7-reset + - items: + - enum: + - amlogic,a4-reset + - amlogic,a5-reset + - const: amlogic,meson-s4-reset reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml index c3b33bbc73196..84c4801df8d9a 100644 --- a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml +++ b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml @@ -23,6 +23,9 @@ properties: - atmel,sama5d3-rstc - microchip,sam9x60-rstc - microchip,sama7g5-rstc + - items: + - const: microchip,sama7d65-rstc + - const: microchip,sama7g5-rstc - items: - const: atmel,sama5d3-rstc - const: atmel,at91sam9g45-rstc diff --git a/Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml b/Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml new file mode 100644 index 0000000000000..c79f61c2373bc --- /dev/null +++ b/Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/renesas,rzv2h-usb2phy-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/V2H(P) USB2PHY Port reset Control + +maintainers: + - Lad Prabhakar + +description: + The RZ/V2H(P) USB2PHY Control mainly controls Port reset and power down of the + USB2.0 PHY. + +properties: + compatible: + const: renesas,r9a09g057-usb2phy-reset # RZ/V2H(P) + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + + '#reset-cells': + const: 0 + +required: + - compatible + - reg + - clocks + - resets + - power-domains + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + + reset-controller@15830000 { + compatible = "renesas,r9a09g057-usb2phy-reset"; + reg = <0x15830000 0x10000>; + clocks = <&cpg CPG_MOD 0xb6>; + resets = <&cpg 0xaf>; + power-domains = <&cpg>; + #reset-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml index 76e1931f09082..1d1b84575960c 100644 --- a/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml +++ b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml @@ -11,7 +11,12 @@ maintainers: properties: compatible: - const: sophgo,sg2042-reset + oneOf: + - items: + - enum: + - sophgo,sg2044-reset + - const: sophgo,sg2042-reset + - const: sophgo,sg2042-reset reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml b/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml new file mode 100644 index 0000000000000..f2e91d0add7a6 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/thead,th1520-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-HEAD TH1520 SoC Reset Controller + +description: + The T-HEAD TH1520 reset controller is a hardware block that asserts/deasserts + resets for SoC subsystems. + +maintainers: + - Michal Wilczynski + +properties: + compatible: + enum: + - thead,th1520-reset + + reg: + maxItems: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - "#reset-cells" + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + rst: reset-controller@ffef528000 { + compatible = "thead,th1520-reset"; + reg = <0xff 0xef528000 0x0 0x1000>; + #reset-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/riscv/sophgo.yaml index a14cb10ff3f07..b4c4d7a7d7add 100644 --- a/Documentation/devicetree/bindings/riscv/sophgo.yaml +++ b/Documentation/devicetree/bindings/riscv/sophgo.yaml @@ -35,6 +35,10 @@ properties: - enum: - milkv,pioneer - const: sophgo,sg2042 + - items: + - enum: + - sophgo,srd3-10 + - const: sophgo,sg2044 additionalProperties: true diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml index 1aa3480d8d818..1ee0aed5057d3 100644 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -17,9 +17,7 @@ allOf: properties: compatible: items: - - enum: - - renesas,r9a06g032-uart - - renesas,r9a06g033-uart + - const: renesas,r9a06g032-uart - const: renesas,rzn1-uart - const: snps,dw-apb-uart then: @@ -45,15 +43,11 @@ properties: compatible: oneOf: - items: - - enum: - - renesas,r9a06g032-uart - - renesas,r9a06g033-uart + - const: renesas,r9a06g032-uart - const: renesas,rzn1-uart - const: snps,dw-apb-uart - items: - - enum: - - renesas,r9a06g032-uart - - renesas,r9a06g033-uart + - const: renesas,r9a06g032-uart - const: renesas,rzn1-uart - items: - enum: diff --git a/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml b/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml index 77c2811530103..39d4637c2d088 100644 --- a/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml +++ b/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml @@ -22,6 +22,8 @@ properties: - amlogic,meson-axg-clk-measure - amlogic,meson-g12a-clk-measure - amlogic,meson-sm1-clk-measure + - amlogic,c3-clk-measure + - amlogic,s4-clk-measure reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,qman-fqd.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,qman-fqd.yaml index de0b4ae740ff2..a975bce599750 100644 --- a/Documentation/devicetree/bindings/soc/fsl/fsl,qman-fqd.yaml +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,qman-fqd.yaml @@ -50,7 +50,7 @@ required: - compatible allOf: - - $ref: reserved-memory.yaml + - $ref: /schemas/reserved-memory/reserved-memory.yaml unevaluatedProperties: false @@ -61,7 +61,7 @@ examples: #size-cells = <2>; qman-fqd { - compatible = "shared-dma-pool"; + compatible = "fsl,qman-fqd"; size = <0 0x400000>; alignment = <0 0x400000>; no-map; diff --git a/Documentation/devicetree/bindings/soc/google/google,gs101-pmu-intr-gen.yaml b/Documentation/devicetree/bindings/soc/google/google,gs101-pmu-intr-gen.yaml new file mode 100644 index 0000000000000..2be022ca6a7d0 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/google/google,gs101-pmu-intr-gen.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/google/google,gs101-pmu-intr-gen.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google Power Management Unit (PMU) Interrupt Generation + +description: | + PMU interrupt generator for handshaking between PMU through interrupts. + +maintainers: + - Peter Griffin + +properties: + compatible: + items: + - const: google,gs101-pmu-intr-gen + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pmu_intr_gen: syscon@17470000 { + compatible = "google,gs101-pmu-intr-gen", "syscon"; + reg = <0x17470000 0x10000>; + }; diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8183-dvfsrc.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8183-dvfsrc.yaml index 1ad5b61b249f2..4c96d49179676 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8183-dvfsrc.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8183-dvfsrc.yaml @@ -23,6 +23,7 @@ properties: compatible: oneOf: - enum: + - mediatek,mt6893-dvfsrc - mediatek,mt8183-dvfsrc - mediatek,mt8195-dvfsrc - items: diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,rpm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,rpm.yaml index b00be9e01206d..3e8d99cb4dc36 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,rpm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,rpm.yaml @@ -36,6 +36,13 @@ properties: - const: err - const: wakeup + clocks: + maxItems: 1 + + clock-names: + items: + - const: ram + qcom,ipc: $ref: /schemas/types.yaml#/definitions/phandle-array items: @@ -46,6 +53,14 @@ properties: description: Three entries specifying the outgoing ipc bit used for signaling the RPM. + clock-controller: + type: object + additionalProperties: true + properties: + compatible: + contains: + const: qcom,rpmcc + patternProperties: "^regulators(-[01])?$": type: object diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml index af632d0e0355c..036562eb5140c 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml @@ -44,7 +44,13 @@ description: | properties: compatible: - const: qcom,rpmh-rsc + oneOf: + - items: + - enum: + - qcom,sc7180-rpmh-apps-rsc + - qcom,sdm845-rpmh-apps-rsc + - const: qcom,rpmh-rsc + - const: qcom,rpmh-rsc interrupts: minItems: 1 @@ -124,7 +130,21 @@ required: - qcom,tcs-offset - reg - reg-names - - power-domains + +allOf: + # Some platforms may lack a OSI-mode PSCI implementation, which implies the + # system power domain can't provide feedback about entering power collapse + - if: + not: + properties: + compatible: + contains: + enum: + - qcom,sc7180-rpmh-apps-rsc + - qcom,sdm845-rpmh-apps-rsc + then: + required: + - power-domains additionalProperties: false diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml index ca4bce8172738..c2f1f5946cfaa 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml @@ -73,9 +73,10 @@ examples: #size-cells = <0>; cpu@0 { - compatible = "qcom,kryo"; + compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "qcom,kpss-acc-v2"; + qcom,acc = <&acc0>; qcom,saw = <&saw0>; reg = <0x0>; operating-points-v2 = <&cpu_opp_table>; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.yaml index fd6db0ca98eb7..4fcae6bedfffa 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.yaml @@ -54,7 +54,7 @@ properties: - compatible wifi: - additionalProperties: false + unevaluatedProperties: false type: object properties: compatible: @@ -88,6 +88,9 @@ properties: - qcom,smem-states - qcom,smem-state-names + allOf: + - $ref: /schemas/net/wireless/wireless-controller.yaml# + required: - compatible - qcom,mmio diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml index e0f7503a9f35b..c41dcaea568ac 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml @@ -25,6 +25,7 @@ properties: items: - enum: - renesas,r9a09g047-sys # RZ/G3E + - renesas,r9a09g056-sys # RZ/V2N - renesas,r9a09g057-sys # RZ/V2H reg: diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml index 51a4c48eea6d7..5e6e6e6208dc5 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -375,6 +375,13 @@ properties: - renesas,r8a779g3 # ES3.x - const: renesas,r8a779g0 + - description: R-Car V4H (R8A779G3) + items: + - enum: + - retronix,sparrow-hawk # Sparrow Hawk board + - const: renesas,r8a779g3 # ES3.x + - const: renesas,r8a779g0 + - description: R-Car V4M (R8A779H0) items: - enum: @@ -551,6 +558,21 @@ properties: - renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA) - const: renesas,r9a09g047 + - description: RZ/V2N (R9A09G056) + items: + - enum: + - renesas,rzv2n-evk # RZ/V2N EVK (RTK0EF0186C03000BJ) + - enum: + - renesas,r9a09g056n41 # RZ/V2N + - renesas,r9a09g056n42 # RZ/V2N with Mali-G31 support + - renesas,r9a09g056n43 # RZ/V2N with Mali-C55 support + - renesas,r9a09g056n44 # RZ/V2N with Mali-G31 + Mali-C55 support + - renesas,r9a09g056n45 # RZ/V2N with cryptographic extension support + - renesas,r9a09g056n46 # RZ/V2N with Mali-G31 + cryptographic extension support + - renesas,r9a09g056n47 # RZ/V2N with Mali-C55 + cryptographic extension support + - renesas,r9a09g056n48 # RZ/V2N with Mali-G31 + Mali-C55 + cryptographic extension support + - const: renesas,r9a09g056 + - description: RZ/V2H(P) (R9A09G057) items: - enum: @@ -570,6 +592,16 @@ properties: - const: renesas,r9a09g057h48 - const: renesas,r9a09g057 + - description: RZ/T2H (R9A09G077) + items: + - enum: + - renesas,rzt2h-evk # RZ/T2H Evaluation Board + - enum: + - renesas,r9a09g077m04 # RZ/T2H with Single Cortex-A55 + Dual Cortex-R52 - no security + - renesas,r9a09g077m24 # RZ/T2H with Dual Cortex-A55 + Dual Cortex-R52 - no security + - renesas,r9a09g077m44 # RZ/T2H with Quad Cortex-A55 + Dual Cortex-R52 - no security + - const: renesas,r9a09g077 + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml index 2f61c1b95fea3..8cbf5b6772ddf 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -18,6 +18,12 @@ properties: - rockchip,rk3528-ioc-grf - rockchip,rk3528-vo-grf - rockchip,rk3528-vpu-grf + - rockchip,rk3562-ioc-grf + - rockchip,rk3562-peri-grf + - rockchip,rk3562-pipephy-grf + - rockchip,rk3562-pmu-grf + - rockchip,rk3562-sys-grf + - rockchip,rk3562-usbphy-grf - rockchip,rk3566-pipe-grf - rockchip,rk3568-pcie3-phy-grf - rockchip,rk3568-pipe-grf @@ -82,6 +88,7 @@ properties: - rockchip,rk3368-pmugrf - rockchip,rk3399-grf - rockchip,rk3399-pmugrf + - rockchip,rk3562-pmu-grf - rockchip,rk3568-grf - rockchip,rk3568-pmugrf - rockchip,rk3576-ioc-grf diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml index 204da6fe458d2..3109df43d5028 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml @@ -129,6 +129,11 @@ properties: description: Node for reboot method + google,pmu-intr-gen-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to PMU interrupt generation interface. + required: - compatible - reg @@ -189,6 +194,16 @@ allOf: properties: dp-phy: false + - if: + properties: + compatible: + contains: + enum: + - google,gs101-pmu + then: + required: + - google,pmu-intr-gen-syscon + examples: - | #include diff --git a/Documentation/devicetree/bindings/soc/sophgo/sophgo,cv1800b-rtc.yaml b/Documentation/devicetree/bindings/soc/sophgo/sophgo,cv1800b-rtc.yaml new file mode 100644 index 0000000000000..5cf186c396c99 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/sophgo/sophgo,cv1800b-rtc.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sophgo/sophgo,cv1800b-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Real Time Clock of the Sophgo CV1800 SoC + +description: + The RTC (Real Time Clock) is an independently powered module in the chip. It + contains a 32KHz oscillator and a Power-On-Reset (POR) sub-module, which can + be used for time display and scheduled alarm produce. In addition, the + hardware state machine provides triggering and timing control for chip + power-on, power-off and reset. + + Furthermore, the 8051 subsystem is located within RTCSYS and is independently + powered. System software can use the 8051 to manage wake conditions and wake + the system while the system is asleep, and communicate with external devices + through peripheral controllers. + + Technical Reference Manual available at + https://github.com/sophgo/sophgo-doc/tree/main/SG200X/TRM + +maintainers: + - sophgo@lists.linux.dev + +allOf: + - $ref: /schemas/rtc/rtc.yaml# + +properties: + compatible: + items: + - const: sophgo,cv1800b-rtc + - const: syscon + + reg: + maxItems: 1 + + interrupts: + items: + - description: RTC Alarm + - description: RTC Longpress + - description: VBAT DET + + interrupt-names: + items: + - const: alarm + - const: longpress + - const: vbat + + clocks: + items: + - description: RTC clock source + - description: DW8051 MCU clock source + + clock-names: + items: + - const: rtc + - const: mcu + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + + rtc@5025000 { + compatible = "sophgo,cv1800b-rtc", "syscon"; + reg = <0x5025000 0x2000>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, + <18 IRQ_TYPE_LEVEL_HIGH>, + <19 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "alarm", "longpress", "vbat"; + clocks = <&clk CLK_RTC_25M>, + <&clk CLK_SRC_RTC_SYS_0>; + clock-names = "rtc", "mcu"; + }; diff --git a/Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2044-top-syscon.yaml b/Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2044-top-syscon.yaml new file mode 100644 index 0000000000000..a82cc3cae576d --- /dev/null +++ b/Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2044-top-syscon.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/sophgo/sophgo,sg2044-top-syscon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2044 SoC TOP system controller + +maintainers: + - Inochi Amaoto + +description: + The Sophgo SG2044 TOP system controller is a hardware block grouping + multiple small functions, such as clocks and some other internal + function. + +properties: + compatible: + items: + - const: sophgo,sg2044-top-syscon + - const: syscon + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + '#clock-cells': + const: 1 + description: + See for valid clock. + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + syscon@50000000 { + compatible = "sophgo,sg2044-top-syscon", "syscon"; + reg = <0x50000000 0x1000>; + #clock-cells = <1>; + clocks = <&osc>; + }; diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml new file mode 100644 index 0000000000000..30aaf49da03d3 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/spacemit/spacemit,k1-syscon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K1 SoC System Controller + +maintainers: + - Haylen Chu + +description: + System controllers found on SpacemiT K1 SoC, which are capable of + clock, reset and power-management functions. + +properties: + compatible: + enum: + - spacemit,k1-syscon-apbc + - spacemit,k1-syscon-apmu + - spacemit,k1-syscon-mpmu + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + + clock-names: + items: + - const: osc + - const: vctcxo_1m + - const: vctcxo_3m + - const: vctcxo_24m + + "#clock-cells": + const: 1 + description: + See for valid indices. + + "#power-domain-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + - "#reset-cells" + +allOf: + - if: + properties: + compatible: + contains: + const: spacemit,k1-syscon-apbc + then: + properties: + "#power-domain-cells": false + else: + required: + - "#power-domain-cells" + +additionalProperties: false + +examples: + - | + system-controller@d4050000 { + compatible = "spacemit,k1-syscon-mpmu"; + reg = <0xd4050000 0x209c>; + clocks = <&osc>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; + clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m"; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml index 378e9cc5fac2a..f3bd0be3b279f 100644 --- a/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml +++ b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml @@ -26,6 +26,7 @@ properties: compatible: items: - enum: + - ti,am654-system-controller - ti,j7200-system-controller - ti,j721e-system-controller - ti,j721s2-system-controller @@ -68,6 +69,23 @@ patternProperties: description: The node corresponding to SoC chip identification. + "^pcie-ctrl@[0-9a-f]+$": + type: object + description: + The node corresponding to PCIe control register. + + "^clock@[0-9a-f]+$": + type: object + $ref: /schemas/soc/ti/ti,am654-serdes-ctrl.yaml# + description: + This is the Serdes Control region. + + "^dss-oldi-io-ctrl@[0-9a-f]+$": + type: object + $ref: /schemas/mfd/syscon.yaml# + description: + This is the DSS OLDI CTRL region. + required: - compatible - reg @@ -110,5 +128,10 @@ examples: compatible = "ti,am654-chipid"; reg = <0x14 0x4>; }; + + pcie0_ctrl: pcie-ctrl@4070 { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x4070 0x4>; + }; }; ... diff --git a/Documentation/devicetree/bindings/sound/audio-graph-card2.yaml b/Documentation/devicetree/bindings/sound/audio-graph-card2.yaml index 94588353f852a..40eb1d7d6cf12 100644 --- a/Documentation/devicetree/bindings/sound/audio-graph-card2.yaml +++ b/Documentation/devicetree/bindings/sound/audio-graph-card2.yaml @@ -18,11 +18,7 @@ properties: label: maxItems: 1 routing: - description: | - A list of the connections between audio components. - Each entry is a pair of strings, the first being the - connection's sink, the second being the connection's source. - $ref: /schemas/types.yaml#/definitions/non-unique-string-array + $ref: audio-graph.yaml#/properties/routing aux-devs: description: | List of phandles pointing to auxiliary devices, such @@ -39,6 +35,8 @@ properties: description: Codec to Codec node hp-det-gpios: $ref: audio-graph.yaml#/properties/hp-det-gpios + mic-det-gpios: + $ref: audio-graph.yaml#/properties/mic-det-gpios widgets: $ref: audio-graph.yaml#/properties/widgets diff --git a/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml b/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml new file mode 100644 index 0000000000000..bf087b57aaf60 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml @@ -0,0 +1,195 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/cirrus,cs48l32.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic CS48L32 audio DSP. + +maintainers: + - patches@opensource.cirrus.com + +description: | + The CS48L32 is a high-performance low-power audio DSP for smartphones and + other portable audio devices. The CS48L32 combines a programmable Halo Core + DSP with a variety of power-efficient fixed-function audio processors. + + See also the binding headers: + + include/dt-bindings/sound/cs48l32.yaml + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + - $ref: dai-common.yaml# + +properties: + compatible: + enum: + - cirrus,cs48l32 + + reg: + description: SPI chip-select number. + maxItems: 1 + + spi-max-frequency: + maximum: 25000000 + + vdd-a-supply: + description: Regulator supplying VDD_A + + vdd-d-supply: + description: Regulator supplying VDD_D + + vdd-io-supply: + description: Regulator supplying VDD_IO + + vdd-cp-supply: + description: Regulator supplying VDD_CP + + reset-gpios: + description: + One entry specifying the GPIO controlling /RESET. Although optional, + it is strongly recommended to use a hardware reset. + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: The clock supplied on MCLK1 + + clock-names: + const: mclk1 + + '#sound-dai-cells': + const: 1 + + cirrus,in-type: + description: | + A list of input type settings for each ADC input. + Inputs are one of these types: + CS48L32_IN_TYPE_DIFF : analog differential (default) + CS48L32_IN_TYPE_SE : analog single-ended + + The type of the left (L) and right (R) channel on each input is + independently configured, as are the two groups of pins muxable to + the input (referred to in the datasheet as "1" and "2"). + + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: + IN1L_1 analog input type. One of the CS48L32_IN_TYPE_xxx. + minimum: 0 + maximum: 1 + default: 0 + - description: + IN1R_1 analog input type. One of the CS48L32_IN_TYPE_xxx. + minimum: 0 + maximum: 1 + default: 0 + - description: + IN1L_2 analog input type. One of the CS48L32_IN_TYPE_xxx. + minimum: 0 + maximum: 1 + default: 0 + - description: + IN1R_2 analog input type. One of the CS48L32_IN_TYPE_xxx. + minimum: 0 + maximum: 1 + default: 0 + + cirrus,pdm-sup: + description: | + Indicate which MICBIAS output supplies bias to the microphone. + There is one cell per input (IN1, IN2, ...). + + One of the CS48L32_MICBIAS_xxx values. + CS48L32_PDM_SUP_VOUT_MIC : mic biased from VOUT_MIC + CS48L32_PDM_SUP_MICBIAS1 : mic biased from MICBIAS1 + + Also see the INn_PDM_SUP field in the datasheet. + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: IN1 PDM supply source + minimum: 0 + maximum: 1 + default: 0 + - description: IN2 PDM supply source + minimum: 0 + maximum: 1 + default: 0 + +required: + - compatible + - reg + - vdd-a-supply + - vdd-d-supply + - vdd-io-supply + - vdd-cp-supply + +additionalProperties: false + +examples: + - | + #include + + spi@e0006000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0xe0006000 0x1000>; + + codec@1 { + compatible = "cirrus,cs48l32"; + + reg = <0x1>; + spi-max-frequency = <2500000>; + + vdd-a-supply = <®ulator_1v8>; + vdd-d-supply = <®ulator_1v2>; + vdd-io-supply = <®ulator_1v8>; + vdd-cp-supply = <®ulator_1v8>; + + reset-gpios = <&gpio 0 0>; + + clocks = <&clks 0>; + clock-names = "mclk1"; + + interrupt-parent = <&gpio0>; + interrupts = <56 8>; + + #sound-dai-cells = <1>; + + cirrus,in-type = < + CS48L32_IN_TYPE_DIFF CS48L32_IN_TYPE_DIFF + CS48L32_IN_TYPE_SE CS48L32_IN_TYPE_SE + >; + + cirrus,pdm-sup = < + CS48L32_PDM_SUP_MICBIAS1 CS48L32_PDM_SUP_MICBIAS1 + >; + }; + }; + +# +# Minimal config +# + - | + #include + + spi@e0006000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0xe0006000 0x1000>; + + codec@1 { + compatible = "cirrus,cs48l32"; + + reg = <0x1>; + + vdd-a-supply = <®ulator_1v8>; + vdd-d-supply = <®ulator_1v2>; + vdd-io-supply = <®ulator_1v8>; + vdd-cp-supply = <®ulator_1v8>; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/everest,es8375.yaml b/Documentation/devicetree/bindings/sound/everest,es8375.yaml new file mode 100644 index 0000000000000..4a3d671c66b19 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/everest,es8375.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/everest,es8375.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Everest ES8375 audio CODEC + +maintainers: + - Michael Zhang + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + const: everest,es8375 + + reg: + maxItems: 1 + + clocks: + items: + - description: clock for master clock (MCLK) + + clock-names: + items: + - const: mclk + + vdda-supply: + description: + Analogue power supply. + + vddd-supply: + description: + Interface power supply. + + everest,mclk-src: + $ref: /schemas/types.yaml#/definitions/uint8 + description: | + Represents the MCLK/SCLK pair pins used as the internal clock. + 0 represents selecting MCLK. + 1 represents selecting SCLK. + enum: [0, 1] + default: 0 + + "#sound-dai-cells": + const: 0 + +required: + - compatible + - reg + - "#sound-dai-cells" + - vdda-supply + - vddd-supply + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + es8375: codec@18 { + compatible = "everest,es8375"; + reg = <0x18>; + vdda-supply = <&vdd3v3>; + vddd-supply = <&vdd3v3>; + #sound-dai-cells = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/everest,es8389.yaml b/Documentation/devicetree/bindings/sound/everest,es8389.yaml new file mode 100644 index 0000000000000..a673df485ab30 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/everest,es8389.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/everest,es8389.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Everest ES8389 audio CODEC + +maintainers: + - Michael Zhang + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + const: everest,es8389 + + reg: + maxItems: 1 + + clocks: + items: + - description: clock for master clock (MCLK) + + clock-names: + items: + - const: mclk + + "#sound-dai-cells": + const: 0 + +required: + - compatible + - reg + - "#sound-dai-cells" + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + es8389: codec@10 { + compatible = "everest,es8389"; + reg = <0x10>; + #sound-dai-cells = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/fsl,mqs.yaml b/Documentation/devicetree/bindings/sound/fsl,mqs.yaml index 8c22e8348b14d..1415247c92c8f 100644 --- a/Documentation/devicetree/bindings/sound/fsl,mqs.yaml +++ b/Documentation/devicetree/bindings/sound/fsl,mqs.yaml @@ -28,6 +28,9 @@ properties: - fsl,imx95-aonmix-mqs - fsl,imx95-netcmix-mqs + "#sound-dai-cells": + const: 0 + clocks: minItems: 1 maxItems: 2 @@ -49,12 +52,17 @@ properties: resets: maxItems: 1 + port: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + required: - compatible - clocks - clock-names allOf: + - $ref: dai-common.yaml# - if: properties: compatible: @@ -86,7 +94,7 @@ allOf: required: - gpr -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/sound/loongson,ls1b-ac97.yaml b/Documentation/devicetree/bindings/sound/loongson,ls1b-ac97.yaml new file mode 100644 index 0000000000000..1c6a2771f9423 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/loongson,ls1b-ac97.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/loongson,ls1b-ac97.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson-1 AC97 Controller + +maintainers: + - Keguang Zhang + +description: + The Loongson-1 AC97 controller supports 2-channel stereo output and input. + It is paired with the DMA engine to handle playback and capture functions. + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + oneOf: + - const: loongson,ls1b-ac97 + - items: + - enum: + - loongson,ls1a-ac97 + - loongson,ls1c-ac97 + - const: loongson,ls1b-ac97 + + reg: + maxItems: 3 + + reg-names: + items: + - const: ac97 + - const: audio-tx + - const: audio-rx + + dmas: + maxItems: 2 + + dma-names: + items: + - const: tx + - const: rx + + '#sound-dai-cells': + const: 0 + +required: + - compatible + - reg + - reg-names + - dmas + - dma-names + - '#sound-dai-cells' + +unevaluatedProperties: false + +examples: + - | + audio-controller@1fe74000 { + compatible = "loongson,ls1b-ac97"; + reg = <0x1fe74000 0x60>, <0x1fe72420 0x4>, <0x1fe74c4c 0x4>; + reg-names = "ac97", "audio-tx", "audio-rx"; + dmas = <&dma 1>, <&dma 2>; + dma-names = "tx", "rx"; + #sound-dai-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/sound/maxim,max98925.yaml b/Documentation/devicetree/bindings/sound/maxim,max98925.yaml index 32fd86204a7ae..121e8d2d44da0 100644 --- a/Documentation/devicetree/bindings/sound/maxim,max98925.yaml +++ b/Documentation/devicetree/bindings/sound/maxim,max98925.yaml @@ -77,11 +77,11 @@ additionalProperties: false examples: - | + #include i2c { #address-cells = <1>; #size-cells = <0>; - #include audio-codec@3a { compatible = "maxim,max98927"; reg = <0x3a>; diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt8188-mt6359.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt8188-mt6359.yaml index 76d5a437dc8f4..7ba2ea2dfa0b1 100644 --- a/Documentation/devicetree/bindings/sound/mediatek,mt8188-mt6359.yaml +++ b/Documentation/devicetree/bindings/sound/mediatek,mt8188-mt6359.yaml @@ -96,10 +96,9 @@ patternProperties: mediatek,clk-provider: $ref: /schemas/types.yaml#/definitions/string description: Indicates dai-link clock master. - items: - enum: - - cpu - - codec + enum: + - cpu + - codec additionalProperties: false diff --git a/Documentation/devicetree/bindings/sound/mt8186-mt6366-da7219-max98357.yaml b/Documentation/devicetree/bindings/sound/mt8186-mt6366-da7219-max98357.yaml index cbc641ecbe94a..037f21443ad14 100644 --- a/Documentation/devicetree/bindings/sound/mt8186-mt6366-da7219-max98357.yaml +++ b/Documentation/devicetree/bindings/sound/mt8186-mt6366-da7219-max98357.yaml @@ -124,10 +124,9 @@ patternProperties: mediatek,clk-provider: $ref: /schemas/types.yaml#/definitions/string description: Indicates dai-link clock master. - items: - enum: - - cpu - - codec + enum: + - cpu + - codec required: - link-name diff --git a/Documentation/devicetree/bindings/sound/mt8195-mt6359.yaml b/Documentation/devicetree/bindings/sound/mt8195-mt6359.yaml index 2af1d8ffbd8b5..356e1feee9620 100644 --- a/Documentation/devicetree/bindings/sound/mt8195-mt6359.yaml +++ b/Documentation/devicetree/bindings/sound/mt8195-mt6359.yaml @@ -21,6 +21,7 @@ properties: - mediatek,mt8195_mt6359_rt1019_rt5682 - mediatek,mt8195_mt6359_rt1011_rt5682 - mediatek,mt8195_mt6359_max98390_rt5682 + - mediatek,mt8195_mt6359 model: $ref: /schemas/types.yaml#/definitions/string @@ -44,6 +45,8 @@ properties: - Right Spk # Sources + - Headphone L + - Headphone R - Headset Mic - HPOL - HPOR @@ -88,6 +91,7 @@ patternProperties: link-name: description: Indicates dai-link name and PCM stream name enum: + - DL_SRC_BE - DPTX_BE - ETDM1_IN_BE - ETDM2_IN_BE diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-graph-card.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-graph-card.yaml index b4bee466d67a2..da89523ccf5f8 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-graph-card.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-graph-card.yaml @@ -23,6 +23,7 @@ properties: enum: - nvidia,tegra210-audio-graph-card - nvidia,tegra186-audio-graph-card + - nvidia,tegra264-audio-graph-card clocks: minItems: 2 diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra186-asrc.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra186-asrc.yaml index e15f387c4c298..66b56e71599b8 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra186-asrc.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra186-asrc.yaml @@ -31,7 +31,9 @@ properties: compatible: oneOf: - - const: nvidia,tegra186-asrc + - enum: + - nvidia,tegra186-asrc + - nvidia,tegra264-asrc - items: - enum: - nvidia,tegra234-asrc diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra186-dspk.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra186-dspk.yaml index e1362c77472bb..46ba167081ef0 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra186-dspk.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra186-dspk.yaml @@ -29,6 +29,7 @@ properties: - const: nvidia,tegra186-dspk - items: - enum: + - nvidia,tegra264-dspk - nvidia,tegra234-dspk - nvidia,tegra194-dspk - const: nvidia,tegra186-dspk diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-admaif.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-admaif.yaml index 15ab40aeab1e0..b32f33214ba60 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-admaif.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-admaif.yaml @@ -26,6 +26,7 @@ properties: - enum: - nvidia,tegra210-admaif - nvidia,tegra186-admaif + - nvidia,tegra264-admaif - items: - enum: - nvidia,tegra234-admaif @@ -39,6 +40,19 @@ properties: dma-names: true + interconnects: + items: + - description: APE read memory client + - description: APE write memory client + + interconnect-names: + items: + - const: dma-mem # read + - const: write + + iommus: + maxItems: 1 + ports: $ref: /schemas/graph.yaml#/properties/ports description: | @@ -74,6 +88,9 @@ then: Should be "tx1", "tx2" ... "tx10" for DMA Tx channel minItems: 1 maxItems: 20 + interconnects: false + interconnect-names: false + iommus: false else: properties: diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-adx.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-adx.yaml index e4c871797fa6c..19a80929f93e6 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-adx.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-adx.yaml @@ -27,7 +27,9 @@ properties: compatible: oneOf: - - const: nvidia,tegra210-adx + - enum: + - nvidia,tegra210-adx + - nvidia,tegra264-adx - items: - enum: - nvidia,tegra234-adx diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-ahub.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-ahub.yaml index c4abac81f2074..1c9f24d268190 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-ahub.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-ahub.yaml @@ -27,6 +27,7 @@ properties: - nvidia,tegra210-ahub - nvidia,tegra186-ahub - nvidia,tegra234-ahub + - nvidia,tegra264-ahub - items: - const: nvidia,tegra194-ahub - const: nvidia,tegra186-ahub diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-amx.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-amx.yaml index 021b72546ba4b..89712102cfdf6 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-amx.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-amx.yaml @@ -26,11 +26,13 @@ properties: compatible: oneOf: - - const: nvidia,tegra210-amx + - enum: + - nvidia,tegra210-amx + - nvidia,tegra194-amx + - nvidia,tegra264-amx - items: - const: nvidia,tegra186-amx - const: nvidia,tegra210-amx - - const: nvidia,tegra194-amx - items: - const: nvidia,tegra234-amx - const: nvidia,tegra194-amx diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-dmic.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-dmic.yaml index bff551c35da7a..bb8088878d4bc 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-dmic.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-dmic.yaml @@ -28,6 +28,7 @@ properties: - const: nvidia,tegra210-dmic - items: - enum: + - nvidia,tegra264-dmic - nvidia,tegra234-dmic - nvidia,tegra194-dmic - nvidia,tegra186-dmic diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-i2s.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-i2s.yaml index a82f11fb6c9a8..903e815af8fd5 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-i2s.yaml @@ -25,7 +25,9 @@ properties: compatible: oneOf: - - const: nvidia,tegra210-i2s + - enum: + - nvidia,tegra210-i2s + - nvidia,tegra264-i2s - items: - enum: - nvidia,tegra234-i2s diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-mbdrc.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-mbdrc.yaml index 5b9198602fc6a..4c121b9cde1e0 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-mbdrc.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-mbdrc.yaml @@ -23,6 +23,7 @@ properties: - const: nvidia,tegra210-mbdrc - items: - enum: + - nvidia,tegra264-mbdrc - nvidia,tegra234-mbdrc - nvidia,tegra194-mbdrc - nvidia,tegra186-mbdrc diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-mixer.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-mixer.yaml index 049898f02e85c..56b4c4fc123cc 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-mixer.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-mixer.yaml @@ -28,6 +28,7 @@ properties: - const: nvidia,tegra210-amixer - items: - enum: + - nvidia,tegra264-amixer - nvidia,tegra234-amixer - nvidia,tegra194-amixer - nvidia,tegra186-amixer diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-mvc.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-mvc.yaml index d0280d8aa3af8..bde4ac6319b19 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-mvc.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-mvc.yaml @@ -31,6 +31,7 @@ properties: - const: nvidia,tegra210-mvc - items: - enum: + - nvidia,tegra264-mvc - nvidia,tegra234-mvc - nvidia,tegra194-mvc - nvidia,tegra186-mvc diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-ope.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-ope.yaml index 9017fb6d575d9..756c3096a2d60 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-ope.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-ope.yaml @@ -25,6 +25,7 @@ properties: - const: nvidia,tegra210-ope - items: - enum: + - nvidia,tegra264-ope - nvidia,tegra234-ope - nvidia,tegra194-ope - nvidia,tegra186-ope diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-peq.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-peq.yaml index 1e373c49d639b..2f11a484dc2e5 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-peq.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-peq.yaml @@ -24,6 +24,7 @@ properties: - const: nvidia,tegra210-peq - items: - enum: + - nvidia,tegra264-peq - nvidia,tegra234-peq - nvidia,tegra194-peq - nvidia,tegra186-peq diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-sfc.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-sfc.yaml index 185ca0be4f026..959aa7fffdac3 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-sfc.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-sfc.yaml @@ -28,6 +28,7 @@ properties: - const: nvidia,tegra210-sfc - items: - enum: + - nvidia,tegra264-sfc - nvidia,tegra234-sfc - nvidia,tegra194-sfc - nvidia,tegra186-sfc diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.yaml index 3ca9affb79a20..8a8767589ee08 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.yaml @@ -20,11 +20,13 @@ properties: compatible: oneOf: - - const: nvidia,tegra30-hda + - enum: + - nvidia,tegra30-hda + - nvidia,tegra194-hda + - nvidia,tegra234-hda + - nvidia,tegra264-hda - items: - enum: - - nvidia,tegra234-hda - - nvidia,tegra194-hda - nvidia,tegra186-hda - nvidia,tegra210-hda - nvidia,tegra124-hda @@ -43,15 +45,12 @@ properties: maxItems: 1 clocks: - minItems: 2 + minItems: 1 maxItems: 3 clock-names: - minItems: 2 - items: - - const: hda - - const: hda2hdmi - - const: hda2codec_2x + minItems: 1 + maxItems: 3 resets: minItems: 2 @@ -59,10 +58,7 @@ properties: reset-names: minItems: 2 - items: - - const: hda - - const: hda2hdmi - - const: hda2codec_2x + maxItems: 3 power-domains: maxItems: 1 @@ -93,6 +89,92 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra30-hda + then: + properties: + clocks: + minItems: 3 + clock-names: + items: + - const: hda + - const: hda2hdmi + - const: hda2codec_2x + resets: + minItems: 3 + reset-names: + items: + - const: hda + - const: hda2hdmi + - const: hda2codec_2x + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra194-hda + then: + properties: + clocks: + minItems: 3 + clock-names: + items: + - const: hda + - const: hda2hdmi + - const: hda2codec_2x + resets: + maxItems: 2 + reset-names: + items: + - const: hda + - const: hda2hdmi + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra234-hda + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: hda + - const: hda2codec_2x + resets: + maxItems: 2 + reset-names: + items: + - const: hda + - const: hda2codec_2x + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra264-hda + then: + properties: + clocks: + maxItems: 1 + clock-names: + items: + - const: hda + resets: + maxItems: 2 + reset-names: + items: + - const: hda + - const: hda2codec_2x + power-domains: false + examples: - | #include diff --git a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml index b9e33a7429b0c..22fe6814b7066 100644 --- a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml @@ -28,9 +28,12 @@ properties: - qcom,sm8750-sndcard - const: qcom,sm8450-sndcard - enum: + - fairphone,fp5-sndcard - qcom,apq8096-sndcard - qcom,qcm6490-idp-sndcard - qcom,qcs6490-rb3gen2-sndcard + - qcom,qcs9075-sndcard + - qcom,qcs9100-sndcard - qcom,qrb4210-rb2-sndcard - qcom,qrb5165-rb5-sndcard - qcom,sc7180-qdsp6-sndcard diff --git a/Documentation/devicetree/bindings/sound/qcom,wcd938x.yaml b/Documentation/devicetree/bindings/sound/qcom,wcd938x.yaml index 10531350c3362..ab1c6285dbf89 100644 --- a/Documentation/devicetree/bindings/sound/qcom,wcd938x.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,wcd938x.yaml @@ -23,9 +23,15 @@ properties: - qcom,wcd9380-codec - qcom,wcd9385-codec + mux-controls: + description: A reference to the audio mux switch for + switching CTIA/OMTP Headset types + maxItems: 1 + us-euro-gpios: description: GPIO spec for swapping gnd and mic segments maxItems: 1 + deprecated: true required: - compatible diff --git a/Documentation/devicetree/bindings/sound/realtek,alc203.yaml b/Documentation/devicetree/bindings/sound/realtek,alc203.yaml new file mode 100644 index 0000000000000..6b90788b45eba --- /dev/null +++ b/Documentation/devicetree/bindings/sound/realtek,alc203.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/realtek,alc203.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek ALC203 AC97 Audio Codec + +maintainers: + - Keguang Zhang + +description: + ALC203 is a full duplex AC97 2.3 compatible stereo audio codec. + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + const: realtek,alc203 + + '#sound-dai-cells': + const: 0 + +required: + - compatible + - '#sound-dai-cells' + +unevaluatedProperties: false + +examples: + - | + audio-codec { + compatible = "realtek,alc203"; + #sound-dai-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/sound/richtek,rt9123.yaml b/Documentation/devicetree/bindings/sound/richtek,rt9123.yaml new file mode 100644 index 0000000000000..5acb05cdfefd7 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/richtek,rt9123.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/richtek,rt9123.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Richtek RT9123 Audio Amplifier + +maintainers: + - ChiYuan Huang + +description: + RT9123 is a 3.2W mono Class-D audio amplifier that features high efficiency + and performance with ultra-low quiescent current. The digital audio interface + support various formats, including I2S, left-justified, right-justified, and + TDM formats. + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + enum: + - richtek,rt9123 + + reg: + maxItems: 1 + + '#sound-dai-cells': + const: 0 + + enable-gpios: + maxItems: 1 + +required: + - compatible + - reg + - '#sound-dai-cells' + +unevaluatedProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + amplifier@5e { + compatible = "richtek,rt9123"; + reg = <0x5e>; + enable-gpios = <&gpio 26 GPIO_ACTIVE_HIGH>; + #sound-dai-cells = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/richtek,rt9123p.yaml b/Documentation/devicetree/bindings/sound/richtek,rt9123p.yaml new file mode 100644 index 0000000000000..693511dfdda40 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/richtek,rt9123p.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/richtek,rt9123p.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Richtek RT9123P Audio Amplifier + +maintainers: + - ChiYuan Huang + +description: + RT9123P is a RT9123 variant which does not support I2C control. + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + enum: + - richtek,rt9123p + + '#sound-dai-cells': + const: 0 + + enable-gpios: + maxItems: 1 + + enable-delay-ms: + description: + Delay time for 'ENABLE' pin changes intended to make I2S clocks ready to + prevent speaker pop noise. The unit is in millisecond. + +required: + - compatible + - '#sound-dai-cells' + +unevaluatedProperties: false + +examples: + - | + #include + + amplifier { + compatible = "richtek,rt9123p"; + enable-gpios = <&gpio 26 GPIO_ACTIVE_HIGH>; + #sound-dai-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/sound/rockchip,rk3576-sai.yaml b/Documentation/devicetree/bindings/sound/rockchip,rk3576-sai.yaml new file mode 100644 index 0000000000000..149da9a91451f --- /dev/null +++ b/Documentation/devicetree/bindings/sound/rockchip,rk3576-sai.yaml @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/rockchip,rk3576-sai.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip Serial Audio Interface Controller + +description: + The Rockchip Serial Audio Interface (SAI) controller is a flexible audio + controller that implements the I2S, I2S/TDM and the PDM standards. + +maintainers: + - Nicolas Frattaroli + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + const: rockchip,rk3576-sai + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + dmas: + minItems: 1 + maxItems: 2 + + dma-names: + minItems: 1 + items: + - enum: [tx, rx] + - const: rx + + clocks: + items: + - description: master audio clock + - description: AHB clock driving the interface + + clock-names: + items: + - const: mclk + - const: hclk + + resets: + minItems: 1 + items: + - description: reset for the mclk domain + - description: reset for the hclk domain + + reset-names: + minItems: 1 + items: + - const: m + - const: h + + port: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + + power-domains: + maxItems: 1 + + "#sound-dai-cells": + const: 0 + + rockchip,sai-rx-route: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Defines the mapping of the controller's SDI ports to actual input lanes, + as well as the number of input lanes. + rockchip,sai-rx-route = <3> would mean sdi3 is receiving from data0, and + that there is only one receiving lane. + This property's absence is to be understood as only one receiving lane + being used if the controller has capture capabilities. + maxItems: 4 + items: + minimum: 0 + maximum: 3 + + rockchip,sai-tx-route: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Defines the mapping of the controller's SDO ports to actual output lanes, + as well as the number of output lanes. + rockchip,sai-tx-route = <3> would mean sdo3 is sending to data0, and + that there is only one transmitting lane. + This property's absence is to be understood as only one transmitting lane + being used if the controller has playback capabilities. + maxItems: 4 + items: + minimum: 0 + maximum: 3 + +required: + - compatible + - reg + - dmas + - dma-names + - clocks + - clock-names + - "#sound-dai-cells" + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + sai1: sai@2a610000 { + compatible = "rockchip,rk3576-sai"; + reg = <0x0 0x2a610000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SAI1_8CH>, <&cru HCLK_SAI1_8CH>; + clock-names = "mclk", "hclk"; + dmas = <&dmac0 2>, <&dmac0 3>; + dma-names = "tx", "rx"; + power-domains = <&power RK3576_PD_AUDIO>; + resets = <&cru SRST_M_SAI1_8CH>, <&cru SRST_H_SAI1_8CH>; + reset-names = "m", "h"; + pinctrl-names = "default"; + pinctrl-0 = <&sai1m0_lrck + &sai1m0_sclk + &sai1m0_sdi0 + &sai1m0_sdo0 + &sai1m0_sdo1 + &sai1m0_sdo2 + &sai1m0_sdo3>; + rockchip,sai-tx-route = <3 1 2 0>; + #sound-dai-cells = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml b/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml index 3591c8c49bfe6..95d947fda6a70 100644 --- a/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml +++ b/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml @@ -15,13 +15,18 @@ description: properties: compatible: - enum: - - qcom,soundwire-v1.3.0 - - qcom,soundwire-v1.5.0 - - qcom,soundwire-v1.5.1 - - qcom,soundwire-v1.6.0 - - qcom,soundwire-v1.7.0 - - qcom,soundwire-v2.0.0 + oneOf: + - enum: + - qcom,soundwire-v1.3.0 + - qcom,soundwire-v1.5.0 + - qcom,soundwire-v1.5.1 + - qcom,soundwire-v1.6.0 + - qcom,soundwire-v1.7.0 + - qcom,soundwire-v2.0.0 + - items: + - enum: + - qcom,soundwire-v2.1.0 + - const: qcom,soundwire-v2.0.0 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/spi/fsl,dspi.yaml b/Documentation/devicetree/bindings/spi/fsl,dspi.yaml index 7ca8fceda7179..bf9cce53c48da 100644 --- a/Documentation/devicetree/bindings/spi/fsl,dspi.yaml +++ b/Documentation/devicetree/bindings/spi/fsl,dspi.yaml @@ -105,12 +105,12 @@ examples: big-endian; flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <16000000>; - spi-cpol; - spi-cpha; - spi-cs-setup-delay-ns = <100>; - spi-cs-hold-delay-ns = <50>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <16000000>; + spi-cpol; + spi-cpha; + spi-cs-setup-delay-ns = <100>; + spi-cs-hold-delay-ns = <50>; }; }; diff --git a/Documentation/devicetree/bindings/spi/nuvoton,wpcm450-fiu.yaml b/Documentation/devicetree/bindings/spi/nuvoton,wpcm450-fiu.yaml index 4e0d391e1d697..c97bf48b56b41 100644 --- a/Documentation/devicetree/bindings/spi/nuvoton,wpcm450-fiu.yaml +++ b/Documentation/devicetree/bindings/spi/nuvoton,wpcm450-fiu.yaml @@ -59,8 +59,3 @@ examples: reg = <0>; }; }; - - shm: syscon@c8001000 { - compatible = "nuvoton,wpcm450-shm", "syscon"; - reg = <0xc8001000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml index 48e97e2402656..8b3640280559d 100644 --- a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml @@ -10,9 +10,6 @@ maintainers: - Thierry Reding - Jonathan Hunter -allOf: - - $ref: spi-controller.yaml# - properties: compatible: enum: @@ -47,6 +44,9 @@ properties: - const: rx - const: tx + iommus: + maxItems: 1 + patternProperties: "@[0-9a-f]+$": type: object @@ -69,6 +69,18 @@ required: unevaluatedProperties: false +allOf: + - $ref: spi-controller.yaml# + - if: + properties: + compatible: + not: + contains: + const: nvidia,tegra234-qspi + then: + properties: + iommus: false + examples: - | #include diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml index aa3f933192034..cb1f15224b455 100644 --- a/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml @@ -21,8 +21,12 @@ allOf: properties: compatible: - enum: - - qcom,ipq9574-snand + oneOf: + - items: + - enum: + - qcom,ipq5018-snand + - const: qcom,ipq9574-snand + - const: qcom,ipq9574-snand reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml b/Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml index 49649fc3f95af..e0c7047ae8adb 100644 --- a/Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml +++ b/Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml @@ -4,14 +4,11 @@ $id: http://devicetree.org/schemas/spi/renesas,sh-msiof.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas MSIOF SPI controller +title: Renesas MSIOF SPI / I2S controller maintainers: - Geert Uytterhoeven -allOf: - - $ref: spi-controller.yaml# - properties: compatible: oneOf: @@ -146,24 +143,38 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 default: 64 + # for MSIOF-I2S + port: + $ref: ../sound/audio-graph-port.yaml# + unevaluatedProperties: false + required: - compatible - reg - interrupts - clocks - power-domains - - '#address-cells' - - '#size-cells' - -if: - not: - properties: - compatible: - contains: - const: renesas,sh-mobile-msiof -then: - required: - - resets + +allOf: + # additional "required"" + - if: + not: + properties: + compatible: + contains: + const: renesas,sh-mobile-msiof + then: + required: + - resets + + # If it doesn't have "port" node, it is "MSIOF-SPI" + - if: + not: + required: + - port + then: + allOf: + - $ref: spi-controller.yaml# unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/spi/samsung,spi.yaml b/Documentation/devicetree/bindings/spi/samsung,spi.yaml index 3c206a64d60ad..fe298d47b1a90 100644 --- a/Documentation/devicetree/bindings/spi/samsung,spi.yaml +++ b/Documentation/devicetree/bindings/spi/samsung,spi.yaml @@ -29,6 +29,7 @@ properties: - items: - enum: - samsung,exynos8895-spi + - samsung,exynosautov920-spi - const: samsung,exynos850-spi - const: samsung,exynos7-spi deprecated: true diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index 53d00ca643b31..0543c526b783a 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -83,9 +83,7 @@ properties: const: canaan,k210-spi - description: Renesas RZ/N1 SPI Controller items: - - enum: - - renesas,r9a06g032-spi # RZ/N1D - - renesas,r9a06g033-spi # RZ/N1S + - const: renesas,r9a06g032-spi # RZ/N1D - const: renesas,rzn1-spi # RZ/N1 reg: diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index 0bb443b8decda..8fc17e16efb20 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -8,12 +8,13 @@ title: Peripheral-specific properties for a SPI bus. description: Many SPI controllers need to add properties to peripheral devices. They could - be common properties like spi-max-frequency, spi-cpha, etc. or they could be - controller specific like delay in clock or data lines, etc. These properties - need to be defined in the peripheral node because they are per-peripheral and - there can be multiple peripherals attached to a controller. All those - properties are listed here. The controller specific properties should go in - their own separate schema that should be referenced from here. + be common properties like spi-max-frequency, spi-cs-high, etc. or they could + be controller specific like delay in clock or data lines, etc. These + properties need to be defined in the peripheral node because they are + per-peripheral and there can be multiple peripherals attached to a + controller. All those properties are listed here. The controller specific + properties should go in their own separate schema that should be referenced + from here. maintainers: - Mark Brown diff --git a/Documentation/devicetree/bindings/spi/spi-rockchip.yaml b/Documentation/devicetree/bindings/spi/spi-rockchip.yaml index 104f5ffdd04e3..748faf7f7081f 100644 --- a/Documentation/devicetree/bindings/spi/spi-rockchip.yaml +++ b/Documentation/devicetree/bindings/spi/spi-rockchip.yaml @@ -34,6 +34,7 @@ properties: - rockchip,rk3328-spi - rockchip,rk3368-spi - rockchip,rk3399-spi + - rockchip,rk3528-spi - rockchip,rk3562-spi - rockchip,rk3568-spi - rockchip,rk3576-spi diff --git a/Documentation/devicetree/bindings/spi/st,stm32mp25-ospi.yaml b/Documentation/devicetree/bindings/spi/st,stm32mp25-ospi.yaml index 5f276f27dc4c1..272bc308726b2 100644 --- a/Documentation/devicetree/bindings/spi/st,stm32mp25-ospi.yaml +++ b/Documentation/devicetree/bindings/spi/st,stm32mp25-ospi.yaml @@ -68,6 +68,7 @@ required: - compatible - reg - clocks + - resets - interrupts - st,syscfg-dlyb diff --git a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml index a7236f7db4ec3..e7f7cf72719ea 100644 --- a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml +++ b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml @@ -50,6 +50,7 @@ properties: - enum: - allwinner,sun50i-a100-system-control - allwinner,sun50i-h6-system-control + - allwinner,sun55i-a523-system-control - const: allwinner,sun50i-a64-system-control reg: diff --git a/Documentation/devicetree/bindings/thermal/airoha,en7581-thermal.yaml b/Documentation/devicetree/bindings/thermal/airoha,en7581-thermal.yaml new file mode 100644 index 0000000000000..ca0242ef03788 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/airoha,en7581-thermal.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/airoha,en7581-thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha EN7581 Thermal Sensor and Monitor + +maintainers: + - Christian Marangi + +properties: + compatible: + const: airoha,en7581-thermal + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + airoha,chip-scu: + description: phandle to the chip SCU syscon + $ref: /schemas/types.yaml#/definitions/phandle + + '#thermal-sensor-cells': + const: 0 + +required: + - compatible + - reg + - interrupts + - airoha,chip-scu + +additionalProperties: false + +examples: + - | + #include + + thermal-sensor@1efbd800 { + compatible = "airoha,en7581-thermal"; + reg = <0x1efbd000 0xd5c>; + interrupts = ; + airoha,chip-scu = <&chip_scu>; + + #thermal-sensor-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index f9d8012c8cf51..0e653bbe98849 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -39,6 +39,7 @@ properties: - description: v1 of TSENS items: - enum: + - qcom,ipq5018-tsens - qcom,msm8937-tsens - qcom,msm8956-tsens - qcom,msm8976-tsens @@ -251,6 +252,7 @@ allOf: compatible: contains: enum: + - qcom,ipq5018-tsens - qcom,ipq8064-tsens - qcom,msm8960-tsens - qcom,tsens-v0_1 diff --git a/Documentation/devicetree/bindings/timer/altr,timer-1.0.txt b/Documentation/devicetree/bindings/timer/altr,timer-1.0.txt deleted file mode 100644 index e698e34887356..0000000000000 --- a/Documentation/devicetree/bindings/timer/altr,timer-1.0.txt +++ /dev/null @@ -1,18 +0,0 @@ -Altera Timer - -Required properties: - -- compatible : should be "altr,timer-1.0" -- reg : Specifies base physical address and size of the registers. -- interrupts : Should contain the timer interrupt number -- clock-frequency : The frequency of the clock that drives the counter, in Hz. - -Example: - -timer { - compatible = "altr,timer-1.0"; - reg = <0x00400000 0x00000020>; - interrupt-parent = <&cpu>; - interrupts = <11>; - clock-frequency = <125000000>; -}; diff --git a/Documentation/devicetree/bindings/timer/altr,timer-1.0.yaml b/Documentation/devicetree/bindings/timer/altr,timer-1.0.yaml new file mode 100644 index 0000000000000..576260c72d42e --- /dev/null +++ b/Documentation/devicetree/bindings/timer/altr,timer-1.0.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/altr,timer-1.0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera Timer + +maintainers: + - Dinh Nguyen + +properties: + compatible: + const: altr,timer-1.0 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-frequency: + description: Frequency of the clock that drives the counter, in Hz. + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + timer@400000 { + compatible = "altr,timer-1.0"; + reg = <0x00400000 0x00000020>; + interrupts = <11>; + clock-frequency = <125000000>; + }; diff --git a/Documentation/devicetree/bindings/timer/arm,mps2-timer.txt b/Documentation/devicetree/bindings/timer/arm,mps2-timer.txt deleted file mode 100644 index 48f84d74edde6..0000000000000 --- a/Documentation/devicetree/bindings/timer/arm,mps2-timer.txt +++ /dev/null @@ -1,28 +0,0 @@ -ARM MPS2 timer - -The MPS2 platform has simple general-purpose 32 bits timers. - -Required properties: -- compatible : Should be "arm,mps2-timer" -- reg : Address and length of the register set -- interrupts : Reference to the timer interrupt - -Required clocking property, have to be one of: -- clocks : The input clock of the timer -- clock-frequency : The rate in HZ in input of the ARM MPS2 timer - -Examples: - -timer1: mps2-timer@40000000 { - compatible = "arm,mps2-timer"; - reg = <0x40000000 0x1000>; - interrupts = <8>; - clocks = <&sysclk>; -}; - -timer2: mps2-timer@40001000 { - compatible = "arm,mps2-timer"; - reg = <0x40001000 0x1000>; - interrupts = <9>; - clock-frequency = <25000000>; -}; diff --git a/Documentation/devicetree/bindings/timer/arm,mps2-timer.yaml b/Documentation/devicetree/bindings/timer/arm,mps2-timer.yaml new file mode 100644 index 0000000000000..64c6aedd7e8e2 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/arm,mps2-timer.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm,mps2-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM MPS2 timer + +maintainers: + - Vladimir Murzin + +description: + The MPS2 platform has simple general-purpose 32 bits timers. + +properties: + compatible: + const: arm,mps2-timer + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-frequency: + description: Rate in Hz of the timer input clock + +oneOf: + - required: [clocks] + - required: [clock-frequency] + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + timer@40000000 { + compatible = "arm,mps2-timer"; + reg = <0x40000000 0x1000>; + interrupts = <8>; + clocks = <&sysclk>; + }; diff --git a/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.txt b/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.txt deleted file mode 100644 index d4c62e7b1714e..0000000000000 --- a/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.txt +++ /dev/null @@ -1,29 +0,0 @@ -* Cirrus Logic CLPS711X Timer Counter - -Required properties: -- compatible: Shall contain "cirrus,ep7209-timer". -- reg : Address and length of the register set. -- interrupts: The interrupt number of the timer. -- clocks : phandle of timer reference clock. - -Note: Each timer should have an alias correctly numbered in "aliases" node. - -Example: - aliases { - timer0 = &timer1; - timer1 = &timer2; - }; - - timer1: timer@80000300 { - compatible = "cirrus,ep7312-timer", "cirrus,ep7209-timer"; - reg = <0x80000300 0x4>; - interrupts = <8>; - clocks = <&clks 5>; - }; - - timer2: timer@80000340 { - compatible = "cirrus,ep7312-timer", "cirrus,ep7209-timer"; - reg = <0x80000340 0x4>; - interrupts = <9>; - clocks = <&clks 6>; - }; diff --git a/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.yaml b/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.yaml new file mode 100644 index 0000000000000..507b777e16bc4 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/cirrus,clps711x-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic CLPS711X Timer Counter + +maintainers: + - Alexander Shiyan + +properties: + compatible: + oneOf: + - items: + - enum: + - cirrus,ep7312-timer + - const: cirrus,ep7209-timer + - const: cirrus,ep7209-timer + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - interrupts + +additionalProperties: false + +examples: + - | + timer@80000300 { + compatible = "cirrus,ep7312-timer", "cirrus,ep7209-timer"; + reg = <0x80000300 0x4>; + interrupts = <8>; + clocks = <&clks 5>; + }; diff --git a/Documentation/devicetree/bindings/timer/cnxt,cx92755-timer.yaml b/Documentation/devicetree/bindings/timer/cnxt,cx92755-timer.yaml new file mode 100644 index 0000000000000..8f1a5af32a36d --- /dev/null +++ b/Documentation/devicetree/bindings/timer/cnxt,cx92755-timer.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cnxt,cx92755-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Conexant Digicolor SoCs Timer Controller + +maintainers: + - Baruch Siach + +properties: + compatible: + const: cnxt,cx92755-timer + + reg: + maxItems: 1 + + interrupts: + description: Contains 8 interrupts, one for each timer + items: + - description: interrupt for timer 0 + - description: interrupt for timer 1 + - description: interrupt for timer 2 + - description: interrupt for timer 3 + - description: interrupt for timer 4 + - description: interrupt for timer 5 + - description: interrupt for timer 6 + - description: interrupt for timer 7 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + timer@f0000fc0 { + compatible = "cnxt,cx92755-timer"; + reg = <0xf0000fc0 0x40>; + interrupts = <19>, <31>, <34>, <35>, <52>, <53>, <54>, <55>; + clocks = <&main_clk>; + }; diff --git a/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt b/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt deleted file mode 100644 index 6b04344f4beaa..0000000000000 --- a/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt +++ /dev/null @@ -1,42 +0,0 @@ -================= -gx6605s SOC Timer -================= - -The timer is used in gx6605s soc as system timer and the driver -contain clk event and clk source. - -============================== -timer node bindings definition -============================== - - Description: Describes gx6605s SOC timer - - PROPERTIES - - - compatible - Usage: required - Value type: - Definition: must be "csky,gx6605s-timer" - - reg - Usage: required - Value type: - Definition: in soc from cpu view - - clocks - Usage: required - Value type: phandle + clock specifier cells - Definition: must be input clk node - - interrupt - Usage: required - Value type: - Definition: must be timer irq num defined by soc - -Examples: ---------- - - timer0: timer@20a000 { - compatible = "csky,gx6605s-timer"; - reg = <0x0020a000 0x400>; - clocks = <&dummy_apb_clk>; - interrupts = <10>; - interrupt-parent = <&intc>; - }; diff --git a/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.yaml b/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.yaml new file mode 100644 index 0000000000000..888fc8113996a --- /dev/null +++ b/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/csky,gx6605s-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: gx6605s SOC Timer + +maintainers: + - Guo Ren + +properties: + compatible: + const: csky,gx6605s-timer + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - interrupts + +additionalProperties: false + +examples: + - | + timer@20a000 { + compatible = "csky,gx6605s-timer"; + reg = <0x0020a000 0x400>; + clocks = <&dummy_apb_clk>; + interrupts = <10>; + }; diff --git a/Documentation/devicetree/bindings/timer/csky,mptimer.txt b/Documentation/devicetree/bindings/timer/csky,mptimer.txt deleted file mode 100644 index f5c7e99cf52bf..0000000000000 --- a/Documentation/devicetree/bindings/timer/csky,mptimer.txt +++ /dev/null @@ -1,42 +0,0 @@ -============================ -C-SKY Multi-processors Timer -============================ - -C-SKY multi-processors timer is designed for C-SKY SMP system and the -regs is accessed by cpu co-processor 4 registers with mtcr/mfcr. - - - PTIM_CTLR "cr<0, 14>" Control reg to start reset timer. - - PTIM_TSR "cr<1, 14>" Interrupt cleanup status reg. - - PTIM_CCVR "cr<3, 14>" Current counter value reg. - - PTIM_LVR "cr<6, 14>" Window value reg to trigger next event. - -============================== -timer node bindings definition -============================== - - Description: Describes SMP timer - - PROPERTIES - - - compatible - Usage: required - Value type: - Definition: must be "csky,mptimer" - - clocks - Usage: required - Value type: - Definition: must be input clk node - - interrupts - Usage: required - Value type: - Definition: must be timer irq num defined by soc - -Examples: ---------- - - timer: timer { - compatible = "csky,mptimer"; - clocks = <&dummy_apb_clk>; - interrupts = <16>; - interrupt-parent = <&intc>; - }; diff --git a/Documentation/devicetree/bindings/timer/csky,mptimer.yaml b/Documentation/devicetree/bindings/timer/csky,mptimer.yaml new file mode 100644 index 0000000000000..12cc5282c8f80 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/csky,mptimer.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/csky,mptimer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: C-SKY Multi-processors Timer + +maintainers: + - Flavio Suligoi + - Guo Ren + +description: | + C-SKY multi-processors timer is designed for C-SKY SMP system and the regs are + accessed by cpu co-processor 4 registers with mtcr/mfcr. + + - PTIM_CTLR "cr<0, 14>" Control reg to start reset timer. + - PTIM_TSR "cr<1, 14>" Interrupt cleanup status reg. + - PTIM_CCVR "cr<3, 14>" Current counter value reg. + - PTIM_LVR "cr<6, 14>" Window value reg to trigger next event. + +properties: + compatible: + items: + - const: csky,mptimer + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - clocks + - interrupts + +additionalProperties: false + +examples: + - | + timer { + compatible = "csky,mptimer"; + clocks = <&dummy_apb_clk>; + interrupts = <16>; + }; diff --git a/Documentation/devicetree/bindings/timer/digicolor-timer.txt b/Documentation/devicetree/bindings/timer/digicolor-timer.txt deleted file mode 100644 index d1b659bbc29fc..0000000000000 --- a/Documentation/devicetree/bindings/timer/digicolor-timer.txt +++ /dev/null @@ -1,18 +0,0 @@ -Conexant Digicolor SoCs Timer Controller - -Required properties: - -- compatible : should be "cnxt,cx92755-timer" -- reg : Specifies base physical address and size of the "Agent Communication" - timer registers -- interrupts : Contains 8 interrupts, one for each timer -- clocks: phandle to the main clock - -Example: - - timer@f0000fc0 { - compatible = "cnxt,cx92755-timer"; - reg = <0xf0000fc0 0x40>; - interrupts = <19>, <31>, <34>, <35>, <52>, <53>, <54>, <55>; - clocks = <&main_clk>; - }; diff --git a/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml b/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml new file mode 100644 index 0000000000000..c1e7c2b6afde1 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/econet,en751221-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EcoNet EN751221 High Precision Timer (HPT) + +maintainers: + - Caleb James DeLisle + +description: + The EcoNet High Precision Timer (HPT) is a timer peripheral found in various + EcoNet SoCs, including the EN751221 and EN751627 families. It provides per-VPE + count/compare registers and a per-CPU control register, with a single interrupt + line using a percpu-devid interrupt mechanism. + +properties: + compatible: + oneOf: + - const: econet,en751221-timer + - items: + - const: econet,en751627-timer + - const: econet,en751221-timer + + reg: + minItems: 1 + maxItems: 2 + + interrupts: + maxItems: 1 + description: A percpu-devid timer interrupt shared across CPUs. + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +allOf: + - if: + properties: + compatible: + contains: + const: econet,en751627-timer + then: + properties: + reg: + items: + - description: VPE timers 0 and 1 + - description: VPE timers 2 and 3 + else: + properties: + reg: + items: + - description: VPE timers 0 and 1 + +additionalProperties: false + +examples: + - | + timer@1fbf0400 { + compatible = "econet,en751627-timer", "econet,en751221-timer"; + reg = <0x1fbf0400 0x100>, <0x1fbe0000 0x100>; + interrupt-parent = <&intc>; + interrupts = <30>; + clocks = <&hpt_clock>; + }; + - | + timer@1fbf0400 { + compatible = "econet,en751221-timer"; + reg = <0x1fbe0400 0x100>; + interrupt-parent = <&intc>; + interrupts = <30>; + clocks = <&hpt_clock>; + }; +... diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.yaml b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.yaml new file mode 100644 index 0000000000000..317c5010c4c11 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ezchip,nps400-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EZChip NPS400 Timers + +maintainers: + - Noam Camus + +properties: + compatible: + enum: + - ezchip,nps400-timer0 + - ezchip,nps400-timer1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - clocks + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: ezchip,nps400-timer0 + then: + required: [ interrupts ] + +examples: + - | + timer { + compatible = "ezchip,nps400-timer0"; + interrupts = <3>; + clocks = <&sysclk>; + }; diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt deleted file mode 100644 index e3cfce8fecc5d..0000000000000 --- a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt +++ /dev/null @@ -1,17 +0,0 @@ -NPS Network Processor - -Required properties: - -- compatible : should be "ezchip,nps400-timer0" - -Clocks required for compatible = "ezchip,nps400-timer0": -- interrupts : The interrupt of the first timer -- clocks : Must contain a single entry describing the clock input - -Example: - -timer { - compatible = "ezchip,nps400-timer0"; - interrupts = <3>; - clocks = <&sysclk>; -}; diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt deleted file mode 100644 index c0ab4190b8fba..0000000000000 --- a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt +++ /dev/null @@ -1,15 +0,0 @@ -NPS Network Processor - -Required properties: - -- compatible : should be "ezchip,nps400-timer1" - -Clocks required for compatible = "ezchip,nps400-timer1": -- clocks : Must contain a single entry describing the clock input - -Example: - -timer { - compatible = "ezchip,nps400-timer1"; - clocks = <&sysclk>; -}; diff --git a/Documentation/devicetree/bindings/timer/fsl,gtm.txt b/Documentation/devicetree/bindings/timer/fsl,gtm.txt deleted file mode 100644 index fc1c571f74123..0000000000000 --- a/Documentation/devicetree/bindings/timer/fsl,gtm.txt +++ /dev/null @@ -1,30 +0,0 @@ -* Freescale General-purpose Timers Module - -Required properties: - - compatible : should be - "fsl,-gtm", "fsl,gtm" for SOC GTMs - "fsl,-qe-gtm", "fsl,qe-gtm", "fsl,gtm" for QE GTMs - "fsl,-cpm2-gtm", "fsl,cpm2-gtm", "fsl,gtm" for CPM2 GTMs - - reg : should contain gtm registers location and length (0x40). - - interrupts : should contain four interrupts. - - clock-frequency : specifies the frequency driving the timer. - -Example: - -timer@500 { - compatible = "fsl,mpc8360-gtm", "fsl,gtm"; - reg = <0x500 0x40>; - interrupts = <90 8 78 8 84 8 72 8>; - interrupt-parent = <&ipic>; - /* filled by u-boot */ - clock-frequency = <0>; -}; - -timer@440 { - compatible = "fsl,mpc8360-qe-gtm", "fsl,qe-gtm", "fsl,gtm"; - reg = <0x440 0x40>; - interrupts = <12 13 14 15>; - interrupt-parent = <&qeic>; - /* filled by u-boot */ - clock-frequency = <0>; -}; diff --git a/Documentation/devicetree/bindings/timer/fsl,gtm.yaml b/Documentation/devicetree/bindings/timer/fsl,gtm.yaml new file mode 100644 index 0000000000000..1f35f1ee0be2a --- /dev/null +++ b/Documentation/devicetree/bindings/timer/fsl,gtm.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/fsl,gtm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale General-purpose Timers Module + +maintainers: + - J. Neuschäfer + +properties: + compatible: + oneOf: + # for SoC GTMs + - items: + - enum: + - fsl,mpc8308-gtm + - fsl,mpc8313-gtm + - fsl,mpc8315-gtm + - fsl,mpc8360-gtm + - const: fsl,gtm + + # for QE GTMs + - items: + - enum: + - fsl,mpc8360-qe-gtm + - fsl,mpc8569-qe-gtm + - const: fsl,qe-gtm + - const: fsl,gtm + + # for CPM2 GTMs (no known examples) + - items: + # - enum: + # - fsl,-cpm2-gtm + - const: fsl,cpm2-gtm + - const: fsl,gtm + + reg: + maxItems: 1 + + interrupts: + items: + - description: Interrupt for timer 1 (e.g. GTM1 or GTM5) + - description: Interrupt for timer 2 (e.g. GTM2 or GTM6) + - description: Interrupt for timer 3 (e.g. GTM3 or GTM7) + - description: Interrupt for timer 4 (e.g. GTM4 or GTM8) + + clock-frequency: true + +required: + - compatible + - reg + - interrupts + - clock-frequency + +additionalProperties: false + +examples: + - | + #include + + timer@500 { + compatible = "fsl,mpc8360-gtm", "fsl,gtm"; + reg = <0x500 0x40>; + interrupts = <90 IRQ_TYPE_LEVEL_LOW>, + <78 IRQ_TYPE_LEVEL_LOW>, + <84 IRQ_TYPE_LEVEL_LOW>, + <72 IRQ_TYPE_LEVEL_LOW>; + /* filled by u-boot */ + clock-frequency = <0>; + }; + + - | + timer@440 { + compatible = "fsl,mpc8360-qe-gtm", "fsl,qe-gtm", "fsl,gtm"; + reg = <0x440 0x40>; + interrupts = <12>, <13>, <14>, <15>; + /* filled by u-boot */ + clock-frequency = <0>; + }; + +... diff --git a/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml b/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml new file mode 100644 index 0000000000000..bee2c35bd0e29 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/fsl,vf610-pit.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Periodic Interrupt Timer (PIT) + +maintainers: + - Frank Li + +description: + The PIT module is an array of timers that can be used to raise interrupts + and trigger DMA channels. + +properties: + compatible: + enum: + - fsl,vf610-pit + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: pit + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + timer@40037000 { + compatible = "fsl,vf610-pit"; + reg = <0x40037000 0x1000>; + interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_PIT>; + clock-names = "pit"; + }; diff --git a/Documentation/devicetree/bindings/timer/img,pistachio-gptimer.txt b/Documentation/devicetree/bindings/timer/img,pistachio-gptimer.txt deleted file mode 100644 index 7afce80bf6a01..0000000000000 --- a/Documentation/devicetree/bindings/timer/img,pistachio-gptimer.txt +++ /dev/null @@ -1,28 +0,0 @@ -* Pistachio general-purpose timer based clocksource - -Required properties: - - compatible: "img,pistachio-gptimer". - - reg: Address range of the timer registers. - - interrupts: An interrupt for each of the four timers - - clocks: Should contain a clock specifier for each entry in clock-names - - clock-names: Should contain the following entries: - "sys", interface clock - "slow", slow counter clock - "fast", fast counter clock - - img,cr-periph: Must contain a phandle to the peripheral control - syscon node. - -Example: - timer: timer@18102000 { - compatible = "img,pistachio-gptimer"; - reg = <0x18102000 0x100>; - interrupts = , - , - , - ; - clocks = <&clk_periph PERIPH_CLK_COUNTER_FAST>, - <&clk_periph PERIPH_CLK_COUNTER_SLOW>, - <&cr_periph SYS_CLK_TIMER>; - clock-names = "fast", "slow", "sys"; - img,cr-periph = <&cr_periph>; - }; diff --git a/Documentation/devicetree/bindings/timer/img,pistachio-gptimer.yaml b/Documentation/devicetree/bindings/timer/img,pistachio-gptimer.yaml new file mode 100644 index 0000000000000..a8654bcf68a98 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/img,pistachio-gptimer.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/img,pistachio-gptimer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Pistachio general-purpose timer + +maintainers: + - Ezequiel Garcia + +properties: + compatible: + const: img,pistachio-gptimer + + reg: + maxItems: 1 + + interrupts: + items: + - description: Timer0 interrupt + - description: Timer1 interrupt + - description: Timer2 interrupt + - description: Timer3 interrupt + + clocks: + items: + - description: Fast counter clock + - description: Slow counter clock + - description: Interface clock + + clock-names: + items: + - const: fast + - const: slow + - const: sys + + img,cr-periph: + description: Peripheral control syscon phandle + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - img,cr-periph + +additionalProperties: false + +examples: + - | + #include + #include + + timer@18102000 { + compatible = "img,pistachio-gptimer"; + reg = <0x18102000 0x100>; + interrupts = , + , + , + ; + clocks = <&clk_periph PERIPH_CLK_COUNTER_FAST>, + <&clk_periph PERIPH_CLK_COUNTER_SLOW>, + <&cr_periph SYS_CLK_TIMER>; + clock-names = "fast", "slow", "sys"; + img,cr-periph = <&cr_periph>; + }; diff --git a/Documentation/devicetree/bindings/timer/jcore,pit.txt b/Documentation/devicetree/bindings/timer/jcore,pit.txt deleted file mode 100644 index af5dd35469d73..0000000000000 --- a/Documentation/devicetree/bindings/timer/jcore,pit.txt +++ /dev/null @@ -1,24 +0,0 @@ -J-Core Programmable Interval Timer and Clocksource - -Required properties: - -- compatible: Must be "jcore,pit". - -- reg: Memory region(s) for timer/clocksource registers. For SMP, - there should be one region per cpu, indexed by the sequential, - zero-based hardware cpu number. - -- interrupts: An interrupt to assign for the timer. The actual pit - core is integrated with the aic and allows the timer interrupt - assignment to be programmed by software, but this property is - required in order to reserve an interrupt number that doesn't - conflict with other devices. - - -Example: - -timer@200 { - compatible = "jcore,pit"; - reg = < 0x200 0x30 0x500 0x30 >; - interrupts = < 0x48 >; -}; diff --git a/Documentation/devicetree/bindings/timer/jcore,pit.yaml b/Documentation/devicetree/bindings/timer/jcore,pit.yaml new file mode 100644 index 0000000000000..9e6e25b75293f --- /dev/null +++ b/Documentation/devicetree/bindings/timer/jcore,pit.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/jcore,pit.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: J-Core Programmable Interval Timer and Clocksource + +maintainers: + - Rich Felker + +properties: + compatible: + const: jcore,pit + + reg: + description: + Memory region(s) for timer/clocksource registers. For SMP, there should be + one region per cpu, indexed by the sequential, zero-based hardware cpu + number. + + interrupts: + description: + An interrupt to assign for the timer. The actual pit core is integrated + with the aic and allows the timer interrupt assignment to be programmed by + software, but this property is required in order to reserve an interrupt + number that doesn't conflict with other devices. + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + timer@200 { + compatible = "jcore,pit"; + reg = <0x200 0x30 0x500 0x30>; + interrupts = <0x48>; + }; diff --git a/Documentation/devicetree/bindings/timer/lsi,zevio-timer.txt b/Documentation/devicetree/bindings/timer/lsi,zevio-timer.txt deleted file mode 100644 index b2d07ad90e9a9..0000000000000 --- a/Documentation/devicetree/bindings/timer/lsi,zevio-timer.txt +++ /dev/null @@ -1,33 +0,0 @@ -TI-NSPIRE timer - -Required properties: - -- compatible : should be "lsi,zevio-timer". -- reg : The physical base address and size of the timer (always first). -- clocks: phandle to the source clock. - -Optional properties: - -- interrupts : The interrupt number of the first timer. -- reg : The interrupt acknowledgement registers - (always after timer base address) - -If any of the optional properties are not given, the timer is added as a -clock-source only. - -Example: - -timer { - compatible = "lsi,zevio-timer"; - reg = <0x900D0000 0x1000>, <0x900A0020 0x8>; - interrupts = <19>; - clocks = <&timer_clk>; -}; - -Example (no clock-events): - -timer { - compatible = "lsi,zevio-timer"; - reg = <0x900D0000 0x1000>; - clocks = <&timer_clk>; -}; diff --git a/Documentation/devicetree/bindings/timer/lsi,zevio-timer.yaml b/Documentation/devicetree/bindings/timer/lsi,zevio-timer.yaml new file mode 100644 index 0000000000000..358455d8e7a8c --- /dev/null +++ b/Documentation/devicetree/bindings/timer/lsi,zevio-timer.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/lsi,zevio-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI-NSPIRE timer + +maintainers: + - Daniel Tang + +properties: + compatible: + const: lsi,zevio-timer + + reg: + minItems: 1 + items: + - description: Timer registers + - description: Interrupt acknowledgement registers (optional) + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +allOf: + - if: + required: [ interrupts ] + then: + properties: + reg: + minItems: 2 + +additionalProperties: false + +examples: + - | + timer@900d0000 { + compatible = "lsi,zevio-timer"; + reg = <0x900D0000 0x1000>, <0x900A0020 0x8>; + interrupts = <19>; + clocks = <&timer_clk>; + }; + - | + timer@900d0000 { + compatible = "lsi,zevio-timer"; + reg = <0x900D0000 0x1000>; + clocks = <&timer_clk>; + }; diff --git a/Documentation/devicetree/bindings/timer/marvell,armada-370-timer.yaml b/Documentation/devicetree/bindings/timer/marvell,armada-370-timer.yaml new file mode 100644 index 0000000000000..bc0677fe86eb3 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/marvell,armada-370-timer.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/marvell,armada-370-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 370, 375, 380 and XP Timers + +maintainers: + - Andrew Lunn + - Gregory Clement + +properties: + compatible: + oneOf: + - items: + - const: marvell,armada-380-timer + - const: marvell,armada-xp-timer + - items: + - const: marvell,armada-375-timer + - const: marvell,armada-370-timer + - enum: + - marvell,armada-370-timer + - marvell,armada-xp-timer + + reg: + items: + - description: Global timer registers + - description: Local/private timer registers + + interrupts: + items: + - description: Global timer interrupt 0 + - description: Global timer interrupt 1 + - description: Global timer interrupt 2 + - description: Global timer interrupt 3 + - description: First private timer interrupt + - description: Second private timer interrupt + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + items: + - const: nbclk + - const: fixed + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + enum: + - marvell,armada-375-timer + - marvell,armada-xp-timer + then: + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + required: + - clock-names + else: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + +examples: + - | + timer@20300 { + compatible = "marvell,armada-xp-timer"; + reg = <0x20300 0x30>, <0x21040 0x30>; + interrupts = <37>, <38>, <39>, <40>, <5>, <6>; + clocks = <&coreclk 2>, <&refclk>; + clock-names = "nbclk", "fixed"; + }; diff --git a/Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt b/Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt deleted file mode 100644 index e9c78ce880e60..0000000000000 --- a/Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt +++ /dev/null @@ -1,44 +0,0 @@ -Marvell Armada 370 and Armada XP Timers ---------------------------------------- - -Required properties: -- compatible: Should be one of the following - "marvell,armada-370-timer", - "marvell,armada-375-timer", - "marvell,armada-xp-timer". -- interrupts: Should contain the list of Global Timer interrupts and - then local timer interrupts -- reg: Should contain location and length for timers register. First - pair for the Global Timer registers, second pair for the - local/private timers. - -Clocks required for compatible = "marvell,armada-370-timer": -- clocks : Must contain a single entry describing the clock input - -Clocks required for compatibles = "marvell,armada-xp-timer", - "marvell,armada-375-timer": -- clocks : Must contain an entry for each entry in clock-names. -- clock-names : Must include the following entries: - "nbclk" (L2/coherency fabric clock), - "fixed" (Reference 25 MHz fixed-clock). - -Examples: - -- Armada 370: - - timer { - compatible = "marvell,armada-370-timer"; - reg = <0x20300 0x30>, <0x21040 0x30>; - interrupts = <37>, <38>, <39>, <40>, <5>, <6>; - clocks = <&coreclk 2>; - }; - -- Armada XP: - - timer { - compatible = "marvell,armada-xp-timer"; - reg = <0x20300 0x30>, <0x21040 0x30>; - interrupts = <37>, <38>, <39>, <40>, <5>, <6>; - clocks = <&coreclk 2>, <&refclk>; - clock-names = "nbclk", "fixed"; - }; diff --git a/Documentation/devicetree/bindings/timer/marvell,orion-timer.txt b/Documentation/devicetree/bindings/timer/marvell,orion-timer.txt deleted file mode 100644 index cd1a0c256f940..0000000000000 --- a/Documentation/devicetree/bindings/timer/marvell,orion-timer.txt +++ /dev/null @@ -1,16 +0,0 @@ -Marvell Orion SoC timer - -Required properties: -- compatible: shall be "marvell,orion-timer" -- reg: base address of the timer register starting with TIMERS CONTROL register -- interrupts: should contain the interrupts for Timer0 and Timer1 -- clocks: phandle of timer reference clock (tclk) - -Example: - timer: timer { - compatible = "marvell,orion-timer"; - reg = <0x20300 0x20>; - interrupt-parent = <&bridge_intc>; - interrupts = <1>, <2>; - clocks = <&core_clk 0>; - }; diff --git a/Documentation/devicetree/bindings/timer/marvell,orion-timer.yaml b/Documentation/devicetree/bindings/timer/marvell,orion-timer.yaml new file mode 100644 index 0000000000000..f973afffa5ba6 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/marvell,orion-timer.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/marvell,orion-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Orion SoC timer + +maintainers: + - Andrew Lunn + - Gregory Clement + +properties: + compatible: + const: marvell,orion-timer + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + items: + - description: Timer0 interrupt + - description: Timer1 interrupt + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + timer@20300 { + compatible = "marvell,orion-timer"; + reg = <0x20300 0x20>; + interrupts = <1>, <2>; + clocks = <&core_clk 0>; + }; diff --git a/Documentation/devicetree/bindings/timer/nxp,s32g2-stm.yaml b/Documentation/devicetree/bindings/timer/nxp,s32g2-stm.yaml new file mode 100644 index 0000000000000..b44b9794bb858 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/nxp,s32g2-stm.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/nxp,s32g2-stm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP System Timer Module (STM) + +maintainers: + - Daniel Lezcano + +description: + The System Timer Module supports commonly required system and application + software timing functions. STM includes a 32-bit count-up timer and four + 32-bit compare channels with a separate interrupt source for each channel. + The timer is driven by the STM module clock divided by an 8-bit prescale + value. + +properties: + compatible: + oneOf: + - const: nxp,s32g2-stm + - items: + - const: nxp,s32g3-stm + - const: nxp,s32g2-stm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Counter clock + - description: Module clock + - description: Register clock + + clock-names: + items: + - const: counter + - const: module + - const: register + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + + timer@4011c000 { + compatible = "nxp,s32g2-stm"; + reg = <0x4011c000 0x3000>; + interrupts = ; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + }; diff --git a/Documentation/devicetree/bindings/timer/renesas,ostm.yaml b/Documentation/devicetree/bindings/timer/renesas,ostm.yaml index 9ba858f094abd..0983c1efec80a 100644 --- a/Documentation/devicetree/bindings/timer/renesas,ostm.yaml +++ b/Documentation/devicetree/bindings/timer/renesas,ostm.yaml @@ -26,6 +26,7 @@ properties: - renesas,r9a07g043-ostm # RZ/G2UL and RZ/Five - renesas,r9a07g044-ostm # RZ/G2{L,LC} - renesas,r9a07g054-ostm # RZ/V2L + - renesas,r9a09g056-ostm # RZ/V2N - renesas,r9a09g057-ostm # RZ/V2H(P) - const: renesas,ostm # Generic @@ -54,12 +55,11 @@ required: if: properties: compatible: - contains: - enum: - - renesas,r9a07g043-ostm - - renesas,r9a07g044-ostm - - renesas,r9a07g054-ostm - - renesas,r9a09g057-ostm + not: + contains: + enum: + - renesas,r7s72100-ostm + - renesas,r7s9210-ostm then: required: - resets diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index 653e2e0ca878f..d85a1a088b35d 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -30,6 +30,7 @@ properties: - items: - enum: - canaan,k210-clint # Canaan Kendryte K210 + - eswin,eic7700-clint # ESWIN EIC7700 - sifive,fu540-c000-clint # SiFive FU540 - spacemit,k1-clint # SpacemiT K1 - starfive,jh7100-clint # StarFive JH7100 diff --git a/Documentation/devicetree/bindings/timer/snps,arc-timer.txt b/Documentation/devicetree/bindings/timer/snps,arc-timer.txt deleted file mode 100644 index b02ab0af10ce2..0000000000000 --- a/Documentation/devicetree/bindings/timer/snps,arc-timer.txt +++ /dev/null @@ -1,27 +0,0 @@ -Synopsys ARC Local Timer with Interrupt Capabilities -- Found on all ARC CPUs (ARC700/ARCHS) -- Can be optionally programmed to interrupt on Limit -- Two identical copies TIMER0 and TIMER1 exist in ARC cores and historically - TIMER0 used as clockevent provider (true for all ARC cores) - TIMER1 used for clocksource (mandatory for ARC700, optional for ARC HS) - -Required properties: - -- compatible : should be "snps,arc-timer" -- interrupts : single Interrupt going into parent intc - (16 for ARCHS cores, 3 for ARC700 cores) -- clocks : phandle to the source clock - -Example: - - timer0 { - compatible = "snps,arc-timer"; - interrupts = <3>; - interrupt-parent = <&core_intc>; - clocks = <&core_clk>; - }; - - timer1 { - compatible = "snps,arc-timer"; - clocks = <&core_clk>; - }; diff --git a/Documentation/devicetree/bindings/timer/snps,arc-timer.yaml b/Documentation/devicetree/bindings/timer/snps,arc-timer.yaml new file mode 100644 index 0000000000000..0d1e37db6f8e3 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/snps,arc-timer.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/snps,arc-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys ARC Local Timer + +maintainers: + - Vineet Gupta + +description: > + Synopsys ARC Local Timer with Interrupt Capabilities + + - Found on all ARC CPUs (ARC700/ARCHS) + - Can be optionally programmed to interrupt on Limit + - Two identical copies TIMER0 and TIMER1 exist in ARC cores and historically + TIMER0 used as clockevent provider (true for all ARC cores) + TIMER1 used for clocksource (mandatory for ARC700, optional for ARC HS) + +properties: + compatible: + const: snps,arc-timer + + interrupts: + maxItems: 1 + description: A single timer interrupt going into the parent interrupt controller. + Use <16> for ARCHS cores, <3> for ARC700 cores. + + clocks: + maxItems: 1 + +required: + - compatible + - clocks + +additionalProperties: false + +examples: + - | + timer0 { + compatible = "snps,arc-timer"; + interrupts = <3>; + clocks = <&core_clk>; + }; diff --git a/Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt b/Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt deleted file mode 100644 index b6cd1b3922ded..0000000000000 --- a/Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt +++ /dev/null @@ -1,14 +0,0 @@ -Synopsys ARC Free Running 64-bit Global Timer for ARC HS CPUs -- clocksource provider for SMP SoC - -Required properties: - -- compatible : should be "snps,archs-gfrc" -- clocks : phandle to the source clock - -Example: - - gfrc { - compatible = "snps,archs-gfrc"; - clocks = <&core_clk>; - }; diff --git a/Documentation/devicetree/bindings/timer/snps,archs-gfrc.yaml b/Documentation/devicetree/bindings/timer/snps,archs-gfrc.yaml new file mode 100644 index 0000000000000..fb16f4aba1c58 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/snps,archs-gfrc.yaml @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/snps,archs-gfrc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys ARC Free Running 64-bit Global Timer for ARC HS CPUs + +maintainers: + - Vineet Gupta + +properties: + compatible: + const: snps,archs-gfrc + + clocks: + maxItems: 1 + +required: + - compatible + - clocks + +additionalProperties: false + +examples: + - | + timer { + compatible = "snps,archs-gfrc"; + clocks = <&core_clk>; + }; diff --git a/Documentation/devicetree/bindings/timer/snps,archs-rtc.txt b/Documentation/devicetree/bindings/timer/snps,archs-rtc.txt deleted file mode 100644 index 47bd7a702f3f6..0000000000000 --- a/Documentation/devicetree/bindings/timer/snps,archs-rtc.txt +++ /dev/null @@ -1,14 +0,0 @@ -Synopsys ARC Free Running 64-bit Local Timer for ARC HS CPUs -- clocksource provider for UP SoC - -Required properties: - -- compatible : should be "snps,archs-rtc" -- clocks : phandle to the source clock - -Example: - - rtc { - compatible = "snps,arc-rtc"; - clocks = <&core_clk>; - }; diff --git a/Documentation/devicetree/bindings/timer/snps,archs-rtc.yaml b/Documentation/devicetree/bindings/timer/snps,archs-rtc.yaml new file mode 100644 index 0000000000000..7478810eb24a1 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/snps,archs-rtc.yaml @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/snps,archs-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys ARC Free Running 64-bit Local Timer for ARC HS CPUs + +maintainers: + - Vineet Gupta + +properties: + compatible: + const: snps,archs-rtc + + clocks: + maxItems: 1 + +required: + - compatible + - clocks + +additionalProperties: false + +examples: + - | + rtc { + compatible = "snps,archs-rtc"; + clocks = <&core_clk>; + }; diff --git a/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt deleted file mode 100644 index ac44c4b67530b..0000000000000 --- a/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt +++ /dev/null @@ -1,17 +0,0 @@ -Milbeaut SoCs Timer Controller - -Required properties: - -- compatible : should be "socionext,milbeaut-timer". -- reg : Specifies base physical address and size of the registers. -- interrupts : The interrupt of the first timer. -- clocks: phandle to the input clk. - -Example: - -timer { - compatible = "socionext,milbeaut-timer"; - reg = <0x1e000050 0x20> - interrupts = <0 91 4>; - clocks = <&clk 4>; -}; diff --git a/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.yaml b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.yaml new file mode 100644 index 0000000000000..9ab72b762314b --- /dev/null +++ b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/socionext,milbeaut-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Milbeaut SoCs Timer Controller + +maintainers: + - Sugaya Taichi + +properties: + compatible: + const: socionext,milbeaut-timer + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + timer@1e000050 { + compatible = "socionext,milbeaut-timer"; + reg = <0x1e000050 0x20>; + interrupts = <0 91 4>; + clocks = <&clk 4>; + }; diff --git a/Documentation/devicetree/bindings/timer/st,spear-timer.txt b/Documentation/devicetree/bindings/timer/st,spear-timer.txt deleted file mode 100644 index b5238a07da171..0000000000000 --- a/Documentation/devicetree/bindings/timer/st,spear-timer.txt +++ /dev/null @@ -1,16 +0,0 @@ -* SPEAr ARM Timer - -** Timer node required properties: - -- compatible : Should be: - "st,spear-timer" -- reg: Address range of the timer registers -- interrupt: Should contain the timer interrupt number - -Example: - - timer@f0000000 { - compatible = "st,spear-timer"; - reg = <0xf0000000 0x400>; - interrupts = <2>; - }; diff --git a/Documentation/devicetree/bindings/timer/st,spear-timer.yaml b/Documentation/devicetree/bindings/timer/st,spear-timer.yaml new file mode 100644 index 0000000000000..9f26b5f2b38a5 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/st,spear-timer.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/st,spear-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SPEAr ARM Timer + +maintainers: + - Viresh Kumar + - Shiraz Hashim + +properties: + compatible: + const: st,spear-timer + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + timer@f0000000 { + compatible = "st,spear-timer"; + reg = <0xf0000000 0x400>; + interrupts = <2>; + }; diff --git a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml index 2e92bcdeb423a..4ed30efe40525 100644 --- a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml +++ b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml @@ -14,6 +14,7 @@ properties: items: - enum: - sophgo,sg2042-aclint-mtimer + - sophgo,sg2044-aclint-mtimer - const: thead,c900-aclint-mtimer reg: diff --git a/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt b/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt deleted file mode 100644 index d3905a5412b86..0000000000000 --- a/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt +++ /dev/null @@ -1,29 +0,0 @@ -* Device tree bindings for Texas instruments Keystone timer - -This document provides bindings for the 64-bit timer in the KeyStone -architecture devices. The timer can be configured as a general-purpose 64-bit -timer, dual general-purpose 32-bit timers. When configured as dual 32-bit -timers, each half can operate in conjunction (chain mode) or independently -(unchained mode) of each other. - -It is global timer is a free running up-counter and can generate interrupt -when the counter reaches preset counter values. - -Documentation: -https://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf - -Required properties: - -- compatible : should be "ti,keystone-timer". -- reg : specifies base physical address and count of the registers. -- interrupts : interrupt generated by the timer. -- clocks : the clock feeding the timer clock. - -Example: - -timer@22f0000 { - compatible = "ti,keystone-timer"; - reg = <0x022f0000 0x80>; - interrupts = ; - clocks = <&clktimer15>; -}; diff --git a/Documentation/devicetree/bindings/timer/ti,keystone-timer.yaml b/Documentation/devicetree/bindings/timer/ti,keystone-timer.yaml new file mode 100644 index 0000000000000..1caf5ce64f016 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/ti,keystone-timer.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ti,keystone-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI Keystone timer + +maintainers: + - Alexander A. Klimov + - Ivan Khoronzhuk + +description: > + A 64-bit timer in the KeyStone architecture devices. The timer can be + configured as a general-purpose 64-bit timer, dual general-purpose 32-bit + timers. When configured as dual 32-bit timers, each half can operate in + conjunction (chain mode) or independently (unchained mode) of each other. + + It is global timer is a free running up-counter and can generate interrupt + when the counter reaches preset counter values. + + Documentation: + https://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf + +properties: + compatible: + const: ti,keystone-timer + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-names: + items: + - const: irq + + clocks: + maxItems: 1 + + clock-names: + items: + - const: timer + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include + + timer@22f0000 { + compatible = "ti,keystone-timer"; + reg = <0x022f0000 0x80>; + interrupts = <110 IRQ_TYPE_EDGE_RISING>; + clocks = <&clktimer15>; + }; diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index 8da408107e554..6a49e8efc0f71 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -173,6 +173,8 @@ properties: - maxim,ds3502 # Temperature Sensor, I2C interface - maxim,max1619 + # Digital temperature sensor with 0.1°C accuracy + - maxim,max30208 # 3-Channel Remote Temperature Sensor - maxim,max31730 # 10-bit 10 kOhm linear programmable voltage divider @@ -343,6 +345,8 @@ properties: - sensortek,stk8ba50 # SGX Sensortech VZ89X Sensors - sgx,vz89x + # SGX Sensortech VZ89TE Sensors + - sgx,vz89te # Silicon Labs EM3581 Zigbee SoC with SPI interface - silabs,em3581 # Silicon Labs SI3210 Programmable CMOS SLIC/CODEC with SPI interface diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml index a03fff5df5ef2..6c6043d9809e1 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -43,6 +43,7 @@ properties: - qcom,sm8450-ufshc - qcom,sm8550-ufshc - qcom,sm8650-ufshc + - qcom,sm8750-ufshc - const: qcom,ufshc - const: jedec,ufs-2.0 @@ -158,6 +159,7 @@ allOf: - qcom,sm8450-ufshc - qcom,sm8550-ufshc - qcom,sm8650-ufshc + - qcom,sm8750-ufshc then: properties: clocks: diff --git a/Documentation/devicetree/bindings/usb/cypress,hx3.yaml b/Documentation/devicetree/bindings/usb/cypress,hx3.yaml index 1033b7a4b8f95..d6eac1213228d 100644 --- a/Documentation/devicetree/bindings/usb/cypress,hx3.yaml +++ b/Documentation/devicetree/bindings/usb/cypress,hx3.yaml @@ -14,9 +14,22 @@ allOf: properties: compatible: - enum: - - usb4b4,6504 - - usb4b4,6506 + oneOf: + - enum: + - usb4b4,6504 + - usb4b4,6506 + - items: + - enum: + - usb4b4,6500 + - usb4b4,6508 + - const: usb4b4,6504 + - items: + - enum: + - usb4b4,6502 + - usb4b4,6503 + - usb4b4,6507 + - usb4b4,650a + - const: usb4b4,6506 reg: true diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml index 379dacacb5268..36f5c644d9590 100644 --- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml +++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml @@ -26,6 +26,8 @@ properties: ranges: true + dma-coherent: true + power-domains: description: specifies a phandle to PM domain provider node maxItems: 1 diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 86f6a19b28ae2..c01adbaacbbbc 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -129,6 +129,8 @@ patternProperties: description: Andes Technology Corporation "^anvo,.*": description: Anvo-Systems Dresden GmbH + "^aoly,.*": + description: Shenzhen Aoly Technology Co., Ltd. "^aosong,.*": description: Guangzhou Aosong Electronic Co., Ltd. "^apm,.*": @@ -432,6 +434,8 @@ patternProperties: description: EBV Elektronik "^eckelmann,.*": description: Eckelmann AG + "^econet,.*": + description: EcoNet (HK) Limited "^edgeble,.*": description: Edgeble AI Technologies Pvt. Ltd. "^edimax,.*": @@ -864,6 +868,8 @@ patternProperties: description: Linux-specific binding "^linx,.*": description: Linx Technologies + "^liontron,.*": + description: Shenzhen Liontron Technology Co., Ltd "^liteon,.*": description: LITE-ON Technology Corp. "^litex,.*": @@ -1158,6 +1164,8 @@ patternProperties: description: Parallax Inc. "^pda,.*": description: Precision Design Associates, Inc. + "^pegatron,.*": + description: Pegatron Corporation "^pericom,.*": description: Pericom Technology Inc. "^pervasive,.*": @@ -1262,6 +1270,8 @@ patternProperties: description: Renesas Electronics Corporation "^rervision,.*": description: Shenzhen Rervision Technology Co., Ltd. + "^retronix,.*": + description: Retronix Technology Inc. "^revotics,.*": description: Revolution Robotics, Inc. (Revotics) "^rex,.*": @@ -1494,6 +1504,8 @@ patternProperties: description: Toby Churchill Ltd. "^tcs,.*": description: Shenzhen City Tang Cheng Technology Co., Ltd. + "^tcu,.*": + description: TC Unterhaltungselektronik AG "^tdo,.*": description: Shangai Top Display Optoelectronics Co., Ltd "^team-source-display,.*": @@ -1607,6 +1619,8 @@ patternProperties: description: Universal Scientific Industrial Co., Ltd. "^usr,.*": description: U.S. Robotics Corporation + "^ultratronik,.*": + description: Ultratronik GmbH "^utoo,.*": description: Aigo Digital Technology Co., Ltd. "^v3,.*": @@ -1749,6 +1763,8 @@ patternProperties: description: Y Soft Corporation a.s. "^yuridenki,.*": description: Yuridenki-Shokai Co. Ltd. + "^yuzukihd,.*": + description: YuzukiHD Open Source Hardware "^zarlink,.*": description: Zarlink Semiconductor "^zealz,.*": diff --git a/Documentation/devicetree/bindings/virtio/pci-iommu.yaml b/Documentation/devicetree/bindings/virtio/pci-iommu.yaml index 972a785a42de5..8bd6ad72ac7ab 100644 --- a/Documentation/devicetree/bindings/virtio/pci-iommu.yaml +++ b/Documentation/devicetree/bindings/virtio/pci-iommu.yaml @@ -20,6 +20,9 @@ description: | virtio-iommu node doesn't have an "iommus" property, and is omitted from the iommu-map property of the root complex. +allOf: + - $ref: /schemas/pci/pci-device.yaml# + properties: # If compatible is present, it should contain the vendor and device ID # according to the PCI Bus Binding specification. Since PCI provides @@ -33,12 +36,7 @@ properties: - const: pci1af4,1057 reg: - description: | - PCI address of the IOMMU. As defined in the PCI Bus Binding - reference, the reg property is a five-cell address encoded as (phys.hi - phys.mid phys.lo size.hi size.lo). phys.hi should contain the device's - BDF as 0b00000000 bbbbbbbb dddddfff 00000000. The other cells should be - zero. See Documentation/devicetree/bindings/pci/pci.txt + maxItems: 1 '#iommu-cells': const: 1 diff --git a/Documentation/devicetree/bindings/watchdog/fsl,scu-wdt.yaml b/Documentation/devicetree/bindings/watchdog/fsl,scu-wdt.yaml index 8b7aa922249bd..1d9f15ec66579 100644 --- a/Documentation/devicetree/bindings/watchdog/fsl,scu-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/fsl,scu-wdt.yaml @@ -20,6 +20,7 @@ properties: items: - enum: - fsl,imx8dxl-sc-wdt + - fsl,imx8qm-sc-wdt - fsl,imx8qxp-sc-wdt - const: fsl,imx-sc-wdt diff --git a/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml b/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml index 0da953cb71272..8a6c3a75a5478 100644 --- a/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml @@ -35,6 +35,7 @@ properties: - fsl,imx8mp-wdt - fsl,imx8mq-wdt - fsl,ls1012a-wdt + - fsl,ls1021a-wdt - fsl,ls1043a-wdt - fsl,vf610-wdt - const: fsl,imx21-wdt @@ -102,6 +103,7 @@ allOf: contains: enum: - fsl,ls1012a-wdt + - fsl,ls1021a-wdt - fsl,ls1043a-wdt then: properties: diff --git a/Documentation/devicetree/bindings/watchdog/nxp,s32g2-swt.yaml b/Documentation/devicetree/bindings/watchdog/nxp,s32g2-swt.yaml new file mode 100644 index 0000000000000..8f168a05b50c9 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/nxp,s32g2-swt.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/nxp,s32g2-swt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP Software Watchdog Timer (SWT) + +maintainers: + - Daniel Lezcano + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + oneOf: + - const: nxp,s32g2-swt + - items: + - const: nxp,s32g3-swt + - const: nxp,s32g2-swt + + reg: + maxItems: 1 + + clocks: + items: + - description: Counter clock + - description: Module clock + - description: Register clock + + clock-names: + items: + - const: counter + - const: module + - const: register + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + watchdog@40100000 { + compatible = "nxp,s32g2-swt"; + reg = <0x40100000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + timeout-sec = <10>; + }; diff --git a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml index 3e0a8747a3570..78874b90c88c5 100644 --- a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml @@ -76,7 +76,9 @@ properties: - const: renesas,rcar-gen4-wdt # R-Car Gen4 - items: - - const: renesas,r9a09g047-wdt # RZ/G3E + - enum: + - renesas,r9a09g047-wdt # RZ/G3E + - renesas,r9a09g056-wdt # RZ/V2N - const: renesas,r9a09g057-wdt # RZ/V2H(P) - const: renesas,r9a09g057-wdt # RZ/V2H(P) diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml index d175ae9683366..53fc64f5b56d3 100644 --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml @@ -25,6 +25,7 @@ properties: - samsung,exynos5420-wdt # for Exynos5420 - samsung,exynos7-wdt # for Exynos7 - samsung,exynos850-wdt # for Exynos850 + - samsung,exynos990-wdt # for Exynos990 - samsung,exynosautov9-wdt # for Exynosautov9 - samsung,exynosautov920-wdt # for Exynosautov920 - items: @@ -49,14 +50,14 @@ properties: samsung,cluster-index: $ref: /schemas/types.yaml#/definitions/uint32 description: - Index of CPU cluster on which watchdog is running (in case of Exynos850 - or Google gs101). + Index of CPU cluster on which watchdog is running (in case of Exynos850, + Exynos990 or Google gs101). samsung,syscon-phandle: $ref: /schemas/types.yaml#/definitions/phandle description: Phandle to the PMU system controller node (in case of Exynos5250, - Exynos5420, Exynos7, Exynos850 and gs101). + Exynos5420, Exynos7, Exynos850, Exynos990 and gs101). required: - compatible @@ -77,6 +78,7 @@ allOf: - samsung,exynos5420-wdt - samsung,exynos7-wdt - samsung,exynos850-wdt + - samsung,exynos990-wdt - samsung,exynosautov9-wdt - samsung,exynosautov920-wdt then: @@ -89,6 +91,7 @@ allOf: enum: - google,gs101-wdt - samsung,exynos850-wdt + - samsung,exynos990-wdt - samsung,exynosautov9-wdt - samsung,exynosautov920-wdt then: @@ -102,7 +105,7 @@ allOf: - const: watchdog - const: watchdog_src samsung,cluster-index: - enum: [0, 1] + enum: [0, 1, 2] required: - samsung,cluster-index else: diff --git a/Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml b/Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml index 1efefd741c06d..ef088e0f6917e 100644 --- a/Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml @@ -28,6 +28,7 @@ properties: - rockchip,rk3328-wdt - rockchip,rk3368-wdt - rockchip,rk3399-wdt + - rockchip,rk3562-wdt - rockchip,rk3568-wdt - rockchip,rk3576-wdt - rockchip,rk3588-wdt diff --git a/Documentation/devicetree/bindings/writing-schema.rst b/Documentation/devicetree/bindings/writing-schema.rst index eb8ced400c7eb..fc73072f12fc5 100644 --- a/Documentation/devicetree/bindings/writing-schema.rst +++ b/Documentation/devicetree/bindings/writing-schema.rst @@ -117,9 +117,14 @@ additionalProperties / unevaluatedProperties should be allowed. * additionalProperties: true - Rare case, used for schemas implementing common set of properties. Such - schemas are supposed to be referenced by other schemas, which then use - 'unevaluatedProperties: false'. Typically bus or common-part schemas. + - Top-level part: + Rare case, used for schemas implementing common set of properties. Such + schemas are supposed to be referenced by other schemas, which then use + 'unevaluatedProperties: false'. Typically bus or common-part schemas. + - Nested node: + When listing only the expected compatible of the nested node and there + is an another schema matching that compatible which ends with one of + two above cases ('false'). examples Optional. A list of one or more DTS hunks implementing this binding only. diff --git a/Documentation/devicetree/overlay-notes.rst b/Documentation/devicetree/overlay-notes.rst index e139f22b363e9..35e79242af9a9 100644 --- a/Documentation/devicetree/overlay-notes.rst +++ b/Documentation/devicetree/overlay-notes.rst @@ -38,10 +38,10 @@ Lets take an example where we have a foo board with the following base tree:: }; ---- foo.dts --------------------------------------------------------------- -The overlay bar.dts, +The overlay bar.dtso, :: - ---- bar.dts - overlay target location by label ---------------------------- + ---- bar.dtso - overlay target location by label --------------------------- /dts-v1/; /plugin/; &ocp { @@ -51,7 +51,7 @@ The overlay bar.dts, ... /* various properties and child nodes */ }; }; - ---- bar.dts --------------------------------------------------------------- + ---- bar.dtso -------------------------------------------------------------- when loaded (and resolved as described in [1]) should result in foo+bar.dts:: @@ -88,9 +88,9 @@ in the base DT. In this case, the target path can be provided. The target location by label syntax is preferred because the overlay can be applied to any base DT containing the label, no matter where the label occurs in the DT. -The above bar.dts example modified to use target path syntax is:: +The above bar.dtso example modified to use target path syntax is:: - ---- bar.dts - overlay target location by explicit path -------------------- + ---- bar.dtso - overlay target location by explicit path ------------------- /dts-v1/; /plugin/; &{/ocp} { @@ -100,7 +100,7 @@ The above bar.dts example modified to use target path syntax is:: ... /* various properties and child nodes */ } }; - ---- bar.dts --------------------------------------------------------------- + ---- bar.dtso -------------------------------------------------------------- Overlay in-kernel API diff --git a/Documentation/doc-guide/sphinx.rst b/Documentation/doc-guide/sphinx.rst index 8081ebfe48bc0..5a91df1051413 100644 --- a/Documentation/doc-guide/sphinx.rst +++ b/Documentation/doc-guide/sphinx.rst @@ -28,7 +28,7 @@ Sphinx Install ============== The ReST markups currently used by the Documentation/ files are meant to be -built with ``Sphinx`` version 2.4.4 or higher. +built with ``Sphinx`` version 3.4.3 or higher. There's a script that checks for the Sphinx requirements. Please see :ref:`sphinx-pre-install` for further details. @@ -42,12 +42,6 @@ with your distributions. In order to do so, it is recommended to install Sphinx inside a virtual environment, using ``virtualenv-3`` or ``virtualenv``, depending on how your distribution packaged Python 3. -.. note:: - - #) It is recommended to use the RTD theme for html output. Depending - on the Sphinx version, it should be installed separately, - with ``pip install sphinx_rtd_theme``. - In summary, if you want to install the latest version of Sphinx, you should do:: @@ -162,6 +156,12 @@ By default, the "Alabaster" theme is used to build the HTML documentation; this theme is bundled with Sphinx and need not be installed separately. The Sphinx theme can be overridden by using the ``DOCS_THEME`` make variable. +.. note:: + + Some people might prefer to use the RTD theme for html output. + Depending on the Sphinx version, it should be installed separately, + with ``pip install sphinx_rtd_theme``. + There is another make variable ``SPHINXDIRS``, which is useful when test building a subset of documentation. For example, you can build documents under ``Documentation/doc-guide`` by running diff --git a/Documentation/driver-api/basics.rst b/Documentation/driver-api/basics.rst index d78b7c328ff7b..5e9f7aee71a75 100644 --- a/Documentation/driver-api/basics.rst +++ b/Documentation/driver-api/basics.rst @@ -108,6 +108,9 @@ Kernel objects manipulation .. kernel-doc:: lib/kobject.c :export: +.. kernel-doc:: lib/kobject_uevent.c + :export: + Kernel utility functions ------------------------ diff --git a/Documentation/driver-api/coco/index.rst b/Documentation/driver-api/coco/index.rst new file mode 100644 index 0000000000000..af9f08ca0cfd3 --- /dev/null +++ b/Documentation/driver-api/coco/index.rst @@ -0,0 +1,12 @@ +.. SPDX-License-Identifier: GPL-2.0 + +====================== +Confidential Computing +====================== + +.. toctree:: + :maxdepth: 1 + + measurement-registers + +.. only:: subproject and html diff --git a/Documentation/driver-api/coco/measurement-registers.rst b/Documentation/driver-api/coco/measurement-registers.rst new file mode 100644 index 0000000000000..962a44efa2c02 --- /dev/null +++ b/Documentation/driver-api/coco/measurement-registers.rst @@ -0,0 +1,12 @@ +.. SPDX-License-Identifier: GPL-2.0 +.. include:: + +===================== +Measurement Registers +===================== + +.. kernel-doc:: include/linux/tsm-mr.h + :internal: + +.. kernel-doc:: drivers/virt/coco/guest/tsm-mr.c + :export: diff --git a/Documentation/driver-api/dmaengine/provider.rst b/Documentation/driver-api/dmaengine/provider.rst index 3085f8b460fa5..8f0910668ca31 100644 --- a/Documentation/driver-api/dmaengine/provider.rst +++ b/Documentation/driver-api/dmaengine/provider.rst @@ -217,10 +217,12 @@ Currently, the types available are: - DMA_ASYNC_TX - - Must not be set by the device, and will be set by the framework - if needed + - The device supports asynchronous memory-to-memory operations, + including memcpy, memset, xor, pq, xor_val, and pq_val. - - TODO: What is it about? + - This capability is automatically set by the DMA engine + framework and must not be configured manually by device + drivers. - DMA_SLAVE diff --git a/Documentation/driver-api/gpio/index.rst b/Documentation/driver-api/gpio/index.rst index 34b57cee33914..43f6a3afe10b5 100644 --- a/Documentation/driver-api/gpio/index.rst +++ b/Documentation/driver-api/gpio/index.rst @@ -27,7 +27,7 @@ Core ACPI support ============ -.. kernel-doc:: drivers/gpio/gpiolib-acpi.c +.. kernel-doc:: drivers/gpio/gpiolib-acpi-core.c :export: Device tree support diff --git a/Documentation/driver-api/index.rst b/Documentation/driver-api/index.rst index 16e2c4ec3c010..3e2a270bd8282 100644 --- a/Documentation/driver-api/index.rst +++ b/Documentation/driver-api/index.rst @@ -81,6 +81,7 @@ Subsystem-specific APIs acpi/index backlight/lp855x-driver.rst clk + coco/index console crypto/index dmaengine/index diff --git a/Documentation/driver-api/ipmi.rst b/Documentation/driver-api/ipmi.rst index dfa021eacd63c..2cc6c898ab903 100644 --- a/Documentation/driver-api/ipmi.rst +++ b/Documentation/driver-api/ipmi.rst @@ -45,7 +45,7 @@ manual), choose the 'IPMI SI handler' option. A driver also exists for direct I2C access to the IPMI management controller. Some boards support this, but it is unknown if it will work on every board. For this, choose 'IPMI SMBus handler', but be ready to try to do some -figuring to see if it will work on your system if the SMBIOS/APCI +figuring to see if it will work on your system if the SMBIOS/ACPI information is wrong or not present. It is fairly safe to have both these enabled and let the drivers auto-detect what is present. @@ -63,7 +63,7 @@ situation, you need to read the section below named 'The SI Driver' or IPMI defines a standard watchdog timer. You can enable this with the 'IPMI Watchdog Timer' config option. If you compile the driver into the kernel, then via a kernel command-line option you can have the -watchdog timer start as soon as it initializes. It also have a lot +watchdog timer start as soon as it initializes. It also has a lot of other options, see the 'Watchdog' section below for more details. Note that you can also have the watchdog continue to run if it is closed (by default it is disabled on close). Go into the 'Watchdog @@ -280,10 +280,8 @@ Creating the User To use the message handler, you must first create a user using ipmi_create_user. The interface number specifies which SMI you want to connect to, and you must supply callback functions to be called -when data comes in. The callback function can run at interrupt level, -so be careful using the callbacks. This also allows to you pass in a -piece of data, the handler_data, that will be passed back to you on -all calls. +when data comes in. This also allows to you pass in a piece of data, +the handler_data, that will be passed back to you on all calls. Once you are done, call ipmi_destroy_user() to get rid of the user. @@ -303,8 +301,7 @@ use it for anything you like. Responses come back in the function pointed to by the ipmi_recv_hndl field of the "handler" that you passed in to ipmi_create_user(). -Remember again, these may be running at interrupt level. Remember to -look at the receive type, too. +Remember to look at the receive type, too. From userland, you fill out an ipmi_req_t structure and use the IPMICTL_SEND_COMMAND ioctl. For incoming stuff, you can use select() @@ -317,13 +314,13 @@ This gives the receiver a place to actually put the message. If the message cannot fit into the data you provide, you will get an EMSGSIZE error and the driver will leave the data in the receive -queue. If you want to get it and have it truncate the message, us +queue. If you want to get it and have it truncate the message, use the IPMICTL_RECEIVE_MSG_TRUNC ioctl. When you send a command (which is defined by the lowest-order bit of the netfn per the IPMI spec) on the IPMB bus, the driver will automatically assign the sequence number to the command and save the -command. If the response is not receive in the IPMI-specified 5 +command. If the response is not received in the IPMI-specified 5 seconds, it will generate a response automatically saying the command timed out. If an unsolicited response comes in (if it was after 5 seconds, for instance), that response will be ignored. @@ -367,7 +364,7 @@ channel bitmasks do not overlap. To respond to a received command, set the response bit in the returned netfn, use the address from the received message, and use the same -msgid that you got in the receive message. +msgid that you got in the received message. From userland, equivalent IOCTLs are provided to do these functions. @@ -440,7 +437,7 @@ register would be 0xca6. This defaults to 1. The regsizes parameter gives the size of a register, in bytes. The data used by IPMI is 8-bits wide, but it may be inside a larger -register. This parameter allows the read and write type to specified. +register. This parameter allows the read and write type to be specified. It may be 1, 2, 4, or 8. The default is 1. Since the register size may be larger than 32 bits, the IPMI data may not @@ -481,8 +478,8 @@ If your IPMI interface does not support interrupts and is a KCS or SMIC interface, the IPMI driver will start a kernel thread for the interface to help speed things up. This is a low-priority kernel thread that constantly polls the IPMI driver while an IPMI operation -is in progress. The force_kipmid module parameter will all the user to -force this thread on or off. If you force it off and don't have +is in progress. The force_kipmid module parameter will allow the user +to force this thread on or off. If you force it off and don't have interrupts, the driver will run VERY slowly. Don't blame me, these interfaces suck. @@ -583,7 +580,7 @@ kernel command line as:: These are the same options as on the module command line. The I2C driver does not support non-blocking access or polling, so -this driver cannod to IPMI panic events, extend the watchdog at panic +this driver cannot do IPMI panic events, extend the watchdog at panic time, or other panic-related IPMI functions without special kernel patches and driver modifications. You can get those at the openipmi web page. @@ -610,7 +607,7 @@ Parameters are:: ipmi_ipmb.retry_time_ms=