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Merge remote-tracking branch 'torvalds/master' into perf-tools
To pick up some extra files that need to be sync'ed with the kernel sources to try and reduce the number of PRs. Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2 parents 563d399 + 04a9f17 commit f8e478e

53 files changed

Lines changed: 235 additions & 139 deletions

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.mailmap

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@@ -327,6 +327,7 @@ Henrik Rydberg <[email protected]>
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Herbert Xu <[email protected]>
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Documentation/dev-tools/kunit/run_wrapper.rst

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@@ -336,6 +336,8 @@ command line arguments:
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- ``--list_tests_attr``: If set, lists all tests that will be run and all of their
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attributes.
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- ``--list_suites``: If set, lists all suites that will be run.
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Command-line completion
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==============================
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MAINTAINERS

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@@ -4022,7 +4022,7 @@ F: drivers/hwmon/asus_wmi_sensors.c
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ASYMMETRIC KEYS
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M: David Howells <[email protected]>
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M: Lukas Wunner <[email protected]>
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M: Ignat Korchagin <ignat@cloudflare.com>
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M: Ignat Korchagin <ignat@linux.win>
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S: Maintained
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ASYMMETRIC KEYS - ECDSA
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M: Lukas Wunner <[email protected]>
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M: Ignat Korchagin <ignat@cloudflare.com>
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M: Ignat Korchagin <ignat@linux.win>
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R: Stefan Berger <[email protected]>
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S: Maintained
@@ -4045,14 +4045,14 @@ F: include/crypto/ecc*
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ASYMMETRIC KEYS - GOST
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M: Lukas Wunner <[email protected]>
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M: Ignat Korchagin <ignat@cloudflare.com>
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M: Ignat Korchagin <ignat@linux.win>
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S: Odd fixes
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F: crypto/ecrdsa*
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ASYMMETRIC KEYS - RSA
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M: Lukas Wunner <[email protected]>
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M: Ignat Korchagin <ignat@cloudflare.com>
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M: Ignat Korchagin <ignat@linux.win>
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S: Maintained
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F: crypto/rsa*

arch/arm/configs/multi_v7_defconfig

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@@ -279,7 +279,6 @@ CONFIG_TI_CPSW_SWITCHDEV=y
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CONFIG_TI_CPTS=y
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CONFIG_TI_KEYSTONE_NETCP=y
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CONFIG_TI_KEYSTONE_NETCP_ETHSS=y
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CONFIG_TI_PRUSS=m
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CONFIG_TI_PRUETH=m
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CONFIG_XILINX_EMACLITE=y
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CONFIG_SFP=m

arch/arm64/boot/dts/renesas/r8a78000.dtsi

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@@ -698,7 +698,7 @@
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compatible = "renesas,scif-r8a78000",
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"renesas,rcar-gen5-scif", "renesas,scif";
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reg = <0 0xc0700000 0 0x40>;
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interrupts = <GIC_SPI 4074 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_ESPI 10 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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status = "disabled";
@@ -708,7 +708,7 @@
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compatible = "renesas,scif-r8a78000",
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"renesas,rcar-gen5-scif", "renesas,scif";
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reg = <0 0xc0704000 0 0x40>;
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interrupts = <GIC_SPI 4075 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_ESPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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status = "disabled";
@@ -718,7 +718,7 @@
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compatible = "renesas,scif-r8a78000",
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"renesas,rcar-gen5-scif", "renesas,scif";
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reg = <0 0xc0708000 0 0x40>;
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interrupts = <GIC_SPI 4076 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_ESPI 12 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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status = "disabled";
@@ -728,7 +728,7 @@
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compatible = "renesas,scif-r8a78000",
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"renesas,rcar-gen5-scif", "renesas,scif";
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reg = <0 0xc070c000 0 0x40>;
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interrupts = <GIC_SPI 4077 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_ESPI 13 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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status = "disabled";
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compatible = "renesas,hscif-r8a78000",
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"renesas,rcar-gen5-hscif", "renesas,hscif";
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reg = <0 0xc0710000 0 0x60>;
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interrupts = <GIC_SPI 4078 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_ESPI 14 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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status = "disabled";
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compatible = "renesas,hscif-r8a78000",
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"renesas,rcar-gen5-hscif", "renesas,hscif";
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reg = <0 0xc0714000 0 0x60>;
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interrupts = <GIC_SPI 4079 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_ESPI 15 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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status = "disabled";
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compatible = "renesas,hscif-r8a78000",
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"renesas,rcar-gen5-hscif", "renesas,hscif";
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reg = <0 0xc0718000 0 0x60>;
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interrupts = <GIC_SPI 4080 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_ESPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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status = "disabled";
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compatible = "renesas,hscif-r8a78000",
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"renesas,rcar-gen5-hscif", "renesas,hscif";
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reg = <0 0xc071c000 0 0x60>;
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interrupts = <GIC_SPI 4081 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_ESPI 17 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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status = "disabled";

arch/arm64/boot/dts/renesas/r9a09g057.dtsi

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@@ -581,16 +581,6 @@
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status = "disabled";
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};
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584-
wdt0: watchdog@11c00400 {
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compatible = "renesas,r9a09g057-wdt";
586-
reg = <0 0x11c00400 0 0x400>;
587-
clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>;
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clock-names = "pclk", "oscclk";
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resets = <&cpg 0x75>;
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power-domains = <&cpg>;
591-
status = "disabled";
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};
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wdt1: watchdog@14400000 {
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compatible = "renesas,r9a09g057-wdt";
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reg = <0 0x14400000 0 0x400>;
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status = "disabled";
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};
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604-
wdt2: watchdog@13000000 {
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compatible = "renesas,r9a09g057-wdt";
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reg = <0 0x13000000 0 0x400>;
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clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>;
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clock-names = "pclk", "oscclk";
609-
resets = <&cpg 0x77>;
610-
power-domains = <&cpg>;
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status = "disabled";
612-
};
613-
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wdt3: watchdog@13000400 {
615-
compatible = "renesas,r9a09g057-wdt";
616-
reg = <0 0x13000400 0 0x400>;
617-
clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>;
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clock-names = "pclk", "oscclk";
619-
resets = <&cpg 0x78>;
620-
power-domains = <&cpg>;
621-
status = "disabled";
622-
};
623-
624594
rtc: rtc@11c00800 {
625595
compatible = "renesas,r9a09g057-rtca3", "renesas,rz-rtca3";
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reg = <0 0x11c00800 0 0x400>;

arch/arm64/boot/dts/renesas/r9a09g077.dtsi

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@@ -974,8 +974,8 @@
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cpg: clock-controller@80280000 {
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compatible = "renesas,r9a09g077-cpg-mssr";
977-
reg = <0 0x80280000 0 0x1000>,
978-
<0 0x81280000 0 0x9000>;
977+
reg = <0 0x80280000 0 0x10000>,
978+
<0 0x81280000 0 0x10000>;
979979
clocks = <&extal_clk>;
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clock-names = "extal";
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#clock-cells = <2>;

arch/arm64/boot/dts/renesas/r9a09g087.dtsi

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@@ -977,8 +977,8 @@
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cpg: clock-controller@80280000 {
979979
compatible = "renesas,r9a09g087-cpg-mssr";
980-
reg = <0 0x80280000 0 0x1000>,
981-
<0 0x81280000 0 0x9000>;
980+
reg = <0 0x80280000 0 0x10000>,
981+
<0 0x81280000 0 0x10000>;
982982
clocks = <&extal_clk>;
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clock-names = "extal";
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#clock-cells = <2>;

arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi

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@@ -162,7 +162,7 @@
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<100000000>;
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renesas,settings = [
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80 00 11 19 4c 42 dc 2f 06 7d 20 1a 5f 1e f2 27
165-
00 40 00 00 00 00 00 00 06 0c 19 02 3f f0 90 86
165+
00 40 00 00 00 00 00 00 06 0c 19 02 3b f0 90 86
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a0 80 30 30 9c
167167
];
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};

arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi

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regulator-max-microvolt = <3300000>;
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gpios-states = <0>;
5555
states = <3300000 0>, <1800000 1>;
56+
regulator-ramp-delay = <60>;
5657
};
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#endif
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