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Merge tag 'mips_6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS updates from Thomas Bogendoerfer: - DT updates for ralink, mobileye and atheros/qualcomm - Clean up of mc146818 usage - Speed up delay calibration for CPS - Other cleanups and fixes * tag 'mips_6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (50 commits) MIPS: Don't use %pK through printk MIPS: Update Joshua Kinard's e-mail address MIPS: mobileye: dts: eyeq5,eyeq6h: rename the emmc controller MIPS: mm: tlb-r4k: Uniquify TLB entries on init MIPS: SGI-IP27: Delete an unnecessary check before kfree() in hub_domain_free() mips/malta,loongson2ef: use generic mc146818_get_time function mips: remove redundant macro mc146818_decode_year mips/mach-rm: remove custom mc146818rtc.h file mips: remove unused function mc146818_set_rtc_mmss MIPS: CPS: Optimise delay CPU calibration for SMP MIPS: CPS: Improve mips_cps_first_online_in_cluster() MIPS: disable MMID when not supported by the hardware MIPS: eyeq5_defconfig: add I2C subsystem, driver and temp sensor driver MIPS: eyeq5_defconfig: add GPIO subsystem & driver MIPS: mobileye: eyeq5: add two GPIO bank nodes MIPS: mobileye: eyeq5: add evaluation board I2C temp sensor MIPS: mobileye: eyeq5: add 5 I2C controller nodes MIPS: eyeq5_defconfig: Update for v6.16-rc1 MIPS: vpe-mt: add missing prototypes for vpe_{alloc,start,stop,free} mips: boot: use 'targets' instead of extra-y in Makefile ...
2 parents 5ae8021 + 3ebcbf0 commit f1aa129

63 files changed

Lines changed: 570 additions & 248 deletions

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‎Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -26,18 +26,22 @@ description: |
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properties:
2828
compatible:
29-
items:
30-
- enum:
31-
- ralink,mt7620-sysc
32-
- ralink,mt7628-sysc
33-
- ralink,mt7688-sysc
34-
- ralink,rt2880-sysc
35-
- ralink,rt3050-sysc
36-
- ralink,rt3052-sysc
37-
- ralink,rt3352-sysc
38-
- ralink,rt3883-sysc
39-
- ralink,rt5350-sysc
40-
- const: syscon
29+
oneOf:
30+
- items:
31+
- enum:
32+
- ralink,mt7620-sysc
33+
- ralink,mt7688-sysc
34+
- ralink,rt2880-sysc
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- ralink,rt3050-sysc
36+
- ralink,rt3052-sysc
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- ralink,rt3352-sysc
38+
- ralink,rt3883-sysc
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- ralink,rt5350-sysc
40+
- const: syscon
41+
- items:
42+
- const: ralink,mt7628-sysc
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- const: ralink,mt7688-sysc
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- const: syscon
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reg:
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maxItems: 1

‎arch/mips/Kconfig‎

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Original file line numberDiff line numberDiff line change
@@ -562,6 +562,7 @@ config MIPS_MALTA
562562
select MIPS_L1_CACHE_SHIFT_6
563563
select MIPS_MSC
564564
select PCI_GT64XXX_PCI0
565+
select RTC_MC146818_LIB
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select SMP_UP if SMP
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select SWAP_IO_SPACE
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select SYS_HAS_CPU_MIPS32_R1
@@ -1836,6 +1837,7 @@ config CPU_LOONGSON2EF
18361837
select CPU_SUPPORTS_64BIT_KERNEL
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select CPU_SUPPORTS_HIGHMEM
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select CPU_SUPPORTS_HUGEPAGES
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select RTC_MC146818_LIB
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18401842
config CPU_LOONGSON32
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bool

‎arch/mips/boot/Makefile‎

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@@ -54,10 +54,10 @@ UIMAGE_ENTRYADDR = $(VMLINUX_ENTRY_ADDRESS)
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# Compressed vmlinux images
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#
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57-
extra-y += vmlinux.bin.bz2
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extra-y += vmlinux.bin.gz
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extra-y += vmlinux.bin.lzma
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extra-y += vmlinux.bin.lzo
57+
targets += vmlinux.bin.bz2
58+
targets += vmlinux.bin.gz
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targets += vmlinux.bin.lzma
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targets += vmlinux.bin.lzo
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$(obj)/vmlinux.bin.bz2: $(obj)/vmlinux.bin FORCE
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$(call if_changed,bzip2)

‎arch/mips/boot/dts/mobileye/eyeq5-epm5.dts‎

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Original file line numberDiff line numberDiff line change
@@ -21,3 +21,11 @@
2121
<0x8 0x02000000 0x0 0x7E000000>;
2222
};
2323
};
24+
25+
&i2c2 {
26+
temperature-sensor@48 {
27+
compatible = "ti,tmp112";
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reg = <0x48>;
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label = "U60";
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};
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};

‎arch/mips/boot/dts/mobileye/eyeq5.dtsi‎

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Original file line numberDiff line numberDiff line change
@@ -110,6 +110,81 @@
110110
ranges;
111111
compatible = "simple-bus";
112112

113+
i2c0: i2c@300000 {
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compatible = "mobileye,eyeq5-i2c", "arm,primecell";
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reg = <0 0x300000 0x0 0x1000>;
116+
interrupt-parent = <&gic>;
117+
interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>;
118+
clock-frequency = <400000>; /* Fast mode */
119+
#address-cells = <1>;
120+
#size-cells = <0>;
121+
clocks = <&olb 35>, <&olb EQ5C_PER_I2C>;
122+
clock-names = "i2cclk", "apb_pclk";
123+
resets = <&olb 0 13>;
124+
i2c-transfer-timeout-us = <10000>;
125+
mobileye,olb = <&olb 0>;
126+
};
127+
128+
i2c1: i2c@400000 {
129+
compatible = "mobileye,eyeq5-i2c", "arm,primecell";
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reg = <0 0x400000 0x0 0x1000>;
131+
interrupt-parent = <&gic>;
132+
interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>;
133+
clock-frequency = <400000>; /* Fast mode */
134+
#address-cells = <1>;
135+
#size-cells = <0>;
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clocks = <&olb 35>, <&olb EQ5C_PER_I2C>;
137+
clock-names = "i2cclk", "apb_pclk";
138+
resets = <&olb 0 14>;
139+
i2c-transfer-timeout-us = <10000>;
140+
mobileye,olb = <&olb 1>;
141+
};
142+
143+
i2c2: i2c@500000 {
144+
compatible = "mobileye,eyeq5-i2c", "arm,primecell";
145+
reg = <0 0x500000 0x0 0x1000>;
146+
interrupt-parent = <&gic>;
147+
interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
148+
clock-frequency = <400000>; /* Fast mode */
149+
#address-cells = <1>;
150+
#size-cells = <0>;
151+
clocks = <&olb 35>, <&olb EQ5C_PER_I2C>;
152+
clock-names = "i2cclk", "apb_pclk";
153+
resets = <&olb 0 15>;
154+
i2c-transfer-timeout-us = <10000>;
155+
mobileye,olb = <&olb 2>;
156+
};
157+
158+
i2c3: i2c@600000 {
159+
compatible = "mobileye,eyeq5-i2c", "arm,primecell";
160+
reg = <0 0x600000 0x0 0x1000>;
161+
interrupt-parent = <&gic>;
162+
interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
163+
clock-frequency = <400000>; /* Fast mode */
164+
#address-cells = <1>;
165+
#size-cells = <0>;
166+
clocks = <&olb 35>, <&olb EQ5C_PER_I2C>;
167+
clock-names = "i2cclk", "apb_pclk";
168+
resets = <&olb 0 16>;
169+
i2c-transfer-timeout-us = <10000>;
170+
mobileye,olb = <&olb 3>;
171+
};
172+
173+
i2c4: i2c@700000 {
174+
compatible = "mobileye,eyeq5-i2c", "arm,primecell";
175+
reg = <0 0x700000 0x0 0x1000>;
176+
interrupt-parent = <&gic>;
177+
interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
178+
clock-frequency = <400000>; /* Fast mode */
179+
#address-cells = <1>;
180+
#size-cells = <0>;
181+
clocks = <&olb 35>, <&olb EQ5C_PER_I2C>;
182+
clock-names = "i2cclk", "apb_pclk";
183+
resets = <&olb 0 17>;
184+
i2c-transfer-timeout-us = <10000>;
185+
mobileye,olb = <&olb 4>;
186+
};
187+
113188
uart0: serial@800000 {
114189
compatible = "arm,pl011", "arm,primecell";
115190
reg = <0 0x800000 0x0 0x1000>;
@@ -178,6 +253,58 @@
178253
clocks = <&olb EQ5C_CPU_CORE0>;
179254
};
180255
};
256+
257+
emmc: mmc@2200000 {
258+
compatible = "mobileye,eyeq-sd4hc", "cdns,sd4hc";
259+
reg = <0 0x2200000 0x0 0x1000>;
260+
interrupt-parent = <&gic>;
261+
interrupts = <GIC_SHARED 10 IRQ_TYPE_LEVEL_HIGH>;
262+
clocks = <&olb EQ5C_PER_EMMC>;
263+
bus-width = <8>;
264+
max-frequency = <200000000>;
265+
mmc-ddr-1_8v;
266+
sd-uhs-ddr50;
267+
mmc-hs200-1_8v;
268+
mmc-hs400-1_8v;
269+
mmc-hs400-enhanced-strobe;
270+
271+
cdns,phy-input-delay-legacy = <4>;
272+
cdns,phy-input-delay-mmc-highspeed = <2>;
273+
cdns,phy-input-delay-mmc-ddr = <3>;
274+
cdns,phy-dll-delay-sdclk = <32>;
275+
cdns,phy-dll-delay-sdclk-hsmmc = <32>;
276+
cdns,phy-dll-delay-strobe = <32>;
277+
};
278+
279+
gpio0: gpio@1400000 {
280+
compatible = "mobileye,eyeq5-gpio";
281+
reg = <0x0 0x1400000 0x0 0x1000>;
282+
gpio-bank = <0>;
283+
ngpios = <29>;
284+
interrupt-parent = <&gic>;
285+
interrupts = <GIC_SHARED 14 IRQ_TYPE_LEVEL_HIGH>;
286+
gpio-controller;
287+
#gpio-cells = <2>;
288+
gpio-ranges = <&olb 0 0 29>;
289+
interrupt-controller;
290+
#interrupt-cells = <2>;
291+
resets = <&olb 0 26>;
292+
};
293+
294+
gpio1: gpio@1500000 {
295+
compatible = "mobileye,eyeq5-gpio";
296+
reg = <0x0 0x1500000 0x0 0x1000>;
297+
gpio-bank = <1>;
298+
ngpios = <23>;
299+
interrupt-parent = <&gic>;
300+
interrupts = <GIC_SHARED 14 IRQ_TYPE_LEVEL_HIGH>;
301+
gpio-controller;
302+
#gpio-cells = <2>;
303+
gpio-ranges = <&olb 0 29 23>;
304+
interrupt-controller;
305+
#interrupt-cells = <2>;
306+
resets = <&olb 0 26>;
307+
};
181308
};
182309
};
183310

‎arch/mips/boot/dts/mobileye/eyeq6h.dtsi‎

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Original file line numberDiff line numberDiff line change
@@ -109,6 +109,28 @@
109109
clock-names = "ref";
110110
};
111111

112+
emmc: mmc@d8010000 {
113+
compatible = "mobileye,eyeq-sd4hc", "cdns,sd4hc";
114+
reg = <0 0xd8010000 0x0 0x1000>;
115+
interrupt-parent = <&gic>;
116+
interrupts = <GIC_SHARED 91 IRQ_TYPE_LEVEL_HIGH>;
117+
clocks = <&olb_south EQ6HC_SOUTH_DIV_EMMC>;
118+
bus-width = <8>;
119+
max-frequency = <200000000>;
120+
mmc-ddr-1_8v;
121+
sd-uhs-ddr50;
122+
mmc-hs200-1_8v;
123+
mmc-hs400-1_8v;
124+
mmc-hs400-enhanced-strobe;
125+
126+
cdns,phy-input-delay-legacy = <4>;
127+
cdns,phy-input-delay-mmc-highspeed = <2>;
128+
cdns,phy-input-delay-mmc-ddr = <3>;
129+
cdns,phy-dll-delay-sdclk = <32>;
130+
cdns,phy-dll-delay-sdclk-hsmmc = <32>;
131+
cdns,phy-dll-delay-strobe = <32>;
132+
};
133+
112134
olb_south: system-controller@d8013000 {
113135
compatible = "mobileye,eyeq6h-south-olb", "syscon";
114136
reg = <0x0 0xd8013000 0x0 0x1000>;

‎arch/mips/boot/dts/qca/ar9132.dtsi‎

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@@ -156,6 +156,15 @@
156156
#address-cells = <1>;
157157
#size-cells = <0>;
158158
};
159+
160+
wifi: wifi@180c0000 {
161+
compatible = "qca,ar9130-wifi";
162+
reg = <0x180c0000 0x230000>;
163+
164+
interrupts = <2>;
165+
166+
status = "disabled";
167+
};
159168
};
160169

161170
usb_phy: usb-phy {

‎arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts‎

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Original file line numberDiff line numberDiff line change
@@ -108,3 +108,7 @@
108108
};
109109
};
110110
};
111+
112+
&wifi {
113+
status = "okay";
114+
};

‎arch/mips/boot/dts/qca/ar9331.dtsi‎

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@@ -285,6 +285,15 @@
285285

286286
status = "disabled";
287287
};
288+
289+
wifi: wifi@18100000 {
290+
compatible = "qca,ar9330-wifi";
291+
reg = <0x18100000 0x20000>;
292+
293+
interrupts = <2>;
294+
295+
status = "disabled";
296+
};
288297
};
289298

290299
usb_phy: usb-phy {

‎arch/mips/boot/dts/qca/ar9331_dpt_module.dts‎

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@@ -97,3 +97,7 @@
9797
&phy_port4 {
9898
status = "okay";
9999
};
100+
101+
&wifi {
102+
status = "okay";
103+
};

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