clk: samsung: gs101: fix alternate mout_hsi0_usb20_ref parent clock

The alternate parent clock for this mux is mout_pll_usb, not the pll
itself.

Fixes: 1891e4d ("clk: samsung: gs101: add support for cmu_hsi0")
Cc: [email protected]
Signed-off-by: André Draszik <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>

Author: andred

drivers/clk/samsung/clk-gs101.c

@@ -2129,7 +2129,7 @@ PNAME(mout_hsi0_usbdpdbg_user_p)	= { "oscclk",
 					    "dout_cmu_hsi0_usbdpdbg" };
 PNAME(mout_hsi0_bus_p)			= { "mout_hsi0_bus_user",
 					    "mout_hsi0_alt_user" };
-PNAME(mout_hsi0_usb20_ref_p)		= { "fout_usb_pll",
+PNAME(mout_hsi0_usb20_ref_p)		= { "mout_pll_usb",
 					    "mout_hsi0_tcxo_user" };
 PNAME(mout_hsi0_usb31drd_p)		= { "fout_usb_pll",
 					    "mout_hsi0_usb31drd_user",