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Anshuman Khandualctmarinas
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arm64/mm: Directly use TTBRx_EL1_CnP
Replace all TTBR_CNP_BIT macro instances with TTBRx_EL1_CNP_BIT which is a standard field from tools sysreg format. Drop the now redundant custom macro TTBR_CNP_BIT. No functional change. Cc: Will Deacon <[email protected]> Cc: Marc Zyngier <[email protected]> Cc: Oliver Upton <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Signed-off-by: Anshuman Khandual <[email protected]> Signed-off-by: Catalin Marinas <[email protected]>
1 parent d989010 commit be6e9de

5 files changed

Lines changed: 6 additions & 8 deletions

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arch/arm64/include/asm/pgtable-hwdef.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -223,8 +223,6 @@
223223
*/
224224
#define S1_TABLE_AP (_AT(pmdval_t, 3) << 61)
225225

226-
#define TTBR_CNP_BIT (UL(1) << 0)
227-
228226
/*
229227
* TCR flags.
230228
*/

arch/arm64/kernel/mte.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -315,8 +315,8 @@ void mte_cpu_setup(void)
315315
* CnP is not a boot feature so MTE gets enabled before CnP, but let's
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* make sure that is the case.
317317
*/
318-
BUG_ON(read_sysreg(ttbr0_el1) & TTBR_CNP_BIT);
319-
BUG_ON(read_sysreg(ttbr1_el1) & TTBR_CNP_BIT);
318+
BUG_ON(read_sysreg(ttbr0_el1) & TTBRx_EL1_CnP);
319+
BUG_ON(read_sysreg(ttbr1_el1) & TTBRx_EL1_CnP);
320320

321321
/* Normal Tagged memory type at the corresponding MAIR index */
322322
sysreg_clear_set(mair_el1,

arch/arm64/kvm/hyp/nvhe/hyp-init.S

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -130,7 +130,7 @@ SYM_CODE_START_LOCAL(___kvm_hyp_init)
130130
ldr x1, [x0, #NVHE_INIT_PGD_PA]
131131
phys_to_ttbr x2, x1
132132
alternative_if ARM64_HAS_CNP
133-
orr x2, x2, #TTBR_CNP_BIT
133+
orr x2, x2, #TTBRx_EL1_CnP
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alternative_else_nop_endif
135135
msr ttbr0_el2, x2
136136

@@ -291,7 +291,7 @@ SYM_TYPED_FUNC_START(__pkvm_init_switch_pgd)
291291
/* Install the new pgtables */
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phys_to_ttbr x5, x0
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alternative_if ARM64_HAS_CNP
294-
orr x5, x5, #TTBR_CNP_BIT
294+
orr x5, x5, #TTBRx_EL1_CnP
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alternative_else_nop_endif
296296
msr ttbr0_el2, x5
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arch/arm64/mm/context.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -354,7 +354,7 @@ void cpu_do_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm)
354354

355355
/* Skip CNP for the reserved ASID */
356356
if (system_supports_cnp() && asid)
357-
ttbr0 |= TTBR_CNP_BIT;
357+
ttbr0 |= TTBRx_EL1_CnP;
358358

359359
/* SW PAN needs a copy of the ASID in TTBR0 for entry */
360360
if (IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN))

arch/arm64/mm/mmu.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2188,7 +2188,7 @@ void __cpu_replace_ttbr1(pgd_t *pgdp, bool cnp)
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phys_addr_t ttbr1 = phys_to_ttbr(virt_to_phys(pgdp));
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21902190
if (cnp)
2191-
ttbr1 |= TTBR_CNP_BIT;
2191+
ttbr1 |= TTBRx_EL1_CnP;
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21932193
replace_phys = (void *)__pa_symbol(idmap_cpu_replace_ttbr1);
21942194

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