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Merge tag 'at91-soc-7.1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/drivers
Microchip AT91 SoC updates for v7.1 This update includes: - device tree bindings conversion to DT schema for CHIPID, RAM controller and PIT, PIT64b, ST timers * tag 'at91-soc-7.1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/at91/linux: dt-bindings: arm: atmel,at91rm9200-sdramc: convert to DT schema dt-bindings: arm: atmel,at91rm9200-st: convert to DT schema dt-bindings: arm: microchip,sam9x60-pit64b : convert to DT schema dt-bindings: arm: atmel,at91sam9260-pit: convert to DT schema dt-bindings: arm: microchip,sama7g5-chipid : convert to DT schema Signed-off-by: Krzysztof Kozlowski <[email protected]>
2 parents d7dbdad + f3ae004 commit 98bc768

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‎Documentation/devicetree/bindings/arm/atmel,at91rm9200-sdramc.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/atmel,at91rm9200-sdramc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip (Atmel) SDRAM / DDR Controller (RAMC / DDRAMC / UDDRC)
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maintainers:
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- Nicolas Ferre <[email protected]>
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- Claudiu Beznea <[email protected]>
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description:
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The SDRAM/DDR Controller (often called RAMC or DDRAMC) in various
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Atmel/Microchip ARM9 and Cortex-A5/A7 SoCs manages external
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SDRAM / DDR memory. It is typically exposed as a syscon node for
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register access from other drivers (e.g. for initialization or mode
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configuration). No interrupts or clocks are usually required in the
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binding.
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properties:
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compatible:
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oneOf:
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- items:
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- const: atmel,at91rm9200-sdramc
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- const: syscon
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- items:
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- const: microchip,sama7d65-uddrc
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- const: microchip,sama7g5-uddrc
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- enum:
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- atmel,at91sam9260-sdramc
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- atmel,at91sam9g45-ddramc
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- atmel,sama5d3-ddramc
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- microchip,sam9x60-ddramc
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- microchip,sam9x7-ddramc
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- microchip,sama7g5-uddrc
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reg:
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maxItems: 1
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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minItems: 1
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items:
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- const: ddrck
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- const: mpddr
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required:
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- compatible
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- reg
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/at91.h>
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ramc@ffffe400 {
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compatible = "atmel,at91sam9g45-ddramc";
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reg = <0xffffe400 0x200>;
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clocks = <&pmc PMC_TYPE_SYSTEM 2>;
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clock-names = "ddrck";
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};
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...

‎Documentation/devicetree/bindings/arm/atmel,at91rm9200-st.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/atmel,at91rm9200-st.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Atmel System Timer
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maintainers:
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- Nicolas Ferre <[email protected]>
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- Claudiu Beznea <[email protected]>
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description:
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The System Timer (ST) module in AT91RM9200 provides periodic tick and
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alarm capabilities. It is exposed as a simple multi-function device
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(simple-mfd + syscon) because it shares its register space and interrupt
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with other System Controller blocks.
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properties:
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compatible:
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items:
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- const: atmel,at91rm9200-st
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- const: syscon
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- const: simple-mfd
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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patternProperties:
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"^watchdog@[0-9a-f]+$":
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$ref: /schemas/watchdog/atmel,at91rm9200-wdt.yaml#
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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timer@fffffd00 {
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compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd";
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reg = <0xfffffd00 0x100>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
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clocks = <&slow_xtal>;
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#address-cells = <1>;
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#size-cells = <1>;
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watchdog@fffffd40 {
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compatible = "atmel,at91rm9200-wdt";
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reg = <0xfffffd40 0x40>;
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};
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};
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...

‎Documentation/devicetree/bindings/arm/atmel,at91sam9260-pit.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/atmel,at91sam9260-pit.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Atmel AT91SAM9260 Periodic Interval Timer (PIT)
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maintainers:
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- Nicolas Ferre <[email protected]>
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- Claudiu Beznea <[email protected]>
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description:
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The Periodic Interval Timer (PIT) is part of the System Controller of
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various Microchip 32-bit ARM-based SoCs (formerly Atmel AT91 series).
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It is a simple down-counter timer used mainly as the kernel tick source.
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The PIT is clocked from the slow clock and shares a single IRQ line with
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other System Controller peripherals.
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properties:
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compatible:
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const: atmel,at91sam9260-pit
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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timer@fffffd30 {
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compatible = "atmel,at91sam9260-pit";
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reg = <0xfffffd30 0x10>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk32k>;
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};
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...

‎Documentation/devicetree/bindings/arm/atmel-sysregs.txt‎

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This file was deleted.

‎Documentation/devicetree/bindings/arm/microchip,sam9x60-pit64b.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/microchip,sam9x60-pit64b.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip PIT64B 64-bit Periodic Interval Timer
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maintainers:
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- Nicolas Ferre <[email protected]>
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- Claudiu Beznea <[email protected]>
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description:
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The Microchip PIT64B is a 64-bit periodic interval timer used in
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several modern Microchip ARM SoCs including SAM9X60, SAM9X7 and
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SAMA7D65 families. It provides extended timing range, flexible
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clock selection and supports both periodic and one-shot interrupt
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generation modes.
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properties:
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compatible:
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oneOf:
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- const: microchip,sam9x60-pit64b
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- items:
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- enum:
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- microchip,sam9x7-pit64b
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- microchip,sama7d65-pit64b
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- microchip,sama7g5-pit64b
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- const: microchip,sam9x60-pit64b
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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minItems: 1
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maxItems: 2
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items:
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enum:
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- pclk
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- gclk
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/clock/at91.h>
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timer@f0028000 {
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compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b";
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reg = <0xf0028000 0x100>;
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interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
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clock-names = "pclk", "gclk";
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};
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...

‎Documentation/devicetree/bindings/arm/microchip,sama7g5-chipid.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/microchip,sama7g5-chipid.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Atmel/Microchip RAMC SDRAM/DDR Controller
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maintainers:
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- Nicolas Ferre <[email protected]>
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- Claudiu Beznea <[email protected]>
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description:
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This binding describes the Atmel/Microchip Chip ID register block used
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for SoC identification and revision information. It requires compatible
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strings matching specific SoC families and a reg property defining the
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register address and size.
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properties:
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compatible:
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enum:
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- atmel,sama5d2-chipid
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- microchip,sama7d65-chipid
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- microchip,sama7g5-chipid
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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unevaluatedProperties: false
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examples:
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- |
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chipid@fc069000 {
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compatible = "atmel,sama5d2-chipid";
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reg = <0xfc069000 0x8>;
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};
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...

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