@@ -51,6 +51,8 @@ enum clk_ids {
5151 CLK_PLLDTY_ACPU_DIV4 ,
5252 CLK_PLLDTY_DIV8 ,
5353 CLK_PLLDTY_DIV16 ,
54+ CLK_PLLDTY_RCPU ,
55+ CLK_PLLDTY_RCPU_DIV4 ,
5456 CLK_PLLVDO_CRU0 ,
5557 CLK_PLLVDO_CRU1 ,
5658 CLK_PLLVDO_ISP ,
@@ -184,6 +186,8 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
184186 DEF_FIXED (".plldty_acpu_div4" , CLK_PLLDTY_ACPU_DIV4 , CLK_PLLDTY_ACPU , 1 , 4 ),
185187 DEF_FIXED (".plldty_div8" , CLK_PLLDTY_DIV8 , CLK_PLLDTY , 1 , 8 ),
186188 DEF_FIXED (".plldty_div16" , CLK_PLLDTY_DIV16 , CLK_PLLDTY , 1 , 16 ),
189+ DEF_DDIV (".plldty_rcpu" , CLK_PLLDTY_RCPU , CLK_PLLDTY , CDDIV3_DIVCTL2 , dtable_2_64 ),
190+ DEF_FIXED (".plldty_rcpu_div4" , CLK_PLLDTY_RCPU_DIV4 , CLK_PLLDTY_RCPU , 1 , 4 ),
187191
188192 DEF_DDIV (".pllvdo_cru0" , CLK_PLLVDO_CRU0 , CLK_PLLVDO , CDDIV3_DIVCTL3 , dtable_2_4 ),
189193 DEF_DDIV (".pllvdo_cru1" , CLK_PLLVDO_CRU1 , CLK_PLLVDO , CDDIV4_DIVCTL0 , dtable_2_4 ),
@@ -231,6 +235,16 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
231235};
232236
233237static const struct rzv2h_mod_clk r9a09g056_mod_clks [] __initconst = {
238+ DEF_MOD ("dmac_0_aclk" , CLK_PLLCM33_GEAR , 0 , 0 , 0 , 0 ,
239+ BUS_MSTOP (5 , BIT (9 ))),
240+ DEF_MOD ("dmac_1_aclk" , CLK_PLLDTY_ACPU_DIV2 , 0 , 1 , 0 , 1 ,
241+ BUS_MSTOP (3 , BIT (2 ))),
242+ DEF_MOD ("dmac_2_aclk" , CLK_PLLDTY_ACPU_DIV2 , 0 , 2 , 0 , 2 ,
243+ BUS_MSTOP (3 , BIT (3 ))),
244+ DEF_MOD ("dmac_3_aclk" , CLK_PLLDTY_RCPU_DIV4 , 0 , 3 , 0 , 3 ,
245+ BUS_MSTOP (10 , BIT (11 ))),
246+ DEF_MOD ("dmac_4_aclk" , CLK_PLLDTY_RCPU_DIV4 , 0 , 4 , 0 , 4 ,
247+ BUS_MSTOP (10 , BIT (12 ))),
234248 DEF_MOD_CRITICAL ("gic_0_gicclk" , CLK_PLLDTY_ACPU_DIV4 , 1 , 3 , 0 , 19 ,
235249 BUS_MSTOP (3 , BIT (5 ))),
236250 DEF_MOD ("gtm_0_pclk" , CLK_PLLCM33_DIV16 , 4 , 3 , 2 , 3 ,
@@ -401,6 +415,11 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
401415
402416static const struct rzv2h_reset r9a09g056_resets [] __initconst = {
403417 DEF_RST (3 , 0 , 1 , 1 ), /* SYS_0_PRESETN */
418+ DEF_RST (3 , 1 , 1 , 2 ), /* DMAC_0_ARESETN */
419+ DEF_RST (3 , 2 , 1 , 3 ), /* DMAC_1_ARESETN */
420+ DEF_RST (3 , 3 , 1 , 4 ), /* DMAC_2_ARESETN */
421+ DEF_RST (3 , 4 , 1 , 5 ), /* DMAC_3_ARESETN */
422+ DEF_RST (3 , 5 , 1 , 6 ), /* DMAC_4_ARESETN */
404423 DEF_RST (3 , 8 , 1 , 9 ), /* GIC_0_GICRESET_N */
405424 DEF_RST (3 , 9 , 1 , 10 ), /* GIC_0_DBG_GICRESET_N */
406425 DEF_RST (6 , 13 , 2 , 30 ), /* GTM_0_PRESETZ */
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