drm/i915/display: Set C10_VDR_CTRL_MSGBUS_ACCESS before phy reg read

According to C10 VDR Register programming sequence we need set
C10_VDR_CTRL_MSGBUS_ACCESS before accessing PHY internal registers from
MsgBus.

v2: set C10_VDR_CTRL_MSGBUS_ACCESS once for all owned lanes

Bspec: 68962
Fixes: 9dc6196 ("drm/i915/display: Add function to configure LFPS sending")
Suggested-by: Gustavo Sousa <[email protected]>
Signed-off-by: Jouni Högander <[email protected]>
Reviewed-by: Gustavo Sousa <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
(cherry picked from commit 8921dce)
Signed-off-by: Tvrtko Ursulin <[email protected]>

Author: hogander

drivers/gpu/drm/i915/display/intel_cx0_phy.c

@@ -3251,6 +3251,10 @@ void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
 
 	wakeref = intel_cx0_phy_transaction_begin(encoder);
 
+	if (intel_encoder_is_c10phy(encoder))
+		intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1), 0,
+			      C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
+
 	for (i = 0; i < 4; i++) {
 		int tx = i % 2 + 1;
 		u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;