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Merge tag 'soc-drivers-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann: "The driver updates again are all over the place with many minor fixes going into platform specific code. The most notable changes are: - Support for Microchip pic64gx system controllers - Work on cleaning up devicetree bindings for SoC drivers, and converting them into the new format - Lots of smaller changes for Qualcomm SoC drivers, including support for a number of newly supported chips - reset controller API cleanups and a new driver for Cix Sky1 - Reworks of the Tegra PMC and CBB drivers, along with a change to how individual Tegra SoCs get selected in Kconfig and BPMP firmware driver updates including a refresh of the ABI header to match the version used by firmware - STM32 updates to the firewall bus driver and support for the debug bus through OP-TEE - SCMI firmware driver improvements for reliability, in particular for dealing with broken firmware interrupts - Memory driver updates for Tegra, and a patch to remove the unused Baikal T1 driver" * tag 'soc-drivers-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (193 commits) firmware: arm_ffa: Use the correct buffer size during RXTX_MAP firmware: qcom: scm: Allow QSEECOM on Lenovo IdeaCentre Mini X clk: spear: fix resource leak in clk_register_vco_pll() reset: rzv2h-usb2phy: Add support for VBUS mux controller registration reset: rzv2h-usb2phy: Convert to regmap API dt-bindings: reset: renesas,rzv2h-usb2phy: Document RZ/G3E USB2PHY reset dt-bindings: reset: renesas,rzv2h-usb2phy: Add '#mux-state-cells' property soc: microchip: add mpfs gpio interrupt mux driver dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux gpio: mpfs: Add interrupt support soc: qcom: ubwc: add helpers to get programmable values soc: qcom: ubwc: add helper to get min_acc length firmware: qcom: scm: Register gunyah watchdog device soc: qcom: socinfo: Add SoC ID for SA8650P dt-bindings: arm: qcom,ids: Add SoC ID for SA8650P firmware: qcom: scm: Allow QSEECOM on Mahua CRD soc: qcom: wcnss: simplify allocation of req soc: qcom: pd-mapper: Add support for Eliza soc: qcom: aoss: compare against normalized cooling state soc: qcom: llcc: fix v1 SB syndrome register offset ...
2 parents e65f471 + 33a20cd commit 31b43c0

148 files changed

Lines changed: 9039 additions & 2652 deletions

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‎Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml‎

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"#address-cells":
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const: 1
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access-controllers:
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maxItems: 1
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patternProperties:
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'^trig-conns@([0-9]+)$':
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type: object

‎Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml‎

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description: Output connection to CoreSight Trace bus
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$ref: /schemas/graph.yaml#/properties/port
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access-controllers:
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maxItems: 1
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required:
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- compatible
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- reg

‎Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml‎

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description: Output connection from the ETM to CoreSight Trace bus.
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$ref: /schemas/graph.yaml#/properties/port
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access-controllers:
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maxItems: 1
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required:
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- compatible
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- clocks

‎Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml‎

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description: Output connection to the CoreSight Trace bus.
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$ref: /schemas/graph.yaml#/properties/port
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access-controllers:
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maxItems: 1
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required:
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- compatible
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- reg

‎Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml‎

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- const: tracedata
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- const: metadata
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access-controllers:
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maxItems: 1
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required:
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- compatible
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- reg

‎Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml‎

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description: Input connection from the CoreSight Trace bus.
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$ref: /schemas/graph.yaml#/properties/port
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access-controllers:
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maxItems: 1
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required:
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- compatible
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- reg

‎Documentation/devicetree/bindings/arm/atmel,at91rm9200-sdramc.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/atmel,at91rm9200-sdramc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip (Atmel) SDRAM / DDR Controller (RAMC / DDRAMC / UDDRC)
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maintainers:
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- Nicolas Ferre <[email protected]>
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- Claudiu Beznea <[email protected]>
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description:
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The SDRAM/DDR Controller (often called RAMC or DDRAMC) in various
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Atmel/Microchip ARM9 and Cortex-A5/A7 SoCs manages external
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SDRAM / DDR memory. It is typically exposed as a syscon node for
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register access from other drivers (e.g. for initialization or mode
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configuration). No interrupts or clocks are usually required in the
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binding.
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properties:
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compatible:
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oneOf:
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- items:
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- const: atmel,at91rm9200-sdramc
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- const: syscon
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- items:
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- const: microchip,sama7d65-uddrc
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- const: microchip,sama7g5-uddrc
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- enum:
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- atmel,at91sam9260-sdramc
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- atmel,at91sam9g45-ddramc
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- atmel,sama5d3-ddramc
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- microchip,sam9x60-ddramc
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- microchip,sam9x7-ddramc
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- microchip,sama7g5-uddrc
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reg:
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maxItems: 1
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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minItems: 1
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items:
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- const: ddrck
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- const: mpddr
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required:
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- compatible
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- reg
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/at91.h>
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ramc@ffffe400 {
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compatible = "atmel,at91sam9g45-ddramc";
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reg = <0xffffe400 0x200>;
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clocks = <&pmc PMC_TYPE_SYSTEM 2>;
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clock-names = "ddrck";
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};
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...

‎Documentation/devicetree/bindings/arm/atmel,at91rm9200-st.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/atmel,at91rm9200-st.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Atmel System Timer
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maintainers:
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- Nicolas Ferre <[email protected]>
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- Claudiu Beznea <[email protected]>
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description:
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The System Timer (ST) module in AT91RM9200 provides periodic tick and
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alarm capabilities. It is exposed as a simple multi-function device
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(simple-mfd + syscon) because it shares its register space and interrupt
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with other System Controller blocks.
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properties:
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compatible:
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items:
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- const: atmel,at91rm9200-st
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- const: syscon
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- const: simple-mfd
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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patternProperties:
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"^watchdog@[0-9a-f]+$":
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$ref: /schemas/watchdog/atmel,at91rm9200-wdt.yaml#
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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timer@fffffd00 {
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compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd";
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reg = <0xfffffd00 0x100>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
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clocks = <&slow_xtal>;
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#address-cells = <1>;
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#size-cells = <1>;
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watchdog@fffffd40 {
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compatible = "atmel,at91rm9200-wdt";
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reg = <0xfffffd40 0x40>;
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};
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};
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...

‎Documentation/devicetree/bindings/arm/atmel,at91sam9260-pit.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/atmel,at91sam9260-pit.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Atmel AT91SAM9260 Periodic Interval Timer (PIT)
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maintainers:
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- Nicolas Ferre <[email protected]>
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- Claudiu Beznea <[email protected]>
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description:
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The Periodic Interval Timer (PIT) is part of the System Controller of
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various Microchip 32-bit ARM-based SoCs (formerly Atmel AT91 series).
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It is a simple down-counter timer used mainly as the kernel tick source.
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The PIT is clocked from the slow clock and shares a single IRQ line with
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other System Controller peripherals.
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properties:
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compatible:
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const: atmel,at91sam9260-pit
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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timer@fffffd30 {
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compatible = "atmel,at91sam9260-pit";
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reg = <0xfffffd30 0x10>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk32k>;
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};
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...

‎Documentation/devicetree/bindings/arm/atmel-sysregs.txt‎

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