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Merge tag 'reset-fixes-for-v7.0-2' of https://git.pengutronix.de/git/pza/linux into arm/fixes
Reset controller fixes for v7.0, part 2 * Decouple spacemit K3 reset lines that were incorrectly coupled together as one, but are in fact separate resets in hardware. * Fix a double free in the reset_add_gpio_aux_device() error path. This has already been fixed on reset/next by commit a9b95ce ("reset: gpio: add a devlink between reset-gpio and its consumer"). * Fix the MODULE_AUTHOR string in the rzg2l-usbphy-ctrl driver. * tag 'reset-fixes-for-v7.0-2' of https://git.pengutronix.de/git/pza/linux: reset: spacemit: k3: Decouple composite reset lines reset: gpio: fix double free in reset_add_gpio_aux_device() error path reset: rzg2l-usbphy-ctrl: Fix malformed MODULE_AUTHOR string Signed-off-by: Krzysztof Kozlowski <[email protected]>
2 parents 55372ab + a0e0c2f commit 14a8912

4 files changed

Lines changed: 73 additions & 38 deletions

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‎drivers/reset/core.c‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -856,7 +856,6 @@ static int reset_add_gpio_aux_device(struct device *parent,
856856
ret = __auxiliary_device_add(adev, "reset");
857857
if (ret) {
858858
auxiliary_device_uninit(adev);
859-
kfree(adev);
860859
return ret;
861860
}
862861

‎drivers/reset/reset-rzg2l-usbphy-ctrl.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -350,4 +350,4 @@ module_platform_driver(rzg2l_usbphy_ctrl_driver);
350350

351351
MODULE_LICENSE("GPL v2");
352352
MODULE_DESCRIPTION("Renesas RZ/G2L USBPHY Control");
353-
MODULE_AUTHOR("[email protected]>");
353+
MODULE_AUTHOR("Biju Das <[email protected]>");

‎drivers/reset/spacemit/reset-spacemit-k3.c‎

Lines changed: 36 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -112,16 +112,21 @@ static const struct ccu_reset_data k3_apmu_resets[] = {
112112
[RESET_APMU_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)),
113113
[RESET_APMU_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)),
114114
[RESET_APMU_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)),
115-
[RESET_APMU_USB2] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0,
116-
BIT(1)|BIT(2)|BIT(3)),
117-
[RESET_APMU_USB3_PORTA] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0,
118-
BIT(5)|BIT(6)|BIT(7)),
119-
[RESET_APMU_USB3_PORTB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0,
120-
BIT(9)|BIT(10)|BIT(11)),
121-
[RESET_APMU_USB3_PORTC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0,
122-
BIT(13)|BIT(14)|BIT(15)),
123-
[RESET_APMU_USB3_PORTD] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0,
124-
BIT(17)|BIT(18)|BIT(19)),
115+
[RESET_APMU_USB2_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(1)),
116+
[RESET_APMU_USB2_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(2)),
117+
[RESET_APMU_USB2_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(3)),
118+
[RESET_APMU_USB3_A_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(5)),
119+
[RESET_APMU_USB3_A_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(6)),
120+
[RESET_APMU_USB3_A_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(7)),
121+
[RESET_APMU_USB3_B_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(9)),
122+
[RESET_APMU_USB3_B_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(10)),
123+
[RESET_APMU_USB3_B_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(11)),
124+
[RESET_APMU_USB3_C_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(13)),
125+
[RESET_APMU_USB3_C_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(14)),
126+
[RESET_APMU_USB3_C_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(15)),
127+
[RESET_APMU_USB3_D_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(17)),
128+
[RESET_APMU_USB3_D_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(18)),
129+
[RESET_APMU_USB3_D_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(19)),
125130
[RESET_APMU_QSPI] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)),
126131
[RESET_APMU_QSPI_BUS] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)),
127132
[RESET_APMU_DMA] = RESET_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)),
@@ -151,10 +156,12 @@ static const struct ccu_reset_data k3_apmu_resets[] = {
151156
[RESET_APMU_CPU7_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(26), 0),
152157
[RESET_APMU_C1_MPSUB_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(28), 0),
153158
[RESET_APMU_MPSUB_DBG] = RESET_DATA(APMU_PMU_CC2_AP, BIT(29), 0),
154-
[RESET_APMU_UCIE] = RESET_DATA(APMU_UCIE_CTRL,
155-
BIT(1) | BIT(2) | BIT(3), 0),
156-
[RESET_APMU_RCPU] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0,
157-
BIT(3) | BIT(2) | BIT(0)),
159+
[RESET_APMU_UCIE_IP] = RESET_DATA(APMU_UCIE_CTRL, BIT(1), 0),
160+
[RESET_APMU_UCIE_HOT] = RESET_DATA(APMU_UCIE_CTRL, BIT(2), 0),
161+
[RESET_APMU_UCIE_MON] = RESET_DATA(APMU_UCIE_CTRL, BIT(3), 0),
162+
[RESET_APMU_RCPU_AUDIO_SYS] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, BIT(0)),
163+
[RESET_APMU_RCPU_MCU_CORE] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, BIT(2)),
164+
[RESET_APMU_RCPU_AUDIO_APMU] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, BIT(3)),
158165
[RESET_APMU_DSI4LN2_ESCCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(3)),
159166
[RESET_APMU_DSI4LN2_LCD_SW] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(4)),
160167
[RESET_APMU_DSI4LN2_LCD_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL4, 0, BIT(9)),
@@ -164,16 +171,21 @@ static const struct ccu_reset_data k3_apmu_resets[] = {
164171
[RESET_APMU_UFS_ACLK] = RESET_DATA(APMU_UFS_CLK_RES_CTRL, 0, BIT(0)),
165172
[RESET_APMU_EDP0] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(0)),
166173
[RESET_APMU_EDP1] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(16)),
167-
[RESET_APMU_PCIE_PORTA] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0,
168-
BIT(5) | BIT(4) | BIT(3)),
169-
[RESET_APMU_PCIE_PORTB] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0,
170-
BIT(5) | BIT(4) | BIT(3)),
171-
[RESET_APMU_PCIE_PORTC] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0,
172-
BIT(5) | BIT(4) | BIT(3)),
173-
[RESET_APMU_PCIE_PORTD] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0,
174-
BIT(5) | BIT(4) | BIT(3)),
175-
[RESET_APMU_PCIE_PORTE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0,
176-
BIT(5) | BIT(4) | BIT(3)),
174+
[RESET_APMU_PCIE_A_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, BIT(3)),
175+
[RESET_APMU_PCIE_A_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, BIT(4)),
176+
[RESET_APMU_PCIE_A_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, BIT(5)),
177+
[RESET_APMU_PCIE_B_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, BIT(3)),
178+
[RESET_APMU_PCIE_B_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, BIT(4)),
179+
[RESET_APMU_PCIE_B_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, BIT(5)),
180+
[RESET_APMU_PCIE_C_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, BIT(3)),
181+
[RESET_APMU_PCIE_C_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, BIT(4)),
182+
[RESET_APMU_PCIE_C_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, BIT(5)),
183+
[RESET_APMU_PCIE_D_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, BIT(3)),
184+
[RESET_APMU_PCIE_D_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, BIT(4)),
185+
[RESET_APMU_PCIE_D_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, BIT(5)),
186+
[RESET_APMU_PCIE_E_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, BIT(3)),
187+
[RESET_APMU_PCIE_E_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, BIT(4)),
188+
[RESET_APMU_PCIE_E_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, BIT(5)),
177189
[RESET_APMU_EMAC0] = RESET_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)),
178190
[RESET_APMU_EMAC1] = RESET_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)),
179191
[RESET_APMU_EMAC2] = RESET_DATA(APMU_EMAC2_CLK_RES_CTRL, 0, BIT(1)),

‎include/dt-bindings/reset/spacemit,k3-resets.h‎

Lines changed: 36 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -97,11 +97,11 @@
9797
#define RESET_APMU_SDH0 13
9898
#define RESET_APMU_SDH1 14
9999
#define RESET_APMU_SDH2 15
100-
#define RESET_APMU_USB2 16
101-
#define RESET_APMU_USB3_PORTA 17
102-
#define RESET_APMU_USB3_PORTB 18
103-
#define RESET_APMU_USB3_PORTC 19
104-
#define RESET_APMU_USB3_PORTD 20
100+
#define RESET_APMU_USB2_AHB 16
101+
#define RESET_APMU_USB2_VCC 17
102+
#define RESET_APMU_USB2_PHY 18
103+
#define RESET_APMU_USB3_A_AHB 19
104+
#define RESET_APMU_USB3_A_VCC 20
105105
#define RESET_APMU_QSPI 21
106106
#define RESET_APMU_QSPI_BUS 22
107107
#define RESET_APMU_DMA 23
@@ -132,8 +132,8 @@
132132
#define RESET_APMU_CPU7_SW 48
133133
#define RESET_APMU_C1_MPSUB_SW 49
134134
#define RESET_APMU_MPSUB_DBG 50
135-
#define RESET_APMU_UCIE 51
136-
#define RESET_APMU_RCPU 52
135+
#define RESET_APMU_USB3_A_PHY 51 /* USB3 A */
136+
#define RESET_APMU_USB3_B_AHB 52
137137
#define RESET_APMU_DSI4LN2_ESCCLK 53
138138
#define RESET_APMU_DSI4LN2_LCD_SW 54
139139
#define RESET_APMU_DSI4LN2_LCD_MCLK 55
@@ -143,16 +143,40 @@
143143
#define RESET_APMU_UFS_ACLK 59
144144
#define RESET_APMU_EDP0 60
145145
#define RESET_APMU_EDP1 61
146-
#define RESET_APMU_PCIE_PORTA 62
147-
#define RESET_APMU_PCIE_PORTB 63
148-
#define RESET_APMU_PCIE_PORTC 64
149-
#define RESET_APMU_PCIE_PORTD 65
150-
#define RESET_APMU_PCIE_PORTE 66
146+
#define RESET_APMU_USB3_B_VCC 62 /* USB3 B */
147+
#define RESET_APMU_USB3_B_PHY 63
148+
#define RESET_APMU_USB3_C_AHB 64
149+
#define RESET_APMU_USB3_C_VCC 65
150+
#define RESET_APMU_USB3_C_PHY 66
151151
#define RESET_APMU_EMAC0 67
152152
#define RESET_APMU_EMAC1 68
153153
#define RESET_APMU_EMAC2 69
154154
#define RESET_APMU_ESPI_MCLK 70
155155
#define RESET_APMU_ESPI_SCLK 71
156+
#define RESET_APMU_USB3_D_AHB 72 /* USB3 D */
157+
#define RESET_APMU_USB3_D_VCC 73
158+
#define RESET_APMU_USB3_D_PHY 74
159+
#define RESET_APMU_UCIE_IP 75
160+
#define RESET_APMU_UCIE_HOT 76
161+
#define RESET_APMU_UCIE_MON 77
162+
#define RESET_APMU_RCPU_AUDIO_SYS 78
163+
#define RESET_APMU_RCPU_MCU_CORE 79
164+
#define RESET_APMU_RCPU_AUDIO_APMU 80
165+
#define RESET_APMU_PCIE_A_DBI 81
166+
#define RESET_APMU_PCIE_A_SLAVE 82
167+
#define RESET_APMU_PCIE_A_MASTER 83
168+
#define RESET_APMU_PCIE_B_DBI 84
169+
#define RESET_APMU_PCIE_B_SLAVE 85
170+
#define RESET_APMU_PCIE_B_MASTER 86
171+
#define RESET_APMU_PCIE_C_DBI 87
172+
#define RESET_APMU_PCIE_C_SLAVE 88
173+
#define RESET_APMU_PCIE_C_MASTER 89
174+
#define RESET_APMU_PCIE_D_DBI 90
175+
#define RESET_APMU_PCIE_D_SLAVE 91
176+
#define RESET_APMU_PCIE_D_MASTER 92
177+
#define RESET_APMU_PCIE_E_DBI 93
178+
#define RESET_APMU_PCIE_E_SLAVE 94
179+
#define RESET_APMU_PCIE_E_MASTER 95
156180

157181
/* DCIU resets*/
158182
#define RESET_DCIU_HDMA 0

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