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dt-bindings: clock: qcom: Add Nord Global Clock Controller
Add device tree bindings for the global clock controller on Qualcomm Nord platform. The global clock controller on Nord SoC is divided into multiple clock controllers (GCC,SE_GCC,NE_GCC and NW_GCC). Add each of the bindings to define the clock controllers. Signed-off-by: Taniya Das <[email protected]> Signed-off-by: Bartosz Golaszewski <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
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‎Documentation/devicetree/bindings/clock/qcom,nord-gcc.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,nord-gcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller on Nord SoC
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maintainers:
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- Taniya Das <[email protected]>
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description: |
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Qualcomm global clock control module provides the clocks, resets and power
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domains on Nord SoC.
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See also: include/dt-bindings/clock/qcom,nord-gcc.h
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properties:
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compatible:
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const: qcom,nord-gcc
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clocks:
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items:
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- description: Board XO source
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- description: Sleep clock source
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- description: PCIE A Pipe clock source
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- description: PCIE B Pipe clock source
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- description: PCIE C Pipe clock source
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- description: PCIE D Pipe clock source
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required:
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- compatible
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- clocks
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- '#power-domain-cells'
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@100000 {
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compatible = "qcom,nord-gcc";
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reg = <0x00100000 0x1f4200>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&sleep_clk>,
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<&pcie_a_pipe_clk>,
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<&pcie_b_pipe_clk>,
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<&pcie_c_pipe_clk>,
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<&pcie_d_pipe_clk>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,nord-negcc.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,nord-negcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global North East Clock & Reset Controller on Nord SoC
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maintainers:
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- Taniya Das <[email protected]>
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description: |
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Qualcomm global clock control (NE) module provides the clocks, resets
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and power domains on Nord SoC.
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See also: include/dt-bindings/clock/qcom,nord-negcc.h
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properties:
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compatible:
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const: qcom,nord-negcc
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clocks:
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items:
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- description: Board XO source
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- description: Sleep clock source
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- description: UFS Phy Rx symbol 0 clock source
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- description: UFS Phy Rx symbol 1 clock source
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- description: UFS Phy Tx symbol 0 clock source
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- description: USB3 Phy sec wrapper pipe clock source
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- description: USB3 Phy wrapper pipe clock source
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required:
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- compatible
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- clocks
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- '#power-domain-cells'
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@8900000 {
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compatible = "qcom,nord-negcc";
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reg = <0x08900000 0xf4200>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&sleep_clk>,
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<&ufs_phy_rx_symbol_0_clk>,
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<&ufs_phy_rx_symbol_1_clk>,
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<&ufs_phy_tx_symbol_0_clk>,
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<&usb3_phy_sec_pipe_clk>,
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<&usb3_phy_pipe_clk>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,nord-nwgcc.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,nord-nwgcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global North West and South East Clock & Reset Controller
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on Nord SoC
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maintainers:
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- Taniya Das <[email protected]>
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description: |
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Qualcomm global clock control (NW, SE) module provides the clocks, resets
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and power domains on Nord SoC.
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See also:
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include/dt-bindings/clock/qcom,nord-nwgcc.h
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include/dt-bindings/clock/qcom,nord-segcc.h
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properties:
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compatible:
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enum:
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- qcom,nord-nwgcc
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- qcom,nord-segcc
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clocks:
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items:
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- description: Board XO source
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- description: Sleep clock source
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required:
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- compatible
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- clocks
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- '#power-domain-cells'
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@8b00000 {
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compatible = "qcom,nord-nwgcc";
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reg = <0x08b00000 0xf4200>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&sleep_clk>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...

‎include/dt-bindings/clock/qcom,nord-gcc.h‎

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GCC_NORD_H
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#define _DT_BINDINGS_CLK_QCOM_GCC_NORD_H
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/* GCC clocks */
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#define GCC_BOOT_ROM_AHB_CLK 0
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#define GCC_GP1_CLK 1
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#define GCC_GP1_CLK_SRC 2
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#define GCC_GP2_CLK 3
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#define GCC_GP2_CLK_SRC 4
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#define GCC_GPLL0 5
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#define GCC_GPLL0_OUT_EVEN 6
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#define GCC_MMU_0_TCU_VOTE_CLK 7
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#define GCC_PCIE_A_AUX_CLK 8
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#define GCC_PCIE_A_AUX_CLK_SRC 9
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#define GCC_PCIE_A_CFG_AHB_CLK 10
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#define GCC_PCIE_A_DTI_QTC_CLK 11
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#define GCC_PCIE_A_MSTR_AXI_CLK 12
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#define GCC_PCIE_A_PHY_AUX_CLK 13
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#define GCC_PCIE_A_PHY_AUX_CLK_SRC 14
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#define GCC_PCIE_A_PHY_RCHNG_CLK 15
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#define GCC_PCIE_A_PHY_RCHNG_CLK_SRC 16
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#define GCC_PCIE_A_PIPE_CLK 17
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#define GCC_PCIE_A_PIPE_CLK_SRC 18
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#define GCC_PCIE_A_SLV_AXI_CLK 19
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#define GCC_PCIE_A_SLV_Q2A_AXI_CLK 20
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#define GCC_PCIE_B_AUX_CLK 21
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#define GCC_PCIE_B_AUX_CLK_SRC 22
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#define GCC_PCIE_B_CFG_AHB_CLK 23
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#define GCC_PCIE_B_DTI_QTC_CLK 24
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#define GCC_PCIE_B_MSTR_AXI_CLK 25
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#define GCC_PCIE_B_PHY_AUX_CLK 26
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#define GCC_PCIE_B_PHY_AUX_CLK_SRC 27
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#define GCC_PCIE_B_PHY_RCHNG_CLK 28
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#define GCC_PCIE_B_PHY_RCHNG_CLK_SRC 29
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#define GCC_PCIE_B_PIPE_CLK 30
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#define GCC_PCIE_B_PIPE_CLK_SRC 31
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#define GCC_PCIE_B_SLV_AXI_CLK 32
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#define GCC_PCIE_B_SLV_Q2A_AXI_CLK 33
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#define GCC_PCIE_C_AUX_CLK 34
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#define GCC_PCIE_C_AUX_CLK_SRC 35
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#define GCC_PCIE_C_CFG_AHB_CLK 36
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#define GCC_PCIE_C_DTI_QTC_CLK 37
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#define GCC_PCIE_C_MSTR_AXI_CLK 38
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#define GCC_PCIE_C_PHY_AUX_CLK 39
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#define GCC_PCIE_C_PHY_AUX_CLK_SRC 40
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#define GCC_PCIE_C_PHY_RCHNG_CLK 41
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#define GCC_PCIE_C_PHY_RCHNG_CLK_SRC 42
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#define GCC_PCIE_C_PIPE_CLK 43
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#define GCC_PCIE_C_PIPE_CLK_SRC 44
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#define GCC_PCIE_C_SLV_AXI_CLK 45
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#define GCC_PCIE_C_SLV_Q2A_AXI_CLK 46
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#define GCC_PCIE_D_AUX_CLK 47
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#define GCC_PCIE_D_AUX_CLK_SRC 48
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#define GCC_PCIE_D_CFG_AHB_CLK 49
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#define GCC_PCIE_D_DTI_QTC_CLK 50
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#define GCC_PCIE_D_MSTR_AXI_CLK 51
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#define GCC_PCIE_D_PHY_AUX_CLK 52
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#define GCC_PCIE_D_PHY_AUX_CLK_SRC 53
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#define GCC_PCIE_D_PHY_RCHNG_CLK 54
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#define GCC_PCIE_D_PHY_RCHNG_CLK_SRC 55
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#define GCC_PCIE_D_PIPE_CLK 56
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#define GCC_PCIE_D_PIPE_CLK_SRC 57
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#define GCC_PCIE_D_SLV_AXI_CLK 58
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#define GCC_PCIE_D_SLV_Q2A_AXI_CLK 59
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#define GCC_PCIE_LINK_AHB_CLK 60
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#define GCC_PCIE_LINK_XO_CLK 61
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#define GCC_PCIE_NOC_ASYNC_BRIDGE_CLK 62
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#define GCC_PCIE_NOC_CNOC_SF_QX_CLK 63
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#define GCC_PCIE_NOC_M_CFG_CLK 64
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#define GCC_PCIE_NOC_M_PDB_CLK 65
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#define GCC_PCIE_NOC_MSTR_AXI_CLK 66
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#define GCC_PCIE_NOC_PWRCTL_CLK 67
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#define GCC_PCIE_NOC_QOSGEN_EXTREF_CLK 68
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#define GCC_PCIE_NOC_REFGEN_CLK 69
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#define GCC_PCIE_NOC_REFGEN_CLK_SRC 70
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#define GCC_PCIE_NOC_S_CFG_CLK 71
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#define GCC_PCIE_NOC_S_PDB_CLK 72
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#define GCC_PCIE_NOC_SAFETY_CLK 73
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#define GCC_PCIE_NOC_SAFETY_CLK_SRC 74
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#define GCC_PCIE_NOC_SLAVE_AXI_CLK 75
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#define GCC_PCIE_NOC_TSCTR_CLK 76
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#define GCC_PCIE_NOC_XO_CLK 77
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#define GCC_PDM2_CLK 78
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#define GCC_PDM2_CLK_SRC 79
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#define GCC_PDM_AHB_CLK 80
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#define GCC_PDM_XO4_CLK 81
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#define GCC_QUPV3_WRAP3_CORE_2X_CLK 82
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#define GCC_QUPV3_WRAP3_CORE_CLK 83
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#define GCC_QUPV3_WRAP3_M_CLK 84
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#define GCC_QUPV3_WRAP3_QSPI_REF_CLK 85
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#define GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC 86
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#define GCC_QUPV3_WRAP3_S0_CLK 87
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#define GCC_QUPV3_WRAP3_S0_CLK_SRC 88
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#define GCC_QUPV3_WRAP3_S_AHB_CLK 89
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#define GCC_SMMU_PCIE_QTC_VOTE_CLK 90
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/* GCC power domains */
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#define GCC_PCIE_A_GDSC 0
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#define GCC_PCIE_A_PHY_GDSC 1
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#define GCC_PCIE_B_GDSC 2
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#define GCC_PCIE_B_PHY_GDSC 3
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#define GCC_PCIE_C_GDSC 4
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#define GCC_PCIE_C_PHY_GDSC 5
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#define GCC_PCIE_D_GDSC 6
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#define GCC_PCIE_D_PHY_GDSC 7
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#define GCC_PCIE_NOC_GDSC 8
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/* GCC resets */
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#define GCC_PCIE_A_BCR 0
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#define GCC_PCIE_A_LINK_DOWN_BCR 1
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#define GCC_PCIE_A_NOCSR_COM_PHY_BCR 2
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#define GCC_PCIE_A_PHY_BCR 3
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#define GCC_PCIE_A_PHY_CFG_AHB_BCR 4
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#define GCC_PCIE_A_PHY_COM_BCR 5
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#define GCC_PCIE_A_PHY_NOCSR_COM_PHY_BCR 6
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#define GCC_PCIE_B_BCR 7
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#define GCC_PCIE_B_LINK_DOWN_BCR 8
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#define GCC_PCIE_B_NOCSR_COM_PHY_BCR 9
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#define GCC_PCIE_B_PHY_BCR 10
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#define GCC_PCIE_B_PHY_CFG_AHB_BCR 11
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#define GCC_PCIE_B_PHY_COM_BCR 12
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#define GCC_PCIE_B_PHY_NOCSR_COM_PHY_BCR 13
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#define GCC_PCIE_C_BCR 14
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#define GCC_PCIE_C_LINK_DOWN_BCR 15
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#define GCC_PCIE_C_NOCSR_COM_PHY_BCR 16
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#define GCC_PCIE_C_PHY_BCR 17
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#define GCC_PCIE_C_PHY_CFG_AHB_BCR 18
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#define GCC_PCIE_C_PHY_COM_BCR 19
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#define GCC_PCIE_C_PHY_NOCSR_COM_PHY_BCR 20
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#define GCC_PCIE_D_BCR 21
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#define GCC_PCIE_D_LINK_DOWN_BCR 22
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#define GCC_PCIE_D_NOCSR_COM_PHY_BCR 23
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#define GCC_PCIE_D_PHY_BCR 24
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#define GCC_PCIE_D_PHY_CFG_AHB_BCR 25
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#define GCC_PCIE_D_PHY_COM_BCR 26
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#define GCC_PCIE_D_PHY_NOCSR_COM_PHY_BCR 27
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#define GCC_PCIE_NOC_BCR 28
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#define GCC_PDM_BCR 29
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#define GCC_QUPV3_WRAPPER_3_BCR 30
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#define GCC_TCSR_PCIE_BCR 31
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#endif

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