fix: rotate-by-zero UB in GPU/DSP ROR/RORQ opcodes

UBSAN on PR #126 found:

  src/tom/gpu.c:1674: shift exponent 32 too large for uint32_t

The classic rotate-right idiom

  (RN >> r1) | (RN << (32 - r1))

invokes UB when r1 == 0 (32-bit shift count of 32 is out of range).
Replace with the standard portable pattern:

  (RN >> r1) | (RN << ((-r1) & 31))

which yields RN | RN == RN for r1 == 0 and is identical for
r1 in [1, 31].  Modern GCC/clang pattern-match this idiom into a
single rotate instruction (rorl on x86, ror on ARM).

Six sites across two files:
  - src/tom/gpu.c       gpu_opcode_ror, gpu_opcode_rorq
  - src/jerry/dsp.c     dsp_opcode_ror, dsp_opcode_rorq, plus the
                        prefetched (PRN) variants

Co-Authored-By: Claude Opus 4.7 <[email protected]>

Author: JoeMatt

src/jerry/dsp.c

@@ -1409,7 +1409,7 @@ INLINE static void dsp_opcode_shrq(void)
 INLINE static void dsp_opcode_ror(void)
 {
 	uint32_t r1 = RM & 0x1F;
-	uint32_t res = (RN >> r1) | (RN << (32 - r1));
+	uint32_t res = (RN >> r1) | (RN << ((-r1) & 31));
 	SET_ZN(res); dsp_flag_c = (RN >> 31) & 1;
 	RN = res;
 }
@@ -1419,7 +1419,7 @@ INLINE static void dsp_opcode_rorq(void)
 {
 	uint32_t r1 = dsp_convert_zero[IMM_1 & 0x1F];
 	uint32_t r2 = RN;
-	uint32_t res = (r2 >> r1) | (r2 << (32 - r1));
+	uint32_t res = (r2 >> r1) | (r2 << ((-r1) & 31));
 	RN = res;
 	SET_ZN(res); dsp_flag_c = (r2 >> 31) & 0x01;
 }
@@ -2226,7 +2226,7 @@ INLINE static void DSP_resmac(void)
 INLINE static void DSP_ror(void)
 {
 	uint32_t r1 = PRM & 0x1F;
-	uint32_t res = (PRN >> r1) | (PRN << (32 - r1));
+	uint32_t res = (PRN >> r1) | (PRN << ((-r1) & 31));
 	SET_ZN(res); dsp_flag_c = (PRN >> 31) & 1;
 	PRES = res;
 }
@@ -2235,7 +2235,7 @@ INLINE static void DSP_rorq(void)
 {
 	uint32_t r1 = dsp_convert_zero[PIMM1 & 0x1F];
 	uint32_t r2 = PRN;
-	uint32_t res = (r2 >> r1) | (r2 << (32 - r1));
+	uint32_t res = (r2 >> r1) | (r2 << ((-r1) & 31));
 	PRES = res;
 	SET_ZN(res); dsp_flag_c = (r2 >> 31) & 0x01;
 }

src/tom/gpu.c

@@ -1671,7 +1671,7 @@ INLINE static void gpu_opcode_shrq(void)
 INLINE static void gpu_opcode_ror(void)
 {
    uint32_t r1 = RM & 0x1F;
-   uint32_t res = (RN >> r1) | (RN << (32 - r1));
+   uint32_t res = (RN >> r1) | (RN << ((-r1) & 31));
    SET_ZN(res); gpu_flag_c = (RN >> 31) & 1;
    RN = res;
 }
@@ -1681,7 +1681,7 @@ INLINE static void gpu_opcode_rorq(void)
 {
    uint32_t r1 = gpu_convert_zero[IMM_1 & 0x1F];
    uint32_t r2 = RN;
-   uint32_t res = (r2 >> r1) | (r2 << (32 - r1));
+   uint32_t res = (r2 >> r1) | (r2 << ((-r1) & 31));
    RN = res;
    SET_ZN(res); gpu_flag_c = (r2 >> 31) & 0x01;
 }