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Add SRAM interface test with custom EEPROM test ROM
- gen_eeprom_test_rom.c: generates a 128KB Jaguar ROM that writes known values (0xCAFE, 0xBEEF, 0xDEAD, 0x1234) to EEPROM via JERRY serial interface bit-banging - sram_test.c: headless test harness that loads the core via dlopen, runs the ROM, and verifies SRAM buffer contents, round-trip, and persistence across retro_reset() - Fix exit(0) on odd PC in M68KInstructionHook — a libretro core must never call exit() - Add SRAM test step to regression-test CI workflow Co-Authored-By: Claude Opus 4.6 <[email protected]>
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‎.github/workflows/regression-test.yml‎

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@@ -77,6 +77,9 @@ jobs:
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chmod +x "${MINIRETRO_BIN}"
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./test/regression_test.sh ./${{ matrix.config.core }}
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- name: Run SRAM interface tests
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run: ./test/sram_test.sh ./${{ matrix.config.core }}
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- name: Upload diff artifacts
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if: failure()
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uses: actions/upload-artifact@v4

‎src/jaguar.c‎

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@@ -172,7 +172,7 @@ void M68KInstructionHook(void)
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pcQPtr &= 0x3FF;
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if (m68kPC & 0x01) // Oops! We're fetching an odd address!
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exit(0);
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return;
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}
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/* Custom UAE 68000 read/write/IRQ functions */

‎test/sram_test.sh‎

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#!/usr/bin/env bash
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#
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# SRAM interface test for virtualjaguar-libretro
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#
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# Generates a test ROM that writes known EEPROM values, then verifies
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# the libretro SRAM interface works correctly (pack/unpack/round-trip).
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#
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# Usage: ./test/sram_test.sh <core_path>
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# Example: ./test/sram_test.sh ./virtualjaguar_libretro.so
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#
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set -euo pipefail
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CORE="${1:?Usage: $0 <core_path>}"
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SCRIPT_DIR="$(cd "$(dirname "$0")" && pwd)"
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WORK_DIR="$(mktemp -d)"
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trap 'rm -rf "${WORK_DIR}"' EXIT
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# --- Detect platform ---
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LDFLAGS=""
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BUILD_CC="${CC:-cc}"
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case "$(uname -s)" in
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Linux)
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LDFLAGS="-ldl"
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;;
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esac
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# --- Resolve core to absolute path ---
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CORE="$(cd "$(dirname "${CORE}")" && pwd)/$(basename "${CORE}")"
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# --- Build ROM generator ---
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echo "==> Building EEPROM test ROM generator..."
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${BUILD_CC} -O2 -Wall -o "${WORK_DIR}/gen_eeprom_test_rom" \
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"${SCRIPT_DIR}/tools/gen_eeprom_test_rom.c"
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# --- Generate test ROM ---
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echo "==> Generating EEPROM test ROM..."
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"${WORK_DIR}/gen_eeprom_test_rom" "${WORK_DIR}/eeprom_test.j64"
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# --- Build SRAM test harness ---
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echo "==> Building SRAM test harness..."
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${BUILD_CC} -O2 -Wall -o "${WORK_DIR}/sram_test" \
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"${SCRIPT_DIR}/tools/sram_test.c" ${LDFLAGS}
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# --- Run tests ---
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echo "==> Running SRAM tests..."
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"${WORK_DIR}/sram_test" "${CORE}" "${WORK_DIR}/eeprom_test.j64"

‎test/tools/gen_eeprom_test_rom.c‎

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/*
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* gen_eeprom_test_rom.c — Generate a minimal Atari Jaguar ROM that writes
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* known values to the EEPROM via the JERRY serial interface (NM93C14).
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*
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* The ROM writes 0xCAFE to address 0 and 0xBEEF to address 1, then loops.
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* After running for a few hundred frames, the SRAM buffer should contain
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* these values packed big-endian at the corresponding offsets.
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*
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* Build: cc -o gen_eeprom_test_rom gen_eeprom_test_rom.c
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* Usage: ./gen_eeprom_test_rom eeprom_test.j64
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*
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* Jaguar ROM layout:
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* 0x000-0x003: unused (gets overwritten by SSP in RAM)
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* 0x400-0x403: ROM flags (0x04040404)
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* 0x404-0x407: Entry point address (0x00802000)
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* 0x2000+: 68K code
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <stdint.h>
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/* Jaguar EEPROM register addresses */
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#define JERRY_EE_DI 0x00F14801 /* Data In (write bit 0) */
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#define JERRY_EE_CS 0x00F15001 /* Chip Select (write to assert) */
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/* TOM interrupt control register — writing 0 masks all interrupts */
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#define TOM_INT1 0x00F000E0 /* Interrupt control register 1 */
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/* 68K instruction encoders.
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* All instructions are word-aligned (even byte count). */
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/* MOVE.B #imm8, (abs32).L — 8 bytes */
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static void emit_move_b_imm_abs(uint8_t *buf, int *pos, uint8_t val, uint32_t addr)
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{
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buf[(*pos)++] = 0x13; buf[(*pos)++] = 0xFC;
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buf[(*pos)++] = 0x00; buf[(*pos)++] = val;
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buf[(*pos)++] = (addr >> 24) & 0xFF;
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buf[(*pos)++] = (addr >> 16) & 0xFF;
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buf[(*pos)++] = (addr >> 8) & 0xFF;
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buf[(*pos)++] = (addr >> 0) & 0xFF;
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}
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/* MOVE.W #imm16, (abs32).L — 8 bytes */
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static void emit_move_w_imm_abs(uint8_t *buf, int *pos, uint16_t val, uint32_t addr)
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{
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buf[(*pos)++] = 0x33; buf[(*pos)++] = 0xFC;
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buf[(*pos)++] = (val >> 8) & 0xFF;
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buf[(*pos)++] = val & 0xFF;
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buf[(*pos)++] = (addr >> 24) & 0xFF;
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buf[(*pos)++] = (addr >> 16) & 0xFF;
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buf[(*pos)++] = (addr >> 8) & 0xFF;
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buf[(*pos)++] = (addr >> 0) & 0xFF;
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}
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/* MOVE.L #imm32, (abs32).L — 12 bytes */
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static void emit_move_l_imm_abs(uint8_t *buf, int *pos, uint32_t val, uint32_t addr)
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{
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buf[(*pos)++] = 0x23; buf[(*pos)++] = 0xFC;
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buf[(*pos)++] = (val >> 24) & 0xFF;
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buf[(*pos)++] = (val >> 16) & 0xFF;
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buf[(*pos)++] = (val >> 8) & 0xFF;
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buf[(*pos)++] = (val >> 0) & 0xFF;
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buf[(*pos)++] = (addr >> 24) & 0xFF;
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buf[(*pos)++] = (addr >> 16) & 0xFF;
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buf[(*pos)++] = (addr >> 8) & 0xFF;
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buf[(*pos)++] = (addr >> 0) & 0xFF;
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}
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/* MOVE #imm16, SR — 4 bytes (set status register, must be in supervisor mode) */
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static void emit_move_to_sr(uint8_t *buf, int *pos, uint16_t val)
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{
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buf[(*pos)++] = 0x46; buf[(*pos)++] = 0xFC;
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buf[(*pos)++] = (val >> 8) & 0xFF;
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buf[(*pos)++] = val & 0xFF;
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}
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/* BRA.S offset (branch to self = 0x60FE for infinite loop) — 2 bytes */
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static void emit_bra_self(uint8_t *buf, int *pos)
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{
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buf[(*pos)++] = 0x60;
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buf[(*pos)++] = 0xFE;
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}
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/* Write a single bit to the EEPROM data-in register */
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static void emit_ee_di(uint8_t *buf, int *pos, int bit)
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{
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emit_move_b_imm_abs(buf, pos, bit & 1, JERRY_EE_DI);
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}
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/* Assert chip select */
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static void emit_ee_cs(uint8_t *buf, int *pos)
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{
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emit_move_b_imm_abs(buf, pos, 0x01, JERRY_EE_CS);
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}
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/*
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* Emit code to write a 16-bit value to a 6-bit EEPROM address.
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*
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* NM93C14 serial protocol:
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* 1. Assert CS (also enables writes in VJ's implementation)
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* 2. START bit: 1
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* 3. Opcode WRITE: 01
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* 4. 6-bit address (MSB first)
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* 5. 16-bit data (MSB first)
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*/
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static void emit_eeprom_write(uint8_t *buf, int *pos, uint8_t addr, uint16_t data)
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{
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int i;
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/* Assert CS — resets state machine & enables writes */
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emit_ee_cs(buf, pos);
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/* START bit */
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emit_ee_di(buf, pos, 1);
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/* Opcode: WRITE = 01 */
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emit_ee_di(buf, pos, 0);
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emit_ee_di(buf, pos, 1);
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/* 6-bit address, MSB first */
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for (i = 5; i >= 0; i--)
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emit_ee_di(buf, pos, (addr >> i) & 1);
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/* 16-bit data, MSB first */
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for (i = 15; i >= 0; i--)
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emit_ee_di(buf, pos, (data >> i) & 1);
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}
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int main(int argc, char **argv)
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{
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FILE *fp;
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uint8_t rom[0x20000]; /* 128KB ROM — minimum for JST_ROM detection */
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int code_pos, rte_addr;
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if (argc != 2)
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{
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fprintf(stderr, "Usage: %s <output.j64>\n", argv[0]);
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return 1;
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}
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memset(rom, 0xFF, sizeof(rom));
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/* ROM header at offset 0x400 */
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rom[0x400] = 0x04; rom[0x401] = 0x04;
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rom[0x402] = 0x04; rom[0x403] = 0x04;
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/* Entry point at 0x802000 (ROM offset 0x2000) */
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rom[0x404] = 0x00; rom[0x405] = 0x80;
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rom[0x406] = 0x20; rom[0x407] = 0x00;
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/* 68K code starts at ROM offset 0x2000.
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*
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* The first thing we do is set up exception vectors in RAM so that
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* any interrupt (TOM halfline, etc.) doesn't jump to random garbage.
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* We place an RTE instruction in RAM and point all vectors at it.
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*
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* We also mask TOM interrupts to prevent the halfline callback
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* from interfering before we're done writing to EEPROM. But the
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* emulator's event system runs independently of 68K interrupts,
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* so frame boundaries still work. */
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code_pos = 0x2000;
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/* Disable 68K interrupts by setting SR interrupt mask to 7 (supervisor mode).
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* SR = 0x2700: supervisor mode, interrupt mask = 7 */
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emit_move_to_sr(rom, &code_pos, 0x2700);
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/* Place an RTE instruction at a known RAM address (0x1000).
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* Then point all exception vectors (0x08-0x3FC) at it. */
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rte_addr = 0x001000;
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/* Write RTE (0x4E73) at RAM 0x1000 */
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emit_move_w_imm_abs(rom, &code_pos, 0x4E73, rte_addr);
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/* Also write a BRA.S self (0x60FE) right after as a safety net */
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emit_move_w_imm_abs(rom, &code_pos, 0x60FE, rte_addr + 2);
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/* Set critical exception vectors to point to our RTE handler.
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* Vectors 0,1 are SSP and PC (already set by boot).
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* Only set the ones that might actually fire:
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* 2: Bus error, 3: Address error, 4: Illegal instruction,
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* 24: Spurious interrupt, 25-31: Autovector interrupts */
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{
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int vecs[] = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,
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24, 25, 26, 27, 28, 29, 30, 31, -1 };
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int v;
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for (v = 0; vecs[v] >= 0; v++)
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emit_move_l_imm_abs(rom, &code_pos, rte_addr, vecs[v] * 4);
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}
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/* Now do the actual EEPROM writes */
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/* Write 0xCAFE to EEPROM address 0 */
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emit_eeprom_write(rom, &code_pos, 0x00, 0xCAFE);
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/* Write 0xBEEF to EEPROM address 1 */
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emit_eeprom_write(rom, &code_pos, 0x01, 0xBEEF);
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/* Write 0xDEAD to EEPROM address 2 */
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emit_eeprom_write(rom, &code_pos, 0x02, 0xDEAD);
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/* Write 0x1234 to EEPROM address 63 (last address) */
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emit_eeprom_write(rom, &code_pos, 0x3F, 0x1234);
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/* Infinite loop */
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emit_bra_self(rom, &code_pos);
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if (code_pos > (int)sizeof(rom))
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{
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fprintf(stderr, "ERROR: code too large (%d bytes, max %d)\n",
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code_pos, (int)sizeof(rom));
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return 1;
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}
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/* Write ROM file */
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fp = fopen(argv[1], "wb");
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if (!fp)
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{
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perror("fopen");
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return 1;
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}
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fwrite(rom, 1, sizeof(rom), fp);
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fclose(fp);
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printf("Generated %s (%d bytes, code ends at offset 0x%04X)\n",
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argv[1], (int)sizeof(rom), code_pos);
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return 0;
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}

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