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ioctl.c
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2550 lines (2211 loc) · 64.9 KB
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// SPDX-License-Identifier: LGPL-2.1-or-later
/*
* This file is part of libnvme.
* Copyright (c) 2020 Western Digital Corporation or its affiliates.
*
* Authors: Keith Busch <[email protected]>
* Chaitanya Kulkarni <[email protected]>
*/
#include <errno.h>
#include <fcntl.h>
#ifdef CONFIG_LIBURING
#include <liburing.h>
#endif
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <inttypes.h>
#include <sys/ioctl.h>
#include <sys/stat.h>
#include <sys/time.h>
#include <ccan/build_assert/build_assert.h>
#include <ccan/ccan/minmax/minmax.h>
#include <ccan/endian/endian.h>
#include "ioctl.h"
#include "util.h"
#include "log.h"
static int nvme_verify_chr(int fd)
{
static struct stat nvme_stat;
int err = fstat(fd, &nvme_stat);
if (err < 0)
return errno;
if (!S_ISCHR(nvme_stat.st_mode)) {
errno = ENOTBLK;
return -1;
}
return 0;
}
int nvme_subsystem_reset(int fd)
{
int ret;
ret = nvme_verify_chr(fd);
if (ret)
return ret;
return ioctl(fd, NVME_IOCTL_SUBSYS_RESET);
}
int nvme_ctrl_reset(int fd)
{
int ret;
ret = nvme_verify_chr(fd);
if (ret)
return ret;
return ioctl(fd, NVME_IOCTL_RESET);
}
int nvme_ns_rescan(int fd)
{
int ret;
ret = nvme_verify_chr(fd);
if (ret)
return ret;
return ioctl(fd, NVME_IOCTL_RESCAN);
}
int nvme_get_nsid(int fd, __u32 *nsid)
{
errno = 0;
*nsid = ioctl(fd, NVME_IOCTL_ID);
return -1 * (errno != 0);
}
__attribute__((weak))
int nvme_submit_passthru64(int fd, unsigned long ioctl_cmd,
struct nvme_passthru_cmd64 *cmd,
__u64 *result)
{
int err = ioctl(fd, ioctl_cmd, cmd);
if (err >= 0 && result)
*result = cmd->result;
return err;
}
__attribute__((weak))
int nvme_submit_passthru(int fd, unsigned long ioctl_cmd,
struct nvme_passthru_cmd *cmd, __u32 *result)
{
int err = ioctl(fd, ioctl_cmd, cmd);
if (err >= 0 && result)
*result = cmd->result;
return err;
}
static int nvme_passthru64(int fd, unsigned long ioctl_cmd, __u8 opcode,
__u8 flags, __u16 rsvd, __u32 nsid, __u32 cdw2,
__u32 cdw3, __u32 cdw10, __u32 cdw11, __u32 cdw12,
__u32 cdw13, __u32 cdw14, __u32 cdw15,
__u32 data_len, void *data, __u32 metadata_len,
void *metadata, __u32 timeout_ms, __u64 *result)
{
struct nvme_passthru_cmd64 cmd = {
.opcode = opcode,
.flags = flags,
.rsvd1 = rsvd,
.nsid = nsid,
.cdw2 = cdw2,
.cdw3 = cdw3,
.metadata = (__u64)(uintptr_t)metadata,
.addr = (__u64)(uintptr_t)data,
.metadata_len = metadata_len,
.data_len = data_len,
.cdw10 = cdw10,
.cdw11 = cdw11,
.cdw12 = cdw12,
.cdw13 = cdw13,
.cdw14 = cdw14,
.cdw15 = cdw15,
.timeout_ms = timeout_ms,
};
return nvme_submit_passthru64(fd, ioctl_cmd, &cmd, result);
}
static int nvme_passthru(int fd, unsigned long ioctl_cmd, __u8 opcode,
__u8 flags, __u16 rsvd, __u32 nsid, __u32 cdw2,
__u32 cdw3, __u32 cdw10, __u32 cdw11, __u32 cdw12,
__u32 cdw13, __u32 cdw14, __u32 cdw15, __u32 data_len,
void *data, __u32 metadata_len, void *metadata,
__u32 timeout_ms, __u32 *result)
{
struct nvme_passthru_cmd cmd = {
.opcode = opcode,
.flags = flags,
.rsvd1 = rsvd,
.nsid = nsid,
.cdw2 = cdw2,
.cdw3 = cdw3,
.metadata = (__u64)(uintptr_t)metadata,
.addr = (__u64)(uintptr_t)data,
.metadata_len = metadata_len,
.data_len = data_len,
.cdw10 = cdw10,
.cdw11 = cdw11,
.cdw12 = cdw12,
.cdw13 = cdw13,
.cdw14 = cdw14,
.cdw15 = cdw15,
.timeout_ms = timeout_ms,
};
return nvme_submit_passthru(fd, ioctl_cmd, &cmd, result);
}
int nvme_submit_admin_passthru64(int fd, struct nvme_passthru_cmd64 *cmd,
__u64 *result)
{
return nvme_submit_passthru64(fd, NVME_IOCTL_ADMIN64_CMD, cmd, result);
}
int nvme_admin_passthru64(int fd, __u8 opcode, __u8 flags, __u16 rsvd,
__u32 nsid, __u32 cdw2, __u32 cdw3, __u32 cdw10,
__u32 cdw11, __u32 cdw12, __u32 cdw13, __u32 cdw14,
__u32 cdw15, __u32 data_len, void *data,
__u32 metadata_len, void *metadata, __u32 timeout_ms,
__u64 *result)
{
return nvme_passthru64(fd, NVME_IOCTL_ADMIN64_CMD, opcode, flags, rsvd,
nsid, cdw2, cdw3, cdw10, cdw11, cdw12, cdw13,
cdw14, cdw15, data_len, data, metadata_len,
metadata, timeout_ms, result);
}
int nvme_submit_admin_passthru(int fd, struct nvme_passthru_cmd *cmd, __u32 *result)
{
return nvme_submit_passthru(fd, NVME_IOCTL_ADMIN_CMD, cmd, result);
}
int nvme_admin_passthru(int fd, __u8 opcode, __u8 flags, __u16 rsvd,
__u32 nsid, __u32 cdw2, __u32 cdw3, __u32 cdw10,
__u32 cdw11, __u32 cdw12, __u32 cdw13, __u32 cdw14,
__u32 cdw15, __u32 data_len, void *data,
__u32 metadata_len, void *metadata, __u32 timeout_ms,
__u32 *result)
{
return nvme_passthru(fd, NVME_IOCTL_ADMIN_CMD, opcode, flags, rsvd,
nsid, cdw2, cdw3, cdw10, cdw11, cdw12, cdw13,
cdw14, cdw15, data_len, data, metadata_len,
metadata, timeout_ms, result);
}
enum features {
NVME_FEATURES_ARBITRATION_BURST_SHIFT = 0,
NVME_FEATURES_ARBITRATION_LPW_SHIFT = 8,
NVME_FEATURES_ARBITRATION_MPW_SHIFT = 16,
NVME_FEATURES_ARBITRATION_HPW_SHIFT = 24,
NVME_FEATURES_ARBITRATION_BURST_MASK = 0x7,
NVME_FEATURES_ARBITRATION_LPW_MASK = 0xff,
NVME_FEATURES_ARBITRATION_MPW_MASK = 0xff,
NVME_FEATURES_ARBITRATION_HPW_MASK = 0xff,
NVME_FEATURES_PWRMGMT_PS_SHIFT = 0,
NVME_FEATURES_PWRMGMT_WH_SHIFT = 5,
NVME_FEATURES_PWRMGMT_PS_MASK = 0x1f,
NVME_FEATURES_PWRMGMT_WH_MASK = 0x7,
NVME_FEATURES_TMPTH_SHIFT = 0,
NVME_FEATURES_TMPSEL_SHIFT = 16,
NVME_FEATURES_THSEL_SHIFT = 20,
NVME_FEATURES_TMPTH_MASK = 0xff,
NVME_FEATURES_TMPSEL_MASK = 0xf,
NVME_FEATURES_THSEL_MASK = 0x3,
NVME_FEATURES_ERROR_RECOVERY_TLER_SHIFT = 0,
NVME_FEATURES_ERROR_RECOVERY_DULBE_SHIFT = 16,
NVME_FEATURES_ERROR_RECOVERY_TLER_MASK = 0xff,
NVME_FEATURES_ERROR_RECOVERY_DULBE_MASK = 0x1,
NVME_FEATURES_VWC_WCE_SHIFT = 0,
NVME_FEATURES_VWC_WCE_MASK = 0x1,
NVME_FEATURES_IRQC_THR_SHIFT = 0,
NVME_FEATURES_IRQC_TIME_SHIFT = 8,
NVME_FEATURES_IRQC_THR_MASK = 0xff,
NVME_FEATURES_IRQC_TIME_MASK = 0xff,
NVME_FEATURES_IVC_IV_SHIFT = 0,
NVME_FEATURES_IVC_CD_SHIFT = 16,
NVME_FEATURES_IVC_IV_MASK = 0xffff,
NVME_FEATURES_IVC_CD_MASK = 0x1,
NVME_FEATURES_WAN_DN_SHIFT = 0,
NVME_FEATURES_WAN_DN_MASK = 0x1,
NVME_FEATURES_APST_APSTE_SHIFT = 0,
NVME_FEATURES_APST_APSTE_MASK = 0x1,
NVME_FEATURES_HCTM_TMT2_SHIFT = 0,
NVME_FEATURES_HCTM_TMT1_SHIFT = 16,
NVME_FEATURES_HCTM_TMT2_MASK = 0xffff,
NVME_FEATURES_HCTM_TMT1_MASK = 0xffff,
NVME_FEATURES_NOPS_NOPPME_SHIFT = 0,
NVME_FEATURES_NOPS_NOPPME_MASK = 0x1,
NVME_FEATURES_PLM_PLE_SHIFT = 0,
NVME_FEATURES_PLM_PLE_MASK = 0x1,
NVME_FEATURES_PLM_WINDOW_SELECT_SHIFT = 0,
NVME_FEATURES_PLM_WINDOW_SELECT_MASK = 0xf,
NVME_FEATURES_LBAS_LSIRI_SHIFT = 0,
NVME_FEATURES_LBAS_LSIPI_SHIFT = 16,
NVME_FEATURES_LBAS_LSIRI_MASK = 0xffff,
NVME_FEATURES_LBAS_LSIPI_MASK = 0xffff,
NVME_FEATURES_IOCSP_IOCSCI_SHIFT = 0,
NVME_FEATURES_IOCSP_IOCSCI_MASK = 0xff,
};
int nvme_identify(struct nvme_identify_args *args)
{
__u32 cdw10 = NVME_SET(args->cntid, IDENTIFY_CDW10_CNTID) |
NVME_SET(args->cns, IDENTIFY_CDW10_CNS);
__u32 cdw11 = NVME_SET(args->cns_specific_id, IDENTIFY_CDW11_CNSSPECID) |
NVME_SET(args->csi, IDENTIFY_CDW11_CSI);
__u32 cdw14 = NVME_SET(args->uuidx, IDENTIFY_CDW14_UUID);
struct nvme_passthru_cmd cmd = {
.opcode = nvme_admin_identify,
.nsid = args->nsid,
.addr = (__u64)(uintptr_t)args->data,
.data_len = NVME_IDENTIFY_DATA_SIZE,
.cdw10 = cdw10,
.cdw11 = cdw11,
.cdw14 = cdw14,
.timeout_ms = args->timeout,
};
if (args->args_size < sizeof(*args)) {
errno = EINVAL;
return -1;
}
return nvme_submit_admin_passthru(args->fd, &cmd, args->result);
}
int nvme_get_log(struct nvme_get_log_args *args)
{
__u32 numd = (args->len >> 2) - 1;
__u16 numdu = numd >> 16, numdl = numd & 0xffff;
__u32 cdw10 = NVME_SET(args->lid, LOG_CDW10_LID) |
NVME_SET(args->lsp, LOG_CDW10_LSP) |
NVME_SET(!!args->rae, LOG_CDW10_RAE) |
NVME_SET(numdl, LOG_CDW10_NUMDL);
__u32 cdw11 = NVME_SET(numdu, LOG_CDW11_NUMDU) |
NVME_SET(args->lsi, LOG_CDW11_LSI);
__u32 cdw12 = args->lpo & 0xffffffff;
__u32 cdw13 = args->lpo >> 32;
__u32 cdw14 = NVME_SET(args->uuidx, LOG_CDW14_UUID) |
NVME_SET(!!args->ot, LOG_CDW14_OT) |
NVME_SET(args->csi, LOG_CDW14_CSI);
struct nvme_passthru_cmd cmd = {
.opcode = nvme_admin_get_log_page,
.nsid = args->nsid,
.addr = (__u64)(uintptr_t)args->log,
.data_len = args->len,
.cdw10 = cdw10,
.cdw11 = cdw11,
.cdw12 = cdw12,
.cdw13 = cdw13,
.cdw14 = cdw14,
.timeout_ms = args->timeout,
};
if (args->args_size < sizeof(struct nvme_get_log_args)) {
errno = EINVAL;
return -1;
}
return nvme_submit_admin_passthru(args->fd, &cmd, args->result);
}
#ifdef CONFIG_LIBURING
enum {
IO_URING_NOT_AVAILABLE,
IO_URING_AVAILABLE,
} io_uring_kernel_support = IO_URING_NOT_AVAILABLE;
/*
* gcc specific attribute, call automatically on the library loading.
* if IORING_OP_URING_CMD is not supported, fallback to ioctl interface.
*/
__attribute__((constructor))
static void nvme_uring_cmd_probe()
{
struct io_uring_probe *probe = io_uring_get_probe();
if (!probe)
return;
if (!io_uring_opcode_supported(probe, IORING_OP_URING_CMD))
return;
io_uring_kernel_support = IO_URING_AVAILABLE;
}
static int nvme_uring_cmd_setup(struct io_uring *ring)
{
return io_uring_queue_init(NVME_URING_ENTRIES, ring,
IORING_SETUP_SQE128 | IORING_SETUP_CQE32);
}
static void nvme_uring_cmd_exit(struct io_uring *ring)
{
io_uring_queue_exit(ring);
}
static int nvme_uring_cmd_admin_passthru_async(struct io_uring *ring, struct nvme_get_log_args *args)
{
struct io_uring_sqe *sqe;
struct nvme_uring_cmd *cmd;
int ret;
__u32 numd = (args->len >> 2) - 1;
__u16 numdu = numd >> 16, numdl = numd & 0xffff;
__u32 cdw10 = NVME_SET(args->lid, LOG_CDW10_LID) |
NVME_SET(args->lsp, LOG_CDW10_LSP) |
NVME_SET(!!args->rae, LOG_CDW10_RAE) |
NVME_SET(numdl, LOG_CDW10_NUMDL);
__u32 cdw11 = NVME_SET(numdu, LOG_CDW11_NUMDU) |
NVME_SET(args->lsi, LOG_CDW11_LSI);
__u32 cdw12 = args->lpo & 0xffffffff;
__u32 cdw13 = args->lpo >> 32;
__u32 cdw14 = NVME_SET(args->uuidx, LOG_CDW14_UUID) |
NVME_SET(!!args->ot, LOG_CDW14_OT) |
NVME_SET(args->csi, LOG_CDW14_CSI);
if (args->args_size < sizeof(struct nvme_get_log_args)) {
errno = EINVAL;
return -1;
}
sqe = io_uring_get_sqe(ring);
if (!sqe)
return -1;
cmd = (void *)&sqe->cmd;
cmd->opcode = nvme_admin_get_log_page,
cmd->nsid = args->nsid,
cmd->addr = (__u64)(uintptr_t)args->log,
cmd->data_len = args->len,
cmd->cdw10 = cdw10,
cmd->cdw11 = cdw11,
cmd->cdw12 = cdw12,
cmd->cdw13 = cdw13,
cmd->cdw14 = cdw14,
cmd->timeout_ms = args->timeout,
sqe->fd = args->fd;
sqe->opcode = IORING_OP_URING_CMD;
sqe->cmd_op = NVME_URING_CMD_ADMIN;
sqe->user_data = (__u64)(uintptr_t)args;
ret = io_uring_submit(ring);
if (ret < 0) {
errno = -ret;
return -1;
}
return 0;
}
static int nvme_uring_cmd_wait_complete(struct io_uring *ring, int n)
{
struct nvme_get_log_args *args;
struct io_uring_cqe *cqe;
int i, ret = 0;
for (i = 0; i < n; i++) {
ret = io_uring_wait_cqe(ring, &cqe);
if (ret) {
errno = -ret;
return -1;
}
if (cqe->res) {
args = (struct nvme_get_log_args *)cqe->user_data;
if (args->result)
*args->result = cqe->res;
ret = cqe->res;
break;
}
io_uring_cqe_seen(ring, cqe);
}
return ret;
}
#endif
int nvme_get_log_page(int fd, __u32 xfer_len, struct nvme_get_log_args *args)
{
__u64 offset = 0, xfer, data_len = args->len;
__u64 start = args->lpo;
bool retain = args->rae;
void *ptr = args->log;
int ret;
args->fd = fd;
#ifdef CONFIG_LIBURING
int n = 0;
struct io_uring ring;
if (io_uring_kernel_support == IO_URING_AVAILABLE) {
if (nvme_uring_cmd_setup(&ring))
return -1;
}
#endif
/*
* 4k is the smallest possible transfer unit, so restricting to 4k
* avoids having to check the MDTS value of the controller.
*/
do {
xfer = data_len - offset;
if (xfer > xfer_len)
xfer = xfer_len;
/*
* Always retain regardless of the RAE parameter until the very
* last portion of this log page so the data remains latched
* during the fetch sequence.
*/
args->lpo = start + offset;
args->len = xfer;
args->log = ptr;
args->rae = offset + xfer < data_len || retain;
#ifdef CONFIG_LIBURING
if (io_uring_kernel_support == IO_URING_AVAILABLE) {
if (n >= NVME_URING_ENTRIES) {
ret = nvme_uring_cmd_wait_complete(&ring, n);
n = 0;
}
n += 1;
ret = nvme_uring_cmd_admin_passthru_async(&ring, args);
if (ret)
nvme_uring_cmd_exit(&ring);
} else
#endif
ret = nvme_get_log(args);
if (ret)
return ret;
offset += xfer;
ptr += xfer;
} while (offset < data_len);
#ifdef CONFIG_LIBURING
if (io_uring_kernel_support == IO_URING_AVAILABLE) {
ret = nvme_uring_cmd_wait_complete(&ring, n);
nvme_uring_cmd_exit(&ring);
if (ret)
return ret;
}
#endif
return 0;
}
static int read_ana_chunk(int fd, enum nvme_log_ana_lsp lsp, bool rae,
__u8 *log, __u8 **read, __u8 *to_read, __u8 *log_end)
{
if (to_read > log_end) {
errno = ENOSPC;
return -1;
}
while (*read < to_read) {
__u32 len = min_t(__u32, log_end - *read, NVME_LOG_PAGE_PDU_SIZE);
int ret;
ret = nvme_get_log_ana(fd, lsp, rae, *read - log, len, *read);
if (ret)
return ret;
*read += len;
}
return 0;
}
static int try_read_ana(int fd, enum nvme_log_ana_lsp lsp, bool rae,
struct nvme_ana_log *log, __u8 *log_end,
__u8 *read, __u8 **to_read, bool *may_retry)
{
__u16 ngrps = le16_to_cpu(log->ngrps);
while (ngrps--) {
__u8 *group = *to_read;
int ret;
__le32 nnsids;
*to_read += sizeof(*log->descs);
ret = read_ana_chunk(fd, lsp, rae,
(__u8 *)log, &read, *to_read, log_end);
if (ret) {
/*
* If the provided buffer isn't long enough,
* the log page may have changed while reading it
* and the computed length was inaccurate.
* Have the caller check chgcnt and retry.
*/
*may_retry = errno == ENOSPC;
return ret;
}
/*
* struct nvme_ana_group_desc has 8-byte alignment
* but the group pointer is only 4-byte aligned.
* Don't dereference the misaligned pointer.
*/
memcpy(&nnsids,
group + offsetof(struct nvme_ana_group_desc, nnsids),
sizeof(nnsids));
*to_read += le32_to_cpu(nnsids) * sizeof(__le32);
ret = read_ana_chunk(fd, lsp, rae,
(__u8 *)log, &read, *to_read, log_end);
if (ret) {
*may_retry = errno == ENOSPC;
return ret;
}
}
*may_retry = true;
return 0;
}
int nvme_get_ana_log_atomic(int fd, bool rgo, bool rae, unsigned int retries,
struct nvme_ana_log *log, __u32 *len)
{
const enum nvme_log_ana_lsp lsp =
rgo ? NVME_LOG_ANA_LSP_RGO_GROUPS_ONLY : 0;
/* Get Log Page can only fetch multiples of dwords */
__u8 * const log_end = (__u8 *)log + (*len & -4);
__u8 *read = (__u8 *)log;
__u8 *to_read;
int ret;
if (!retries) {
errno = EINVAL;
return -1;
}
to_read = (__u8 *)log->descs;
ret = read_ana_chunk(fd, lsp, rae,
(__u8 *)log, &read, to_read, log_end);
if (ret)
return ret;
do {
bool may_retry = false;
int saved_ret;
int saved_errno;
__le64 chgcnt;
saved_ret = try_read_ana(fd, lsp, rae, log, log_end,
read, &to_read, &may_retry);
/*
* If the log page was read with multiple Get Log Page commands,
* chgcnt must be checked afterwards to ensure atomicity
*/
*len = to_read - (__u8 *)log;
if (*len <= NVME_LOG_PAGE_PDU_SIZE || !may_retry)
return saved_ret;
saved_errno = errno;
chgcnt = log->chgcnt;
read = (__u8 *)log;
to_read = (__u8 *)log->descs;
ret = read_ana_chunk(fd, lsp, rae,
(__u8 *)log, &read, to_read, log_end);
if (ret)
return ret;
if (log->chgcnt == chgcnt) {
/* Log hasn't changed; return try_read_ana() result */
errno = saved_errno;
return saved_ret;
}
} while (--retries);
errno = EAGAIN;
return -1;
}
int nvme_set_features(struct nvme_set_features_args *args)
{
__u32 cdw10 = NVME_SET(args->fid, FEATURES_CDW10_FID) |
NVME_SET(!!args->save, SET_FEATURES_CDW10_SAVE);
__u32 cdw14 = NVME_SET(args->uuidx, FEATURES_CDW14_UUID);
struct nvme_passthru_cmd cmd = {
.opcode = nvme_admin_set_features,
.nsid = args->nsid,
.addr = (__u64)(uintptr_t)args->data,
.data_len = args->data_len,
.cdw10 = cdw10,
.cdw11 = args->cdw11,
.cdw12 = args->cdw12,
.cdw13 = args->cdw13,
.cdw14 = cdw14,
.cdw15 = args->cdw15,
.timeout_ms = args->timeout,
};
if (args->args_size < sizeof(*args)) {
errno = EINVAL;
return -1;
}
return nvme_submit_admin_passthru(args->fd, &cmd, args->result);
}
static int __nvme_set_features(int fd, __u8 fid, __u32 cdw11, bool save,
__u32 *result)
{
struct nvme_set_features_args args = {
.args_size = sizeof(args),
.fd = fd,
.fid = fid,
.nsid = NVME_NSID_NONE,
.cdw11 = cdw11,
.cdw12 = 0,
.save = save,
.uuidx = NVME_UUID_NONE,
.cdw15 = 0,
.data_len = 0,
.data = NULL,
.timeout = NVME_DEFAULT_IOCTL_TIMEOUT,
.result = result,
};
return nvme_set_features(&args);
}
int nvme_set_features_arbitration(int fd, __u8 ab, __u8 lpw, __u8 mpw,
__u8 hpw, bool save, __u32 *result)
{
__u32 value = NVME_SET(ab, FEAT_ARBITRATION_BURST) |
NVME_SET(lpw, FEAT_ARBITRATION_LPW) |
NVME_SET(mpw, FEAT_ARBITRATION_MPW) |
NVME_SET(hpw, FEAT_ARBITRATION_HPW);
return __nvme_set_features(fd, NVME_FEAT_FID_ARBITRATION, value, save,
result);
}
int nvme_set_features_power_mgmt(int fd, __u8 ps, __u8 wh, bool save,
__u32 *result)
{
__u32 value = NVME_SET(ps, FEAT_PWRMGMT_PS) |
NVME_SET(wh, FEAT_PWRMGMT_WH);
return __nvme_set_features(fd, NVME_FEAT_FID_POWER_MGMT, value, save,
result);
}
int nvme_set_features_lba_range(int fd, __u32 nsid, __u8 nr_ranges, bool save,
struct nvme_lba_range_type *data, __u32 *result)
{
return nvme_set_features_data(
fd, NVME_FEAT_FID_LBA_RANGE, nsid, nr_ranges - 1, save,
sizeof(*data), data, result);
}
int nvme_set_features_temp_thresh(int fd, __u16 tmpth, __u8 tmpsel,
enum nvme_feat_tmpthresh_thsel thsel,
bool save, __u32 *result)
{
__u32 value = NVME_SET(tmpth, FEAT_TT_TMPTH) |
NVME_SET(tmpsel, FEAT_TT_TMPSEL) |
NVME_SET(thsel, FEAT_TT_THSEL);
return __nvme_set_features(fd, NVME_FEAT_FID_TEMP_THRESH, value, save,
result);
}
int nvme_set_features_temp_thresh2(int fd, __u16 tmpth, __u8 tmpsel,
enum nvme_feat_tmpthresh_thsel thsel, __u8 tmpthh,
bool save, __u32 *result)
{
__u32 value = NVME_SET(tmpth, FEAT_TT_TMPTH) |
NVME_SET(tmpsel, FEAT_TT_TMPSEL) |
NVME_SET(thsel, FEAT_TT_THSEL) |
NVME_SET(tmpthh, FEAT_TT_TMPTHH);
return __nvme_set_features(fd, NVME_FEAT_FID_TEMP_THRESH, value, save,
result);
}
int nvme_set_features_err_recovery(int fd, __u32 nsid, __u16 tler, bool dulbe,
bool save, __u32 *result)
{
__u32 value = NVME_SET(tler, FEAT_ERROR_RECOVERY_TLER) |
NVME_SET(!!dulbe, FEAT_ERROR_RECOVERY_DULBE);
return nvme_set_features_simple(
fd, NVME_FEAT_FID_ERR_RECOVERY, nsid, value, save, result);
}
int nvme_set_features_volatile_wc(int fd, bool wce, bool save, __u32 *result)
{
__u32 value = NVME_SET(!!wce, FEAT_VWC_WCE);
return __nvme_set_features(fd, NVME_FEAT_FID_VOLATILE_WC, value, save,
result);
}
int nvme_set_features_irq_coalesce(int fd, __u8 thr, __u8 time, bool save,
__u32 *result)
{
__u32 value = NVME_SET(thr, FEAT_IRQC_THR) |
NVME_SET(time, FEAT_IRQC_TIME);
return __nvme_set_features(fd, NVME_FEAT_FID_IRQ_COALESCE, value, save,
result);
}
int nvme_set_features_irq_config(int fd, __u16 iv, bool cd, bool save,
__u32 *result)
{
__u32 value = NVME_SET(iv, FEAT_ICFG_IV) |
NVME_SET(!!cd, FEAT_ICFG_CD);
return __nvme_set_features(fd, NVME_FEAT_FID_IRQ_CONFIG, value, save,
result);
}
int nvme_set_features_write_atomic(int fd, bool dn, bool save, __u32 *result)
{
__u32 value = NVME_SET(!!dn, FEAT_WA_DN);
return __nvme_set_features(fd, NVME_FEAT_FID_WRITE_ATOMIC, value, save,
result);
}
int nvme_set_features_async_event(int fd, __u32 events,
bool save, __u32 *result)
{
return __nvme_set_features(fd, NVME_FEAT_FID_ASYNC_EVENT, events, save,
result);
}
int nvme_set_features_auto_pst(int fd, bool apste, bool save,
struct nvme_feat_auto_pst *apst, __u32 *result)
{
return nvme_set_features_data(fd, NVME_FEAT_FID_AUTO_PST,
NVME_NSID_NONE, NVME_SET(!!apste, FEAT_APST_APSTE), save,
sizeof(*apst), apst, result);
}
int nvme_set_features_timestamp(int fd, bool save, __u64 timestamp)
{
__le64 t = cpu_to_le64(timestamp);
struct nvme_timestamp ts = {};
memcpy(ts.timestamp, &t, sizeof(ts.timestamp));
return nvme_set_features_data(fd, NVME_FEAT_FID_TIMESTAMP,
NVME_NSID_NONE, 0, save, sizeof(ts), &ts, NULL);
}
int nvme_set_features_hctm(int fd, __u16 tmt2, __u16 tmt1,
bool save, __u32 *result)
{
__u32 value = NVME_SET(tmt2, FEAT_HCTM_TMT2) |
NVME_SET(tmt1, FEAT_HCTM_TMT1);
return __nvme_set_features(fd, NVME_FEAT_FID_HCTM, value, save,
result);
}
int nvme_set_features_nopsc(int fd, bool noppme, bool save, __u32 *result)
{
__u32 value = NVME_SET(noppme, FEAT_NOPS_NOPPME);
return __nvme_set_features(fd, NVME_FEAT_FID_NOPSC, value, save,
result);
}
int nvme_set_features_rrl(int fd, __u8 rrl, __u16 nvmsetid,
bool save, __u32 *result)
{
struct nvme_set_features_args args = {
.args_size = sizeof(args),
.fd = fd,
.fid = NVME_FEAT_FID_RRL,
.nsid = NVME_NSID_NONE,
.cdw11 = nvmsetid,
.cdw12 = rrl,
.save = save,
.uuidx = NVME_UUID_NONE,
.cdw15 = 0,
.data_len = 0,
.data = NULL,
.timeout = NVME_DEFAULT_IOCTL_TIMEOUT,
.result = result,
};
return nvme_set_features(&args);
}
int nvme_set_features_plm_config(int fd, bool plm, __u16 nvmsetid, bool save,
struct nvme_plm_config *data, __u32 *result)
{
struct nvme_set_features_args args = {
.args_size = sizeof(args),
.fd = fd,
.fid = NVME_FEAT_FID_PLM_CONFIG,
.nsid = NVME_NSID_NONE,
.cdw11 = nvmsetid,
.cdw12 = !!plm,
.save = save,
.uuidx = NVME_UUID_NONE,
.cdw15 = 0,
.data_len = sizeof(*data),
.data = data,
.timeout = NVME_DEFAULT_IOCTL_TIMEOUT,
.result = result,
};
return nvme_set_features(&args);
}
int nvme_set_features_plm_window(int fd, enum nvme_feat_plm_window_select sel,
__u16 nvmsetid, bool save, __u32 *result)
{
__u32 cdw12 = NVME_SET(sel, FEAT_PLMW_WS);
struct nvme_set_features_args args = {
.args_size = sizeof(args),
.fd = fd,
.fid = NVME_FEAT_FID_PLM_WINDOW,
.nsid = NVME_NSID_NONE,
.cdw11 = nvmsetid,
.cdw12 = cdw12,
.save = save,
.uuidx = NVME_UUID_NONE,
.cdw15 = 0,
.data_len = 0,
.data = NULL,
.timeout = NVME_DEFAULT_IOCTL_TIMEOUT,
.result = result,
};
return nvme_set_features(&args);
}
int nvme_set_features_lba_sts_interval(int fd, __u16 lsiri, __u16 lsipi,
bool save, __u32 *result)
{
__u32 value = NVME_SET(lsiri, FEAT_LBAS_LSIRI) |
NVME_SET(lsipi, FEAT_LBAS_LSIPI);
return __nvme_set_features(fd, NVME_FEAT_FID_LBA_STS_INTERVAL, value,
save, result);
}
int nvme_set_features_host_behavior(int fd, bool save,
struct nvme_feat_host_behavior *data)
{
return nvme_set_features_data(fd, NVME_FEAT_FID_HOST_BEHAVIOR,
NVME_NSID_NONE, 0, false, sizeof(*data), data, NULL);
}
int nvme_set_features_sanitize(int fd, bool nodrm, bool save, __u32 *result)
{
return __nvme_set_features(fd, NVME_FEAT_FID_SANITIZE, !!nodrm, save,
result);
}
int nvme_set_features_endurance_evt_cfg(int fd, __u16 endgid, __u8 egwarn,
bool save, __u32 *result)
{
__u32 value = endgid | egwarn << 16;
return __nvme_set_features(fd, NVME_FEAT_FID_ENDURANCE_EVT_CFG, value,
save, result);
}
int nvme_set_features_sw_progress(int fd, __u8 pbslc, bool save,
__u32 *result)
{
return __nvme_set_features(fd, NVME_FEAT_FID_SW_PROGRESS, pbslc, save,
result);
}
int nvme_set_features_host_id(int fd, bool exhid, bool save, __u8 *hostid)
{
__u32 len = exhid ? 16 : 8;
__u32 value = !!exhid;
return nvme_set_features_data(fd, NVME_FEAT_FID_HOST_ID,
NVME_NSID_NONE, value, save, len, hostid, NULL);
}
int nvme_set_features_resv_mask(int fd, __u32 mask, bool save, __u32 *result)
{
return __nvme_set_features(fd, NVME_FEAT_FID_RESV_MASK, mask, save,
result);
}
int nvme_set_features_resv_mask2(int fd, __u32 nsid, __u32 mask, bool save,
__u32 *result)
{
return nvme_set_features_simple(
fd, NVME_FEAT_FID_RESV_MASK, nsid, mask, save, result);
}
int nvme_set_features_resv_persist(int fd, bool ptpl, bool save, __u32 *result)
{
return __nvme_set_features(fd, NVME_FEAT_FID_RESV_PERSIST, !!ptpl, save,
result);
}
int nvme_set_features_resv_persist2(int fd, __u32 nsid, bool ptpl, bool save,
__u32 *result)
{
return nvme_set_features_simple(
fd, NVME_FEAT_FID_RESV_PERSIST, nsid, !!ptpl, save, result);
}
int nvme_set_features_write_protect(int fd, enum nvme_feat_nswpcfg_state state,
bool save, __u32 *result)
{
return __nvme_set_features(fd, NVME_FEAT_FID_WRITE_PROTECT, state,
false, result);
}
int nvme_set_features_write_protect2(int fd, __u32 nsid,
enum nvme_feat_nswpcfg_state state,
bool save, __u32 *result)
{
return nvme_set_features_simple(
fd, NVME_FEAT_FID_WRITE_PROTECT, nsid, state, false, result);
}
int nvme_set_features_iocs_profile(int fd, __u16 iocsi, bool save)
{
__u32 value = NVME_SET(iocsi, FEAT_IOCSP_IOCSCI);
return __nvme_set_features(fd, NVME_FEAT_FID_IOCS_PROFILE, value,
save, NULL);
}
int nvme_get_features(struct nvme_get_features_args *args)
{
__u32 cdw10 = NVME_SET(args->fid, FEATURES_CDW10_FID) |
NVME_SET(args->sel, GET_FEATURES_CDW10_SEL);
__u32 cdw14 = NVME_SET(args->uuidx, FEATURES_CDW14_UUID);
struct nvme_passthru_cmd cmd = {
.opcode = nvme_admin_get_features,
.nsid = args->nsid,
.addr = (__u64)(uintptr_t)args->data,