drm/asahi: Implement ASAHI_BIND_SINGLE_PAGE (mmu/pgtbl)

Signed-off-by: Asahi Lina <[email protected]>

Author: jannau

drivers/gpu/drm/asahi/mmu.rs

@@ -229,6 +229,8 @@ impl gpuvm::DriverGpuVm for VmInner {
 
         let bo = ctx.vm_bo.as_ref().expect("step_map with no BO");
 
+        let one_page = op.flags().contains(gpuvm::GpuVaFlags::REPEAT);
+
         let guard = bo.inner().sgt.lock();
         for range in guard.as_ref().expect("step_map with no SGT").iter() {
             // TODO: proper DMA address/length handling
@@ -252,18 +254,27 @@ impl gpuvm::DriverGpuVm for VmInner {
 
             assert!(offset == 0);
 
-            len = len.min(left);
+            if one_page {
+                len = left;
+            } else {
+                len = len.min(left);
+            }
 
             mod_dev_dbg!(
                 self.dev,
-                "MMU: map: {:#x}:{:#x} -> {:#x}\n",
+                "MMU: map: {:#x}:{:#x} -> {:#x} [OP={}]\n",
                 addr,
                 len,
-                iova
+                iova,
+                one_page
             );
 
-            self.page_table
-                .map_pages(iova..(iova + len as u64), addr as PhysicalAddr, ctx.prot)?;
+            self.page_table.map_pages(
+                iova..(iova + len as u64),
+                addr as PhysicalAddr,
+                ctx.prot,
+                one_page,
+            )?;
 
             left -= len;
             iova += len as u64;
@@ -476,8 +487,12 @@ impl VmInner {
                 iova
             );
 
-            self.page_table
-                .map_pages(iova..(iova + len as u64), addr as PhysicalAddr, prot)?;
+            self.page_table.map_pages(
+                iova..(iova + len as u64),
+                addr as PhysicalAddr,
+                prot,
+                false,
+            )?;
 
             iova += len as u64;
             left -= len;
@@ -1117,6 +1132,7 @@ impl Vm {
         size: u64,
         offset: u64,
         prot: Prot,
+        single_page: bool,
     ) -> Result {
         // Mapping needs a complete context
         let mut ctx = StepContext {
@@ -1154,14 +1170,20 @@ impl Vm {
             return Err(EINVAL);
         }
 
+        let (flags, gem_range) = if single_page {
+            (gpuvm::GpuVaFlags::REPEAT, UAT_PGSZ as u32)
+        } else {
+            (gpuvm::GpuVaFlags::NONE, 0u32)
+        };
+
         mod_dev_dbg!(
             inner.dev,
             "MMU: sm_map: {:#x} [{:#x}] -> {:#x}\n",
             offset,
             size,
             addr
         );
-        inner.sm_map(&mut ctx, addr, size, offset)
+        inner.sm_map(&mut ctx, addr, size, offset, gem_range, flags)
     }
 
     /// Add a direct MMIO mapping to this Vm at a free address.
@@ -1209,10 +1231,12 @@ impl Vm {
             0,
         )?;
 
-        let ret =
-            inner
-                .page_table
-                .map_pages(iova..(iova + size as u64), phys as PhysicalAddr, prot);
+        let ret = inner.page_table.map_pages(
+            iova..(iova + size as u64),
+            phys as PhysicalAddr,
+            prot,
+            false,
+        );
         // Drop the exec_lock first, so that if map_node failed the
         // KernelMappingInner destructur does not deadlock.
         core::mem::drop(inner);

drivers/gpu/drm/asahi/pgtable.rs

@@ -399,6 +399,7 @@ impl UatPageTable {
         iova_range: Range<u64>,
         mut phys: PhysicalAddr,
         prot: Prot,
+        one_page: bool,
     ) -> Result {
         mod_pr_debug!(
             "UATPageTable::map_pages: {:#x?} {:#x?} {:?}\n",
@@ -424,7 +425,9 @@ impl UatPageTable {
                     );
                 }
                 pte.store(phys | prot.as_pte() | pte_bits, Ordering::Relaxed);
-                phys += UAT_PGSZ as PhysicalAddr;
+                if !one_page {
+                    phys += UAT_PGSZ as PhysicalAddr;
+                }
             }
         })
     }