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smasher816haata
smasher816
authored and
haata
committed
sam: Enable MPU
1 parent 634ed04 commit 01848e5

8 files changed

Lines changed: 170 additions & 43 deletions

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‎Debug/cli/cli.c‎

Lines changed: 35 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -60,6 +60,7 @@ CLIDict_Entry( reload, "Signals microcontroller to reflash/reload." );
6060
CLIDict_Entry( reset, "Resets the terminal back to initial settings." );
6161
CLIDict_Entry( restart, "Sends a software restart, should be similar to powering on the device." );
6262
CLIDict_Entry( tick, "Displays the fundamental tick size, and current ticks since last systick." );
63+
CLIDict_Entry( ram, "Shows the current and max ram usage" );
6364
CLIDict_Entry( version, "Version information about this firmware." );
6465

6566
CLIDict_Def( basicCLIDict, "General Commands" ) = {
@@ -78,6 +79,7 @@ CLIDict_Def( basicCLIDict, "General Commands" ) = {
7879
CLIDict_Item( reset ),
7980
CLIDict_Item( restart ),
8081
CLIDict_Item( tick ),
82+
CLIDict_Item( ram ),
8183
CLIDict_Item( version ),
8284
{ 0, 0, 0 } // Null entry for dictionary end
8385
};
@@ -868,3 +870,36 @@ void cliFunc_version( char* args )
868870
#endif
869871
}
870872

873+
void cliFunc_ram( char* args )
874+
{
875+
extern uint32_t _sstack, _estack;
876+
877+
uint32_t *p;
878+
for (p = &_sstack; p < &_estack; p++) {
879+
if (*p != 0xDEADBEEF) break;
880+
}
881+
882+
uint32_t stack_size = &_estack - &_sstack;
883+
uint32_t stack_current = &_estack - (uint32_t*)__get_MSP();
884+
uint32_t stack_peak = &_estack - p;
885+
886+
print( NL );
887+
print("stack: ");
888+
printHex(stack_size);
889+
print(" bytes" NL);
890+
891+
print(" current = ");
892+
printHex(stack_current);
893+
print(" (");
894+
printInt8( 100 * stack_current / stack_size );
895+
print("%)" NL);
896+
897+
print(" peak = ");
898+
printHex(stack_peak);
899+
print(" (");
900+
printInt8( 100 * stack_peak / stack_size );
901+
print("%)" NL);
902+
903+
print(NL);
904+
print("heap: N/A" NL);
905+
}

‎Debug/cli/cli.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -131,5 +131,6 @@ void cliFunc_reload ( char* args );
131131
void cliFunc_reset ( char* args );
132132
void cliFunc_restart ( char* args );
133133
void cliFunc_tick ( char* args );
134+
void cliFunc_ram ( char* args );
134135
void cliFunc_version ( char* args );
135136

‎Lib/arm_cortex.c‎

Lines changed: 41 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,29 @@
1919
* THE SOFTWARE.
2020
*/
2121

22-
#include <stdint.h>
22+
/**< Interrupt Number Definition */
23+
typedef enum IRQn
24+
{
25+
/****** Cortex-M4 Processor Exceptions Numbers ******************************/
26+
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
27+
MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */
28+
BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */
29+
UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */
30+
SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */
31+
DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */
32+
PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */
33+
SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */
34+
} IRQn_Type;
35+
36+
/**
37+
* \brief Configuration of the Cortex-M4 Processor and Core Peripherals
38+
*/
39+
40+
#define __CM4_REV 0x0001 /**< SAM4S8B core revision number ([15:8] revision number, [7:0] patch number) */
41+
#define __MPU_PRESENT 1 /**< SAM4S8B does provide a MPU */
42+
#define __FPU_PRESENT 0 /**< SAM4S8B does not provide a FPU */
43+
#define __NVIC_PRIO_BITS 4 /**< SAM4S8B uses 4 Bits for the Priority Levels */
44+
#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
2345
#include "arm_cortex.h"
2446

2547
Cortex_IRQ get_current_isr()
@@ -106,7 +128,22 @@ void read_stacked_fault_frame( uint32_t *faultStackedAddress )
106128
}
107129

108130
// Causes more BusFaults to be precise (good for debugging)
109-
void disable_write_buffering()
110-
{
111-
SCnSCB_ACTLR |= SCnSCB_ACTLR_DISDEFWBUF_Msk;
131+
void disable_write_buffering() {
132+
SCnSCB->ACTLR |= SCnSCB_ACTLR_DISDEFWBUF_Msk;
133+
}
134+
135+
void mpu_setup_region(uint8_t region, uint32_t *start, uint32_t *end, uint32_t attr) {
136+
MPU->RBAR = (( (uint32_t)start << MPU_RBAR_ADDR_Pos ) & MPU_RBAR_ADDR_Msk) |
137+
((region << MPU_RBAR_REGION_Pos) & MPU_RBAR_REGION_Msk) |
138+
((1 << MPU_RBAR_VALID_Pos) & MPU_RBAR_VALID_Msk);
139+
140+
uint8_t size_pow = 32 - __CLZ(end - start) - 1;
141+
MPU->RASR = ((size_pow << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) |
142+
((1 << MPU_RASR_ENABLE_Pos) & MPU_RASR_ENABLE_Msk) |
143+
attr;
144+
}
145+
146+
void mpu_enable() {
147+
//MPU->CTRL = MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_ENABLE_Msk;
148+
MPU->CTRL = MPU_CTRL_ENABLE_Msk;
112149
}

‎Lib/arm_cortex.h‎

Lines changed: 51 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -20,28 +20,59 @@
2020
*/
2121

2222
#pragma once
23+
#include <stdint.h>
2324

2425
// ----- Defines -----
2526

26-
/* Auxiliary Control Register Definitions */
27-
#define SCnSCB_ACTLR *(volatile uint32_t *)0xE000E008 // Auxiliary control
27+
#include <core_cm4.h>
2828

29+
#define PERIPH_START ((uint32_t*)0x40000000)
30+
#define PERIPH_END ((uint32_t*)0x40200000)
2931

30-
#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
31-
#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
32+
#define SYSTEM_START ((uint32_t*)0xE0000000)
33+
#define SYSTEM_END ((uint32_t*)0xE000F000)
3234

33-
#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
34-
#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
35+
/* MPU Aliases */
3536

36-
#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
37-
#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
37+
#define MPU_ATTR_XN (( 1 << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk)
38+
#define MPU_ATTR_AP(ap) ((ap << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)
3839

39-
#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
40-
#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
40+
#define MPU_ACCESS_NONE ((0b000 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)
41+
#define MPU_ACCESS_RW_PRIV ((0b001 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)
42+
#define MPU_ACCESS_PRIV_WRITE ((0b010 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)
43+
#define MPU_ACCESS_RW_ALL ((0b011 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)
44+
#define MPU_ACCESS_RO_PRIV ((0b101 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)
45+
#define MPU_ACCESS_RO_ALL ((0b110 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)
4146

42-
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
43-
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
47+
// Normal memory, non-shareable, write-through
48+
#define MPU_ATTR_FLASH (((0b000 << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) \
49+
| ((1 << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) \
50+
| ((0 << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) \
51+
| ((0 << MPU_RASR_S_Pos) & MPU_RASR_S_Msk))
4452

53+
// Normal memory, shareable, write-through
54+
#define MPU_ATTR_INTERNAL_SRAM (((0b000 << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) \
55+
| ((1 << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) \
56+
| ((0 << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) \
57+
| ((1 << MPU_RASR_S_Pos) & MPU_RASR_S_Msk))
58+
59+
// Normal memory, shareable, write-back, write-allocate
60+
#define MPU_ATTR_EXTERNAL_SRAM (((0b000 << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) \
61+
| ((1 << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) \
62+
| ((1 << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) \
63+
| ((1 << MPU_RASR_S_Pos) & MPU_RASR_S_Msk))
64+
65+
// Device memory, shareable
66+
#define MPU_ATTR_PERIPHERALS (((0b000 << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) \
67+
| ((0 << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) \
68+
| ((1 << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) \
69+
| ((1 << MPU_RASR_S_Pos) & MPU_RASR_S_Msk))
70+
71+
// Device memory, shareable
72+
#define MPU_ATTR_SYSTEM (((0b000 << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) \
73+
| ((0 << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) \
74+
| ((0 << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) \
75+
| ((0 << MPU_RASR_S_Pos) & MPU_RASR_S_Msk))
4576

4677
// ----- Types -----
4778

@@ -145,10 +176,18 @@ typedef struct __attribute__((packed)) {
145176
} DFSR_t;
146177

147178

179+
// ----- Variables -----
180+
181+
extern uint32_t _sidata, _sdata, _edata, _sbss, _ebss, _app_rom, _app_rom_end, _bootloader;
182+
183+
148184
// ----- Functions -----
149185

150186
extern void __attribute__((naked)) debug_isr ( void );
151187

152188
Cortex_IRQ get_current_isr();
153189
void read_stacked_fault_frame( uint32_t *faultStackedAddress );
154190
void disable_write_buffering();
191+
192+
void mpu_setup_region(uint8_t region, uint32_t *start, uint32_t *end, uint32_t attr);
193+
void mpu_enable();

‎Lib/ld/sam4s8b.ld‎

Lines changed: 11 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,10 @@ MEMORY
4646
_app_rom = ORIGIN( FLASH );
4747
_app_rom_end = ORIGIN( FLASH ) + LENGTH( FLASH );
4848

49+
/* Memmory range for the RAM */
50+
_ram_start_ = ORIGIN( RAM );
51+
_ram_end_ = ORIGIN( RAM ) + LENGTH( RAM ) -1 ;
52+
4953
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
5054
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x500;
5155

@@ -121,8 +125,12 @@ SECTIONS
121125
{
122126
. = ALIGN(4);
123127
_srelocate = .;
128+
_sramfunc = .;
124129
*(.ramfunc .ramfunc.*);
130+
_eramfunc = .;
131+
_sdata = .;
125132
*(.data .data.*);
133+
_edata = .;
126134
. = ALIGN(4);
127135
_erelocate = .;
128136
} > RAM
@@ -142,8 +150,10 @@ SECTIONS
142150
_ezero = .;
143151
} > RAM
144152

153+
. = . + 1K; /* padding for mpu protection */
154+
145155
/* stack section */
146-
.stack (NOLOAD):
156+
.stack (NOLOAD): AT( _ram_end - STACK_SIZE )
147157
{
148158
. = ALIGN(8);
149159
_sstack = .;
@@ -152,17 +162,6 @@ SECTIONS
152162
_estack = .;
153163
} > RAM
154164

155-
/* heap section */
156-
.heap (NOLOAD):
157-
{
158-
. = ALIGN(8);
159-
_sheap = .;
160-
. = . + HEAP_SIZE;
161-
. = ALIGN(8);
162-
_eheap = .;
163-
} > RAM
164-
165165
. = ALIGN(4);
166166
_end = . ;
167-
_ram_end_ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
168167
}

‎Lib/ld/sam4s8c.ld‎

Lines changed: 12 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -46,8 +46,12 @@ MEMORY
4646
_app_rom = ORIGIN( FLASH );
4747
_app_rom_end = ORIGIN( FLASH ) + LENGTH( FLASH );
4848

49+
/* Memmory range for the RAM */
50+
_ram_start_ = ORIGIN( RAM );
51+
_ram_end_ = ORIGIN( RAM ) + LENGTH( RAM ) -1 ;
52+
4953
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
50-
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x400;
54+
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x500;
5155

5256
/* The heapsize used by the application. NOTE: you need to adjust according to your application. */
5357
HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x200;
@@ -121,8 +125,12 @@ SECTIONS
121125
{
122126
. = ALIGN(4);
123127
_srelocate = .;
128+
_sramfunc = .;
124129
*(.ramfunc .ramfunc.*);
130+
_eramfunc = .;
131+
_sdata = .;
125132
*(.data .data.*);
133+
_edata = .;
126134
. = ALIGN(4);
127135
_erelocate = .;
128136
} > RAM
@@ -142,8 +150,10 @@ SECTIONS
142150
_ezero = .;
143151
} > RAM
144152

153+
. = . + 1K; /* padding for mpu protection */
154+
145155
/* stack section */
146-
.stack (NOLOAD):
156+
.stack (NOLOAD): AT( ORIGIN( RAM ) + LENGTH( RAM ) - STACK_SIZE )
147157
{
148158
. = ALIGN(8);
149159
_sstack = .;
@@ -152,18 +162,6 @@ SECTIONS
152162
_estack = .;
153163
} > RAM
154164

155-
/* heap section */
156-
.heap (NOLOAD):
157-
{
158-
. = ALIGN(8);
159-
_sheap = .;
160-
. = . + HEAP_SIZE;
161-
. = ALIGN(8);
162-
_eheap = .;
163-
} > RAM
164-
165165
. = ALIGN(4);
166166
_end = . ;
167-
_ram_end_ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
168167
}
169-

‎Lib/sam.c‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -57,6 +57,9 @@ extern uint32_t _szero;
5757
extern uint32_t _ezero;
5858
extern uint32_t _sstack;
5959
extern uint32_t _estack;
60+
extern uint32_t _ram_start_, _ram_end_;
61+
extern uint32_t _sramfunc, _eramfunc;
62+
extern uint32_t _sdata, _edata;
6063

6164
// Unique Id storage variable
6265
// Must be read from flash using ReadUniqueID()
@@ -437,6 +440,10 @@ void ResetHandler()
437440
*pDest++ = 0;
438441
}
439442

443+
/* Initialize the stack */
444+
for (pDest = &_sstack; pDest < &_estack;) {
445+
*pDest++ = 0xDEADBEEF;
446+
}
440447

441448
/* Set 6 FWS for Embedded Flash Access according to 120MHz configuration */
442449
EFC0->EEFC_FMR = EEFC_FMR_FWS(5)|EEFC_FMR_CLOE;
@@ -520,6 +527,16 @@ void ResetHandler()
520527
//REG_MTB_MASTER = 0x80000000 + 6;
521528
#endif
522529

530+
// Default to no access
531+
mpu_setup_region(0, &_sfixed, &_efixed, MPU_ATTR_FLASH | MPU_ACCESS_RO_ALL | 0);
532+
mpu_setup_region(1, STORAGE_FLASH_START, STORAGE_FLASH_END, MPU_ATTR_FLASH | MPU_ACCESS_RW_ALL | MPU_ATTR_XN);
533+
mpu_setup_region(2, &_sramfunc, &_eramfunc, MPU_ATTR_INTERNAL_SRAM | MPU_ACCESS_RO_ALL | 0);
534+
mpu_setup_region(3, _sdata, &_ezero, MPU_ATTR_INTERNAL_SRAM | MPU_ACCESS_RW_ALL | MPU_ATTR_XN);
535+
mpu_setup_region(4, _sstack, &_estack, MPU_ATTR_INTERNAL_SRAM | MPU_ACCESS_RW_ALL | MPU_ATTR_XN);
536+
mpu_setup_region(5, PERIPH_START, PERIPH_END, MPU_ATTR_PERIPHERALS | MPU_ACCESS_PRIV_WRITE | MPU_ATTR_XN);
537+
mpu_setup_region(6, SYSTEM_END, SYSTEM_END, MPU_ACCESS_PRIV_WRITE); // Always XN
538+
mpu_enable();
539+
523540
// Initialize the SysTick counter
524541
SysTick->LOAD = (F_CPU / 1000) - 1;
525542
SysTick->VAL = 0;

‎Lib/sam.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,8 @@
5959
#define STORAGE_FLASH_PAGE_SIZE IFLASH0_PAGE_SIZE
6060
#define STORAGE_RESERVED_FLASH (STORAGE_PAGES * STORAGE_FLASH_PAGE_SIZE)
6161
#define STORAGE_FLASH_SIZE IFLASH0_SIZE
62-
#define STORAGE_FLASH_START (IFLASH0_ADDR + STORAGE_FLASH_SIZE - STORAGE_RESERVED_FLASH)
62+
#define STORAGE_FLASH_END (IFLASH0_ADDR + STORAGE_FLASH_SIZE)
63+
#define STORAGE_FLASH_START (STORAGE_FLASH_END - STORAGE_RESERVED_FLASH)
6364

6465

6566

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