Merge tag 'jdk-26.0.1+8' into sapmachine26

Added tag jdk-26.0.1+8 for changeset fcc00fc

Author: RealCLanger

.jcheck/conf

@@ -1,7 +1,7 @@
 [general]
-project=jdk
+project=jdk-updates
 jbs=JDK
-version=26
+version=26.0.1
 
 [checks]
 error=author,committer,reviewers,merge,issues,executable,symlink,message,hg-tag,whitespace,problemlists,copyright

make/modules/java.base/Copy.gmk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2014, 2025, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2014, 2026, Oracle and/or its affiliates. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
@@ -172,6 +172,10 @@ ifeq ($(USE_EXTERNAL_LIBZ), true)
   LEGAL_EXCLUDES += zlib.md
 endif
 
+ifneq ($(TOOLCHAIN_TYPE), gcc)
+  LEGAL_EXCLUDES += gcc.md
+endif
+
 $(eval $(call SetupCopyLegalFiles, COPY_LEGAL, \
     EXCLUDES := $(LEGAL_EXCLUDES), \
 ))

src/hotspot/cpu/aarch64/aarch64.ad

@@ -7702,10 +7702,11 @@ instruct bytes_reverse_unsigned_short(iRegINoSp dst, iRegIorL2I src) %{
   match(Set dst (ReverseBytesUS src));
 
   ins_cost(INSN_COST);
-  format %{ "rev16w  $dst, $src" %}
+  format %{ "rev16w $dst, $src\t# $dst -> unsigned short" %}
 
   ins_encode %{
     __ rev16w(as_Register($dst$$reg), as_Register($src$$reg));
+    __ narrow_subword_type(as_Register($dst$$reg), T_CHAR);
   %}
 
   ins_pipe(ialu_reg);

src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp

@@ -2665,6 +2665,17 @@ void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in
   }
 }
 
+void MacroAssembler::narrow_subword_type(Register reg, BasicType bt) {
+  assert(is_subword_type(bt), "required");
+  switch (bt) {
+  case T_BOOLEAN: andw(reg, reg, 1); break;
+  case T_BYTE:    sxtbw(reg, reg); break;
+  case T_CHAR:    uxthw(reg, reg); break;
+  case T_SHORT:   sxthw(reg, reg); break;
+  default:        ShouldNotReachHere();
+  }
+}
+
 void MacroAssembler::decrementw(Register reg, int value)
 {
   if (value < 0)  { incrementw(reg, -value);      return; }

src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp

@@ -33,6 +33,7 @@
 #include "oops/compressedOops.hpp"
 #include "oops/compressedKlass.hpp"
 #include "runtime/vm_version.hpp"
+#include "utilities/globalDefinitions.hpp"
 #include "utilities/powerOfTwo.hpp"
 
 class OopMap;
@@ -721,6 +722,9 @@ class MacroAssembler: public Assembler {
   // Support for sign-extension (hi:lo = extend_sign(lo))
   void extend_sign(Register hi, Register lo);
 
+  // Clean up a subword typed value to the representation in compliance with JVMS §2.3
+  void narrow_subword_type(Register reg, BasicType bt);
+
   // Load and store values by size and signed-ness
   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
   void store_sized_value(Address dst, Register src, size_t size_in_bytes);

src/hotspot/cpu/arm/arm.ad

@@ -9199,10 +9199,12 @@ instruct bytes_reverse_long(iRegL dst, iRegL src) %{
 
 instruct bytes_reverse_unsigned_short(iRegI dst, iRegI src) %{
   match(Set dst (ReverseBytesUS src));
-  size(4);
-  format %{ "REV16 $dst,$src" %}
+  size(8);
+  format %{ "REV32 $dst,$src\n\t"
+            "LSR   $dst,$dst,#16" %}
   ins_encode %{
-    __ rev16($dst$$Register, $src$$Register);
+    __ rev($dst$$Register, $src$$Register);
+    __ mov($dst$$Register, AsmOperand($dst$$Register, lsr, 16));
   %}
   ins_pipe( iload_mem ); // FIXME
 %}

src/hotspot/cpu/ppc/interp_masm_ppc_64.cpp

@@ -1109,11 +1109,11 @@ void InterpreterMacroAssembler::verify_method_data_pointer() {
   lhz(R11_scratch1, in_bytes(DataLayout::bci_offset()), R28_mdx);
   ld(R12_scratch2, in_bytes(Method::const_offset()), R19_method);
   addi(R11_scratch1, R11_scratch1, in_bytes(ConstMethod::codes_offset()));
-  add(R11_scratch1, R12_scratch2, R12_scratch2);
+  add(R11_scratch1, R11_scratch1, R12_scratch2);
   cmpd(CR0, R11_scratch1, R14_bcp);
   beq(CR0, verify_continue);
 
-  call_VM_leaf(CAST_FROM_FN_PTR(address, InterpreterRuntime::verify_mdp ), R19_method, R14_bcp, R28_mdx);
+  call_VM_leaf(CAST_FROM_FN_PTR(address, InterpreterRuntime::verify_mdp), R19_method, R14_bcp, R28_mdx);
 
   bind(verify_continue);
 #endif

src/hotspot/cpu/ppc/ppc.ad

@@ -12391,6 +12391,19 @@ instruct countTrailingZerosL_cnttzd(iRegIdst dst, iRegLsrc src) %{
   ins_pipe(pipe_class_default);
 %}
 
+// Expand nodes for byte_reverse_int/ushort/short.
+instruct rlwinm(iRegIdst dst, iRegIsrc src, immI16 shift, immI16 mb, immI16 me) %{
+  effect(DEF dst, USE src, USE shift, USE mb, USE me);
+  predicate(false);
+
+  format %{ "RLWINM  $dst, $src, $shift, $mb, $me" %}
+  size(4);
+  ins_encode %{
+    __ rlwinm($dst$$Register, $src$$Register, $shift$$constant, $mb$$constant, $me$$constant);
+  %}
+  ins_pipe(pipe_class_default);
+%}
+
 // Expand nodes for byte_reverse_int.
 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 n, immI16 b) %{
   effect(DEF dst, USE src, USE n, USE b);
@@ -12547,34 +12560,22 @@ instruct bytes_reverse_long(iRegLdst dst, iRegLsrc src) %{
   ins_pipe(pipe_class_default);
 %}
 
+// Need zero extend. Must not use brh only.
 instruct bytes_reverse_ushort_Ex(iRegIdst dst, iRegIsrc src) %{
   match(Set dst (ReverseBytesUS src));
-  predicate(!UseByteReverseInstructions);
   ins_cost(2*DEFAULT_COST);
 
   expand %{
+    immI16  imm31 %{ (int) 31 %}
+    immI16  imm24 %{ (int) 24 %}
     immI16  imm16 %{ (int) 16 %}
     immI16   imm8 %{ (int)  8 %}
 
-    urShiftI_reg_imm(dst, src, imm8);
+    rlwinm(dst, src, imm24, imm24, imm31);
     insrwi(dst, src, imm8, imm16);
   %}
 %}
 
-instruct bytes_reverse_ushort(iRegIdst dst, iRegIsrc src) %{
-  match(Set dst (ReverseBytesUS src));
-  predicate(UseByteReverseInstructions);
-  ins_cost(DEFAULT_COST);
-  size(4);
-
-  format %{ "BRH  $dst, $src" %}
-
-  ins_encode %{
-    __ brh($dst$$Register, $src$$Register);
-  %}
-  ins_pipe(pipe_class_default);
-%}
-
 instruct bytes_reverse_short_Ex(iRegIdst dst, iRegIsrc src) %{
   match(Set dst (ReverseBytesS src));
   predicate(!UseByteReverseInstructions);

src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp

@@ -213,7 +213,7 @@ void RegisterSaver::restore_live_registers(MacroAssembler* masm) {
 // Is vector's size (in bytes) bigger than a size saved by default?
 // riscv does not ovlerlay the floating-point registers on vector registers like aarch64.
 bool SharedRuntime::is_wide_vector(int size) {
-  return UseRVV;
+  return UseRVV && size > 0;
 }
 
 // ---------------------------------------------------------------------------

src/hotspot/cpu/riscv/vm_version_riscv.cpp

@@ -167,11 +167,6 @@ void VM_Version::common_initialize() {
       (unaligned_scalar.value() == MISALIGNED_SCALAR_FAST));
   }
 
-  if (FLAG_IS_DEFAULT(AlignVector)) {
-    FLAG_SET_DEFAULT(AlignVector,
-      unaligned_vector.value() != MISALIGNED_VECTOR_FAST);
-  }
-
 #ifdef __riscv_ztso
   // Hotspot is compiled with TSO support, it will only run on hardware which
   // supports Ztso
@@ -242,6 +237,11 @@ void VM_Version::c2_initialize() {
     }
   }
 
+  if (FLAG_IS_DEFAULT(AlignVector)) {
+    FLAG_SET_DEFAULT(AlignVector,
+      unaligned_vector.value() != MISALIGNED_VECTOR_FAST);
+  }
+
   // NOTE: Make sure codes dependent on UseRVV are put after MaxVectorSize initialize,
   //       as there are extra checks inside it which could disable UseRVV
   //       in some situations.