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vmaksimovmaksimo
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[Backport to 15] [LLVM->SPV-IR] Add const to GroupAsyncCopy/GenericPtrMemSemantics/vload* source pointer (#3480)
Movtivation is similar to 96f5ade: * Align with OpenCL builtin. * Align with their declarations in https://github.com/intel/llvm/blob/sycl/clang/lib/Sema/SPIRVBuiltins.td. * Targets consuming SPV-IR don't need to implement both const and non-const builtin variants; that duplication only bloats the builtin library without any benefit.
1 parent eaa272b commit b92f026

7 files changed

Lines changed: 204 additions & 199 deletions

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‎lib/SPIRV/SPIRVUtil.cpp‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2484,6 +2484,7 @@ class SPIRVFriendlyIRMangleInfo : public BuiltinFuncMangleInfo {
24842484
addUnsignedArg(3);
24852485
break;
24862486
case OpGroupAsyncCopy:
2487+
setArgAttr(2, SPIR::ATTR_CONST);
24872488
addUnsignedArg(3);
24882489
addUnsignedArg(4);
24892490
break;
@@ -2627,6 +2628,9 @@ class SPIRVFriendlyIRMangleInfo : public BuiltinFuncMangleInfo {
26272628
case internal::OpConvertHandleToSampledImageINTEL:
26282629
addUnsignedArg(0);
26292630
break;
2631+
case OpGenericPtrMemSemantics:
2632+
setArgAttr(0, SPIR::ATTR_CONST);
2633+
break;
26302634
default:;
26312635
// No special handling is needed
26322636
}
@@ -2699,6 +2703,7 @@ class OpenCLStdToSPIRVFriendlyIRMangleInfo : public BuiltinFuncMangleInfo {
26992703
case OpenCLLIB::Vload_halfn:
27002704
case OpenCLLIB::Vloada_halfn:
27012705
addUnsignedArg(0);
2706+
setArgAttr(1, SPIR::ATTR_CONST);
27022707
break;
27032708
case OpenCLLIB::Vstoren:
27042709
case OpenCLLIB::Vstore_half:

‎test/OpenCL.std/vload_half.spvasm‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -6,22 +6,22 @@
66
;
77
; CHECK-LABEL: spir_kernel void @test
88
;
9-
; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS1Dh(
10-
; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS1Dh(
11-
; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS1Dh(
12-
; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS1Dh(
13-
; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS3Dh(
14-
; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS3Dh(
15-
; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS3Dh(
16-
; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS3Dh(
17-
; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS2Dh(
18-
; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS2Dh(
19-
; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS2Dh(
20-
; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS2Dh(
21-
; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPDh(
22-
; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPDh(
23-
; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPDh(
24-
; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPDh(
9+
; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS1KDh(
10+
; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS1KDh(
11+
; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS1KDh(
12+
; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS1KDh(
13+
; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS3KDh(
14+
; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS3KDh(
15+
; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS3KDh(
16+
; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS3KDh(
17+
; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS2KDh(
18+
; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS2KDh(
19+
; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS2KDh(
20+
; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPU3AS2KDh(
21+
; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPKDh(
22+
; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPKDh(
23+
; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPKDh(
24+
; CHECK-SPV-IR: call spir_func float @_Z29__spirv_ocl_vload_half_RfloatjPKDh(
2525
;
2626
; CHECK-CL20: call spir_func float @_Z10vload_halfjPU3AS1KDh
2727
; CHECK-CL20: call spir_func float @_Z10vload_halfjPU3AS1KDh

‎test/OpenCL.std/vload_halfn.spvasm‎

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -6,26 +6,26 @@
66
;
77
; CHECK-LABEL: spir_kernel void @test
88
;
9-
; CHECK-SPV-IR: call spir_func <2 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat2jPU3AS1Dhi(
10-
; CHECK-SPV-IR: call spir_func <3 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat3jPU3AS1Dhi(
11-
; CHECK-SPV-IR: call spir_func <4 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat4jPU3AS1Dhi(
12-
; CHECK-SPV-IR: call spir_func <8 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat8jPU3AS1Dhi(
13-
; CHECK-SPV-IR: call spir_func <16 x float> @_Z32__spirv_ocl_vload_halfn_Rfloat16jPU3AS1Dhi(
14-
; CHECK-SPV-IR: call spir_func <2 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat2jPU3AS3Dhi(
15-
; CHECK-SPV-IR: call spir_func <3 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat3jPU3AS3Dhi(
16-
; CHECK-SPV-IR: call spir_func <4 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat4jPU3AS3Dhi(
17-
; CHECK-SPV-IR: call spir_func <8 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat8jPU3AS3Dhi(
18-
; CHECK-SPV-IR: call spir_func <16 x float> @_Z32__spirv_ocl_vload_halfn_Rfloat16jPU3AS3Dhi(
19-
; CHECK-SPV-IR: call spir_func <2 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat2jPU3AS2Dhi(
20-
; CHECK-SPV-IR: call spir_func <3 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat3jPU3AS2Dhi(
21-
; CHECK-SPV-IR: call spir_func <4 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat4jPU3AS2Dhi(
22-
; CHECK-SPV-IR: call spir_func <8 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat8jPU3AS2Dhi(
23-
; CHECK-SPV-IR: call spir_func <16 x float> @_Z32__spirv_ocl_vload_halfn_Rfloat16jPU3AS2Dhi(
24-
; CHECK-SPV-IR: call spir_func <2 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat2jPDhi(
25-
; CHECK-SPV-IR: call spir_func <3 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat3jPDhi(
26-
; CHECK-SPV-IR: call spir_func <4 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat4jPDhi(
27-
; CHECK-SPV-IR: call spir_func <8 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat8jPDhi(
28-
; CHECK-SPV-IR: call spir_func <16 x float> @_Z32__spirv_ocl_vload_halfn_Rfloat16jPDhi(
9+
; CHECK-SPV-IR: call spir_func <2 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat2jPU3AS1KDhi(
10+
; CHECK-SPV-IR: call spir_func <3 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat3jPU3AS1KDhi(
11+
; CHECK-SPV-IR: call spir_func <4 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat4jPU3AS1KDhi(
12+
; CHECK-SPV-IR: call spir_func <8 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat8jPU3AS1KDhi(
13+
; CHECK-SPV-IR: call spir_func <16 x float> @_Z32__spirv_ocl_vload_halfn_Rfloat16jPU3AS1KDhi(
14+
; CHECK-SPV-IR: call spir_func <2 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat2jPU3AS3KDhi(
15+
; CHECK-SPV-IR: call spir_func <3 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat3jPU3AS3KDhi(
16+
; CHECK-SPV-IR: call spir_func <4 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat4jPU3AS3KDhi(
17+
; CHECK-SPV-IR: call spir_func <8 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat8jPU3AS3KDhi(
18+
; CHECK-SPV-IR: call spir_func <16 x float> @_Z32__spirv_ocl_vload_halfn_Rfloat16jPU3AS3KDhi(
19+
; CHECK-SPV-IR: call spir_func <2 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat2jPU3AS2KDhi(
20+
; CHECK-SPV-IR: call spir_func <3 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat3jPU3AS2KDhi(
21+
; CHECK-SPV-IR: call spir_func <4 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat4jPU3AS2KDhi(
22+
; CHECK-SPV-IR: call spir_func <8 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat8jPU3AS2KDhi(
23+
; CHECK-SPV-IR: call spir_func <16 x float> @_Z32__spirv_ocl_vload_halfn_Rfloat16jPU3AS2KDhi(
24+
; CHECK-SPV-IR: call spir_func <2 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat2jPKDhi(
25+
; CHECK-SPV-IR: call spir_func <3 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat3jPKDhi(
26+
; CHECK-SPV-IR: call spir_func <4 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat4jPKDhi(
27+
; CHECK-SPV-IR: call spir_func <8 x float> @_Z31__spirv_ocl_vload_halfn_Rfloat8jPKDhi(
28+
; CHECK-SPV-IR: call spir_func <16 x float> @_Z32__spirv_ocl_vload_halfn_Rfloat16jPKDhi(
2929
;
3030
; CHECK-CL20: call spir_func <2 x float> @_Z11vload_half2jPU3AS1KDh
3131
; CHECK-CL20: call spir_func <3 x float> @_Z11vload_half3jPU3AS1KDh

‎test/OpenCL.std/vloada_halfn.spvasm‎

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -6,26 +6,26 @@
66
;
77
; CHECK-LABEL: spir_kernel void @test
88
;
9-
; CHECK-SPV-IR: call spir_func <2 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat2jPU3AS1Dhi(
10-
; CHECK-SPV-IR: call spir_func <3 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat3jPU3AS1Dhi(
11-
; CHECK-SPV-IR: call spir_func <4 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat4jPU3AS1Dhi(
12-
; CHECK-SPV-IR: call spir_func <8 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat8jPU3AS1Dhi(
13-
; CHECK-SPV-IR: call spir_func <16 x float> @_Z33__spirv_ocl_vloada_halfn_Rfloat16jPU3AS1Dhi(
14-
; CHECK-SPV-IR: call spir_func <2 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat2jPU3AS3Dhi(
15-
; CHECK-SPV-IR: call spir_func <3 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat3jPU3AS3Dhi(
16-
; CHECK-SPV-IR: call spir_func <4 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat4jPU3AS3Dhi(
17-
; CHECK-SPV-IR: call spir_func <8 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat8jPU3AS3Dhi(
18-
; CHECK-SPV-IR: call spir_func <16 x float> @_Z33__spirv_ocl_vloada_halfn_Rfloat16jPU3AS3Dhi(
19-
; CHECK-SPV-IR: call spir_func <2 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat2jPU3AS2Dhi(
20-
; CHECK-SPV-IR: call spir_func <3 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat3jPU3AS2Dhi(
21-
; CHECK-SPV-IR: call spir_func <4 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat4jPU3AS2Dhi(
22-
; CHECK-SPV-IR: call spir_func <8 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat8jPU3AS2Dhi(
23-
; CHECK-SPV-IR: call spir_func <16 x float> @_Z33__spirv_ocl_vloada_halfn_Rfloat16jPU3AS2Dhi(
24-
; CHECK-SPV-IR: call spir_func <2 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat2jPDhi(
25-
; CHECK-SPV-IR: call spir_func <3 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat3jPDhi(
26-
; CHECK-SPV-IR: call spir_func <4 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat4jPDhi(
27-
; CHECK-SPV-IR: call spir_func <8 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat8jPDhi(
28-
; CHECK-SPV-IR: call spir_func <16 x float> @_Z33__spirv_ocl_vloada_halfn_Rfloat16jPDhi(
9+
; CHECK-SPV-IR: call spir_func <2 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat2jPU3AS1KDhi(
10+
; CHECK-SPV-IR: call spir_func <3 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat3jPU3AS1KDhi(
11+
; CHECK-SPV-IR: call spir_func <4 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat4jPU3AS1KDhi(
12+
; CHECK-SPV-IR: call spir_func <8 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat8jPU3AS1KDhi(
13+
; CHECK-SPV-IR: call spir_func <16 x float> @_Z33__spirv_ocl_vloada_halfn_Rfloat16jPU3AS1KDhi(
14+
; CHECK-SPV-IR: call spir_func <2 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat2jPU3AS3KDhi(
15+
; CHECK-SPV-IR: call spir_func <3 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat3jPU3AS3KDhi(
16+
; CHECK-SPV-IR: call spir_func <4 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat4jPU3AS3KDhi(
17+
; CHECK-SPV-IR: call spir_func <8 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat8jPU3AS3KDhi(
18+
; CHECK-SPV-IR: call spir_func <16 x float> @_Z33__spirv_ocl_vloada_halfn_Rfloat16jPU3AS3KDhi(
19+
; CHECK-SPV-IR: call spir_func <2 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat2jPU3AS2KDhi(
20+
; CHECK-SPV-IR: call spir_func <3 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat3jPU3AS2KDhi(
21+
; CHECK-SPV-IR: call spir_func <4 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat4jPU3AS2KDhi(
22+
; CHECK-SPV-IR: call spir_func <8 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat8jPU3AS2KDhi(
23+
; CHECK-SPV-IR: call spir_func <16 x float> @_Z33__spirv_ocl_vloada_halfn_Rfloat16jPU3AS2KDhi(
24+
; CHECK-SPV-IR: call spir_func <2 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat2jPKDhi(
25+
; CHECK-SPV-IR: call spir_func <3 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat3jPKDhi(
26+
; CHECK-SPV-IR: call spir_func <4 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat4jPKDhi(
27+
; CHECK-SPV-IR: call spir_func <8 x float> @_Z32__spirv_ocl_vloada_halfn_Rfloat8jPKDhi(
28+
; CHECK-SPV-IR: call spir_func <16 x float> @_Z33__spirv_ocl_vloada_halfn_Rfloat16jPKDhi(
2929
;
3030
; CHECK-CL20: call spir_func <2 x float> @_Z12vloada_half2jPU3AS1KDh
3131
; CHECK-CL20: call spir_func <3 x float> @_Z12vloada_half3jPU3AS1KDh

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