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arm64: dts: apple: Add cpufreq and OPP to M3 (t8122)
In the Apple M3 (t8122) device tree: - Add the following properties to each CPU node - operating-points-v2 - capacity-dmips-mhz - performance-domains - Add operating point tables for p-cores and e-cores - Add cpufreq hardware controller nodes (for both p-cluster and e-cluster) Signed-off-by: Michael Reeves <[email protected]>
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‎arch/arm64/boot/dts/apple/t8122.dtsi‎

Lines changed: 195 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -62,6 +62,9 @@
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reg = <0x0 0x0>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
65+
operating-points-v2 = <&ecluster_opp>;
66+
capacity-dmips-mhz = <756>;
67+
performance-domains = <&cpufreq_e>;
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next-level-cache = <&l2_cache_0>;
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i-cache-size = <0x20000>;
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d-cache-size = <0x10000>;
@@ -73,6 +76,9 @@
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reg = <0x0 0x1>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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operating-points-v2 = <&ecluster_opp>;
80+
capacity-dmips-mhz = <756>;
81+
performance-domains = <&cpufreq_e>;
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next-level-cache = <&l2_cache_0>;
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i-cache-size = <0x20000>;
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d-cache-size = <0x10000>;
@@ -84,6 +90,9 @@
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reg = <0x0 0x2>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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operating-points-v2 = <&ecluster_opp>;
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capacity-dmips-mhz = <756>;
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performance-domains = <&cpufreq_e>;
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next-level-cache = <&l2_cache_0>;
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i-cache-size = <0x20000>;
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d-cache-size = <0x10000>;
@@ -95,6 +104,9 @@
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reg = <0x0 0x3>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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operating-points-v2 = <&ecluster_opp>;
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capacity-dmips-mhz = <756>;
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performance-domains = <&cpufreq_e>;
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next-level-cache = <&l2_cache_0>;
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i-cache-size = <0x20000>;
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d-cache-size = <0x10000>;
@@ -106,6 +118,9 @@
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reg = <0x0 0x10100>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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operating-points-v2 = <&pcluster_opp>;
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capacity-dmips-mhz = <1024>;
123+
performance-domains = <&cpufreq_p>;
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next-level-cache = <&l2_cache_1>;
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i-cache-size = <0x30000>;
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d-cache-size = <0x20000>;
@@ -117,6 +132,9 @@
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reg = <0x0 0x10101>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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operating-points-v2 = <&pcluster_opp>;
136+
capacity-dmips-mhz = <1024>;
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performance-domains = <&cpufreq_p>;
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next-level-cache = <&l2_cache_1>;
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i-cache-size = <0x30000>;
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d-cache-size = <0x20000>;
@@ -128,6 +146,9 @@
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reg = <0x0 0x10102>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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operating-points-v2 = <&pcluster_opp>;
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capacity-dmips-mhz = <1024>;
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performance-domains = <&cpufreq_p>;
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next-level-cache = <&l2_cache_1>;
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i-cache-size = <0x30000>;
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d-cache-size = <0x20000>;
@@ -139,6 +160,9 @@
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reg = <0x0 0x10103>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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operating-points-v2 = <&pcluster_opp>;
164+
capacity-dmips-mhz = <1024>;
165+
performance-domains = <&cpufreq_p>;
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next-level-cache = <&l2_cache_1>;
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i-cache-size = <0x30000>;
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d-cache-size = <0x20000>;
@@ -159,6 +183,165 @@
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};
160184
};
161185

186+
ecluster_opp: opp-table-0 {
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compatible = "operating-points-v2";
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opp-shared;
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190+
opp01 {
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opp-hz = /bits/ 64 <600000000>;
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opp-level = <1>;
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clock-latency-ns = <7500>;
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opp-microwatt = <26000>;
195+
};
196+
opp02 {
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opp-hz = /bits/ 64 <912000000>;
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opp-level = <2>;
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clock-latency-ns = <20000>;
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opp-microwatt = <56000>;
201+
};
202+
opp03 {
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opp-hz = /bits/ 64 <1284000000>;
204+
opp-level = <3>;
205+
clock-latency-ns = <22000>;
206+
opp-microwatt = <88000>;
207+
};
208+
opp04 {
209+
opp-hz = /bits/ 64 <1752000000>;
210+
opp-level = <4>;
211+
clock-latency-ns = <30000>;
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opp-microwatt = <155000>;
213+
};
214+
opp05 {
215+
opp-hz = /bits/ 64 <2004000000>;
216+
opp-level = <5>;
217+
clock-latency-ns = <35000>;
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opp-microwatt = <231000>;
219+
};
220+
opp06 {
221+
opp-hz = /bits/ 64 <2256000000>;
222+
opp-level = <6>;
223+
clock-latency-ns = <39000>;
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opp-microwatt = <254000>;
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};
226+
opp07 {
227+
opp-hz = /bits/ 64 <2424000000>;
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opp-level = <7>;
229+
clock-latency-ns = <53000>;
230+
opp-microwatt = <351000>;
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};
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};
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pcluster_opp: opp-table-1 {
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compatible = "operating-points-v2";
236+
opp-shared;
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opp01 {
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opp-hz = /bits/ 64 <660000000>;
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opp-level = <1>;
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clock-latency-ns = <9000>;
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opp-microwatt = <133000>;
243+
};
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opp02 {
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opp-hz = /bits/ 64 <924000000>;
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opp-level = <2>;
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clock-latency-ns = <19000>;
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opp-microwatt = <212000>;
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};
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opp03 {
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opp-hz = /bits/ 64 <1188000000>;
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opp-level = <3>;
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clock-latency-ns = <22000>;
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opp-microwatt = <261000>;
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};
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opp04 {
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opp-hz = /bits/ 64 <1452000000>;
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opp-level = <4>;
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clock-latency-ns = <24000>;
260+
opp-microwatt = <345000>;
261+
};
262+
opp05 {
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opp-hz = /bits/ 64 <1704000000>;
264+
opp-level = <5>;
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clock-latency-ns = <26000>;
266+
opp-microwatt = <441000>;
267+
};
268+
opp06 {
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opp-hz = /bits/ 64 <1968000000>;
270+
opp-level = <6>;
271+
clock-latency-ns = <28000>;
272+
opp-microwatt = <619000>;
273+
};
274+
opp07 {
275+
opp-hz = /bits/ 64 <2208000000>;
276+
opp-level = <7>;
277+
clock-latency-ns = <30000>;
278+
opp-microwatt = <740000>;
279+
};
280+
opp08 {
281+
opp-hz = /bits/ 64 <2400000000>;
282+
opp-level = <8>;
283+
clock-latency-ns = <33000>;
284+
opp-microwatt = <855000>;
285+
};
286+
opp09 {
287+
opp-hz = /bits/ 64 <2568000000>;
288+
opp-level = <9>;
289+
clock-latency-ns = <34000>;
290+
opp-microwatt = <1006000>;
291+
};
292+
opp10 {
293+
opp-hz = /bits/ 64 <2724000000>;
294+
opp-level = <10>;
295+
clock-latency-ns = <36000>;
296+
opp-microwatt = <1217000>;
297+
};
298+
opp11 {
299+
opp-hz = /bits/ 64 <2868000000>;
300+
opp-level = <11>;
301+
clock-latency-ns = <41000>;
302+
opp-microwatt = <1534000>;
303+
};
304+
opp12 {
305+
opp-hz = /bits/ 64 <2988000000>;
306+
opp-level = <12>;
307+
clock-latency-ns = <42000>;
308+
opp-microwatt = <1714000>;
309+
};
310+
opp13 {
311+
opp-hz = /bits/ 64 <3096000000>;
312+
opp-level = <13>;
313+
clock-latency-ns = <44000>;
314+
opp-microwatt = <1877000>;
315+
};
316+
opp14 {
317+
opp-hz = /bits/ 64 <3204000000>;
318+
opp-level = <14>;
319+
clock-latency-ns = <46000>;
320+
opp-microwatt = <2159000>;
321+
};
322+
opp15 {
323+
opp-hz = /bits/ 64 <3324000000>;
324+
opp-level = <15>;
325+
clock-latency-ns = <62000>;
326+
opp-microwatt = <2393000>;
327+
turbo-mode;
328+
};
329+
opp16 {
330+
opp-hz = /bits/ 64 <3408000000>;
331+
opp-level = <16>;
332+
clock-latency-ns = <62000>;
333+
opp-microwatt = <2497000>;
334+
turbo-mode;
335+
};
336+
opp17 {
337+
opp-hz = /bits/ 64 <3504000000>;
338+
opp-level = <17>;
339+
clock-latency-ns = <62000>;
340+
opp-microwatt = <2648000>;
341+
turbo-mode;
342+
};
343+
};
344+
162345
timer {
163346
compatible = "arm,armv8-timer";
164347
interrupt-parent = <&aic>;
@@ -193,6 +376,18 @@
193376
/* Required to get >32-bit DMA via DARTs */
194377
dma-ranges = <0 0 0 0 0xffffffff 0xffffc000>;
195378

379+
cpufreq_e: cpufreq@210e20000 {
380+
compatible = "apple,t8122-cluster-cpufreq", "apple,t8112-cluster-cpufreq", "apple,cluster-cpufreq";
381+
reg = <0x2 0x10e20000 0 0x1000>;
382+
#performance-domain-cells = <0>;
383+
};
384+
385+
cpufreq_p: cpufreq@211e20000 {
386+
compatible = "apple,t8122-cluster-cpufreq", "apple,t8112-cluster-cpufreq", "apple,cluster-cpufreq";
387+
reg = <0x2 0x11e20000 0 0x1000>;
388+
#performance-domain-cells = <0>;
389+
};
390+
196391
i2c0: i2c@235010000 {
197392
compatible = "apple,t8122-i2c", "apple,t8103-i2c";
198393
reg = <0x2 0x35010000 0x0 0x4000>;

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