Skip to content

Commit 5f1fd85

Browse files
AnastaZIukAnastaZIuk
committed
pulled original remote and resolved conflicts
2 parents fdca6b2 + 5e3ad38 commit 5f1fd85

15 files changed

Lines changed: 333 additions & 12 deletions

‎include/spirv/spir-v.xml‎

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -92,7 +92,9 @@
9292
<id value="39" vendor="SirLynix" tool="Nazara ShaderLang Compiler" comment="Contact Jérôme Leclercq, https://github.com/NazaraEngine/ShaderLang"/>
9393
<id value="40" vendor="NVIDIA" tool="Slang Compiler" comment="Contact Theresa Foley, [email protected], https://github.com/shader-slang/slang/"/>
9494
<id value="41" vendor="Zig Software Foundation" tool="Zig Compiler" comment="Contact Robin Voetter, https://github.com/Snektron"/>
95-
<unused start="42" end="0xFFFF" comment="Tool ID range reservable for future use by vendors"/>
95+
<id value="42" vendor="Rendong Liang" tool="spq" comment="Contact Rendong Liang, [email protected], https://github.com/PENGUINLIONG/spq-rs"/>
96+
<id value="43" vendor="LLVM" tool="LLVM SPIR-V Backend" comment="Contact Michal Paszkowski, [email protected], https://github.com/llvm/llvm-project/tree/main/llvm/lib/Target/SPIRV"/>
97+
<unused start="44" end="0xFFFF" comment="Tool ID range reservable for future use by vendors"/>
9698
</ids>
9799

98100
<!-- SECTION: SPIR-V Opcodes and Enumerants -->
@@ -208,8 +210,8 @@
208210

209211
<!-- Reserved loop control bits -->
210212
<ids type="LoopControl" start="0" end="15" vendor="Khronos" comment="Reserved LoopControl bits, not available to vendors - see the SPIR-V Specification"/>
211-
<ids type="LoopControl" start="16" end="25" vendor="Intel" comment="Contact [email protected]"/>
212-
<ids type="LoopControl" start="26" end="30" comment="Unreserved bits reservable for use by vendors"/>
213+
<ids type="LoopControl" start="16" end="27" vendor="Intel" comment="Contact [email protected]"/>
214+
<ids type="LoopControl" start="28" end="30" comment="Unreserved bits reservable for use by vendors"/>
213215
<ids type="LoopControl" start="31" end="31" vendor="Khronos" comment="Reserved LoopControl bit, not available to vendors"/>
214216

215217

@@ -269,8 +271,8 @@
269271

270272
<!-- Reserved memory operand bits -->
271273
<ids type="MemoryOperand" start="0" end="15" vendor="Khronos" comment="Reserved MemoryOperand bits, not available to vendors - see the SPIR-V Specification"/>
272-
<ids type="MemoryOperand" start="16" end="17" vendor="Intel" comment="Contact [email protected]"/>
273-
<ids type="MemoryOperand" start="18" end="30" comment="Unreserved bits reservable for use by vendors"/>
274+
<ids type="MemoryOperand" start="16" end="18" vendor="Intel" comment="Contact [email protected]"/>
275+
<ids type="MemoryOperand" start="19" end="30" comment="Unreserved bits reservable for use by vendors"/>
274276
<ids type="MemoryOperand" start="31" end="31" vendor="Khronos" comment="Reserved MemoryOperand bit, not available to vendors"/>
275277

276278
<!-- SECTION: SPIR-V Image Operand Bit Reservations -->

‎include/spirv/unified1/NonSemanticVkspReflection.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@ extern "C" {
3333
#endif
3434

3535
enum {
36-
NonSemanticVkspReflectionRevision = 1,
36+
NonSemanticVkspReflectionRevision = 2,
3737
NonSemanticVkspReflectionRevision_BitWidthPadding = 0x7fffffff
3838
};
3939

‎include/spirv/unified1/extinst.nonsemantic.vkspreflection.grammar.json‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
{
2-
"revision" : 1,
2+
"revision" : 2,
33
"instructions" : [
44
{
55
"opname" : "Configuration",
@@ -12,7 +12,8 @@
1212
{"kind" : "LiteralString", "name" : "EntryPoint" },
1313
{"kind" : "LiteralInteger", "name" : "groupCountX" },
1414
{"kind" : "LiteralInteger", "name" : "groupCountY" },
15-
{"kind" : "LiteralInteger", "name" : "groupCountZ" }
15+
{"kind" : "LiteralInteger", "name" : "groupCountZ" },
16+
{"kind" : "LiteralInteger", "name" : "dispatchId" }
1617
]
1718
},
1819
{

‎include/spirv/unified1/spirv.bf‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -212,6 +212,9 @@ namespace Spv
212212
StreamingInterfaceINTEL = 6154,
213213
RegisterMapInterfaceINTEL = 6160,
214214
NamedBarrierCountINTEL = 6417,
215+
MaximumRegistersINTEL = 6461,
216+
MaximumRegistersIdINTEL = 6462,
217+
NamedMaximumRegistersINTEL = 6463,
215218
}
216219

217220
[AllowDuplicates, CRepr] public enum StorageClass
@@ -1157,6 +1160,7 @@ namespace Spv
11571160
RayQueryPositionFetchKHR = 5391,
11581161
AtomicFloat16VectorNV = 5404,
11591162
RayTracingDisplacementMicromapNV = 5409,
1163+
RawAccessChainsNV = 5414,
11601164
SubgroupShuffleINTEL = 5568,
11611165
SubgroupBufferBlockIOINTEL = 5569,
11621166
SubgroupImageBlockIOINTEL = 5570,
@@ -1230,6 +1234,7 @@ namespace Spv
12301234
GroupUniformArithmeticKHR = 6400,
12311235
MaskedGatherScatterINTEL = 6427,
12321236
CacheControlsINTEL = 6441,
1237+
RegisterLimitsINTEL = 6460,
12331238
}
12341239

12351240
[AllowDuplicates, CRepr] public enum RayFlagsShift
@@ -1400,6 +1405,24 @@ namespace Spv
14001405
StreamingINTEL = 3,
14011406
}
14021407

1408+
[AllowDuplicates, CRepr] public enum NamedMaximumNumberOfRegisters
1409+
{
1410+
AutoINTEL = 0,
1411+
}
1412+
1413+
[AllowDuplicates, CRepr] public enum RawAccessChainOperandsShift
1414+
{
1415+
RobustnessPerComponentNV = 0,
1416+
RobustnessPerElementNV = 1,
1417+
}
1418+
1419+
[AllowDuplicates, CRepr] public enum RawAccessChainOperandsMask
1420+
{
1421+
MaskNone = 0,
1422+
RobustnessPerComponentNV = 0x00000001,
1423+
RobustnessPerElementNV = 0x00000002,
1424+
}
1425+
14031426
[AllowDuplicates, CRepr] public enum Op
14041427
{
14051428
OpNop = 0,
@@ -1878,6 +1901,7 @@ namespace Spv
18781901
OpConvertUToSampledImageNV = 5395,
18791902
OpConvertSampledImageToUNV = 5396,
18801903
OpSamplerImageAddressingModeNV = 5397,
1904+
OpRawAccessChainNV = 5398,
18811905
OpSubgroupShuffleINTEL = 5571,
18821906
OpSubgroupShuffleDownINTEL = 5572,
18831907
OpSubgroupShuffleUpINTEL = 5573,

‎include/spirv/unified1/spirv.core.grammar.json‎

Lines changed: 91 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6251,6 +6251,24 @@
62516251
"capabilities" : [ "BindlessTextureNV" ],
62526252
"version" : "None"
62536253
},
6254+
{
6255+
"opname" : "OpRawAccessChainNV",
6256+
"class" : "Memory",
6257+
"opcode" : 5398,
6258+
"operands" : [
6259+
{ "kind" : "IdResultType" },
6260+
{ "kind" : "IdResult" },
6261+
{ "kind" : "IdRef", "name" : "'Base'" },
6262+
{ "kind" : "IdRef", "name" : "'Byte stride'" },
6263+
{ "kind" : "IdRef", "name" : "'Element index'" },
6264+
{ "kind" : "IdRef", "name" : "'Byte offset'" },
6265+
{ "kind" : "RawAccessChainOperands", "quantifier" : "?" }
6266+
],
6267+
"capabilities" : [
6268+
"RawAccessChainsNV"
6269+
],
6270+
"version" : "None"
6271+
},
62546272
{
62556273
"opname" : "OpSubgroupShuffleINTEL",
62566274
"class" : "Group",
@@ -10667,6 +10685,28 @@
1066710685
}
1066810686
]
1066910687
},
10688+
{
10689+
"category" : "BitEnum",
10690+
"kind" : "RawAccessChainOperands",
10691+
"enumerants" : [
10692+
{
10693+
"enumerant" : "None",
10694+
"value" : "0x0000"
10695+
},
10696+
{
10697+
"enumerant" : "RobustnessPerComponentNV",
10698+
"value" : "0x0001",
10699+
"capabilities" : [ "RawAccessChainsNV" ],
10700+
"version" : "None"
10701+
},
10702+
{
10703+
"enumerant" : "RobustnessPerElementNV",
10704+
"value" : "0x0002",
10705+
"capabilities" : [ "RawAccessChainsNV" ],
10706+
"version" : "None"
10707+
}
10708+
]
10709+
},
1067010710
{
1067110711
"category" : "ValueEnum",
1067210712
"kind" : "SourceLanguage",
@@ -11660,6 +11700,33 @@
1166011700
],
1166111701
"capabilities" : [ "VectorComputeINTEL" ],
1166211702
"version" : "None"
11703+
},
11704+
{
11705+
"enumerant" : "MaximumRegistersINTEL",
11706+
"value" : 6461,
11707+
"parameters" : [
11708+
{ "kind" : "LiteralInteger", "name" : "'Number of Registers'" }
11709+
],
11710+
"capabilities" : [ "RegisterLimitsINTEL" ],
11711+
"version" : "None"
11712+
},
11713+
{
11714+
"enumerant" : "MaximumRegistersIdINTEL",
11715+
"value" : 6462,
11716+
"parameters" : [
11717+
{ "kind" : "IdRef", "name" : "'Number of Registers'" }
11718+
],
11719+
"capabilities" : [ "RegisterLimitsINTEL" ],
11720+
"version" : "None"
11721+
},
11722+
{
11723+
"enumerant" : "NamedMaximumRegistersINTEL",
11724+
"value" : 6463,
11725+
"parameters" : [
11726+
{ "kind" : "NamedMaximumNumberOfRegisters", "name" : "'Named Maximum Number of Registers'" }
11727+
],
11728+
"capabilities" : [ "RegisterLimitsINTEL" ],
11729+
"version" : "None"
1166311730
}
1166411731
]
1166511732
},
@@ -16056,6 +16123,12 @@
1605616123
"extensions" : [ "SPV_NV_displacement_micromap" ],
1605716124
"version" : "None"
1605816125
},
16126+
{
16127+
"enumerant" : "RawAccessChainsNV",
16128+
"value" : 5414,
16129+
"extensions" : [ "SPV_NV_raw_access_chains" ],
16130+
"version" : "None"
16131+
},
1605916132
{
1606016133
"enumerant" : "SubgroupShuffleINTEL",
1606116134
"value" : 5568,
@@ -16497,6 +16570,12 @@
1649716570
"value" : 6441,
1649816571
"extensions" : [ "SPV_INTEL_cache_controls" ],
1649916572
"version" : "None"
16573+
},
16574+
{
16575+
"enumerant" : "RegisterLimitsINTEL",
16576+
"value" : 6460,
16577+
"extensions" : [ "SPV_INTEL_maximum_registers" ],
16578+
"version" : "None"
1650016579
}
1650116580
]
1650216581
},
@@ -16734,6 +16813,18 @@
1673416813
}
1673516814
]
1673616815
},
16816+
{
16817+
"category" : "ValueEnum",
16818+
"kind" : "NamedMaximumNumberOfRegisters",
16819+
"enumerants" : [
16820+
{
16821+
"enumerant" : "AutoINTEL",
16822+
"value" : 0,
16823+
"capabilities" : [ "RegisterLimitsINTEL" ],
16824+
"version" : "None"
16825+
}
16826+
]
16827+
},
1673716828
{
1673816829
"category" : "Id",
1673916830
"kind" : "IdResultType",

‎include/spirv/unified1/spirv.cs‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -211,6 +211,9 @@ public enum ExecutionMode
211211
StreamingInterfaceINTEL = 6154,
212212
RegisterMapInterfaceINTEL = 6160,
213213
NamedBarrierCountINTEL = 6417,
214+
MaximumRegistersINTEL = 6461,
215+
MaximumRegistersIdINTEL = 6462,
216+
NamedMaximumRegistersINTEL = 6463,
214217
}
215218

216219
public enum StorageClass
@@ -1156,6 +1159,7 @@ public enum Capability
11561159
RayQueryPositionFetchKHR = 5391,
11571160
AtomicFloat16VectorNV = 5404,
11581161
RayTracingDisplacementMicromapNV = 5409,
1162+
RawAccessChainsNV = 5414,
11591163
SubgroupShuffleINTEL = 5568,
11601164
SubgroupBufferBlockIOINTEL = 5569,
11611165
SubgroupImageBlockIOINTEL = 5570,
@@ -1229,6 +1233,7 @@ public enum Capability
12291233
GroupUniformArithmeticKHR = 6400,
12301234
MaskedGatherScatterINTEL = 6427,
12311235
CacheControlsINTEL = 6441,
1236+
RegisterLimitsINTEL = 6460,
12321237
}
12331238

12341239
public enum RayFlagsShift
@@ -1399,6 +1404,24 @@ public enum StoreCacheControl
13991404
StreamingINTEL = 3,
14001405
}
14011406

1407+
public enum NamedMaximumNumberOfRegisters
1408+
{
1409+
AutoINTEL = 0,
1410+
}
1411+
1412+
public enum RawAccessChainOperandsShift
1413+
{
1414+
RobustnessPerComponentNV = 0,
1415+
RobustnessPerElementNV = 1,
1416+
}
1417+
1418+
public enum RawAccessChainOperandsMask
1419+
{
1420+
MaskNone = 0,
1421+
RobustnessPerComponentNV = 0x00000001,
1422+
RobustnessPerElementNV = 0x00000002,
1423+
}
1424+
14021425
public enum Op
14031426
{
14041427
OpNop = 0,
@@ -1877,6 +1900,7 @@ public enum Op
18771900
OpConvertUToSampledImageNV = 5395,
18781901
OpConvertSampledImageToUNV = 5396,
18791902
OpSamplerImageAddressingModeNV = 5397,
1903+
OpRawAccessChainNV = 5398,
18801904
OpSubgroupShuffleINTEL = 5571,
18811905
OpSubgroupShuffleDownINTEL = 5572,
18821906
OpSubgroupShuffleUpINTEL = 5573,

‎include/spirv/unified1/spirv.h‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -219,6 +219,9 @@ typedef enum SpvExecutionMode_ {
219219
SpvExecutionModeStreamingInterfaceINTEL = 6154,
220220
SpvExecutionModeRegisterMapInterfaceINTEL = 6160,
221221
SpvExecutionModeNamedBarrierCountINTEL = 6417,
222+
SpvExecutionModeMaximumRegistersINTEL = 6461,
223+
SpvExecutionModeMaximumRegistersIdINTEL = 6462,
224+
SpvExecutionModeNamedMaximumRegistersINTEL = 6463,
222225
SpvExecutionModeMax = 0x7fffffff,
223226
} SpvExecutionMode;
224227

@@ -1156,6 +1159,7 @@ typedef enum SpvCapability_ {
11561159
SpvCapabilityRayQueryPositionFetchKHR = 5391,
11571160
SpvCapabilityAtomicFloat16VectorNV = 5404,
11581161
SpvCapabilityRayTracingDisplacementMicromapNV = 5409,
1162+
SpvCapabilityRawAccessChainsNV = 5414,
11591163
SpvCapabilitySubgroupShuffleINTEL = 5568,
11601164
SpvCapabilitySubgroupBufferBlockIOINTEL = 5569,
11611165
SpvCapabilitySubgroupImageBlockIOINTEL = 5570,
@@ -1229,6 +1233,7 @@ typedef enum SpvCapability_ {
12291233
SpvCapabilityGroupUniformArithmeticKHR = 6400,
12301234
SpvCapabilityMaskedGatherScatterINTEL = 6427,
12311235
SpvCapabilityCacheControlsINTEL = 6441,
1236+
SpvCapabilityRegisterLimitsINTEL = 6460,
12321237
SpvCapabilityMax = 0x7fffffff,
12331238
} SpvCapability;
12341239

@@ -1397,6 +1402,23 @@ typedef enum SpvStoreCacheControl_ {
13971402
SpvStoreCacheControlMax = 0x7fffffff,
13981403
} SpvStoreCacheControl;
13991404

1405+
typedef enum SpvNamedMaximumNumberOfRegisters_ {
1406+
SpvNamedMaximumNumberOfRegistersAutoINTEL = 0,
1407+
SpvNamedMaximumNumberOfRegistersMax = 0x7fffffff,
1408+
} SpvNamedMaximumNumberOfRegisters;
1409+
1410+
typedef enum SpvRawAccessChainOperandsShift_ {
1411+
SpvRawAccessChainOperandsRobustnessPerComponentNVShift = 0,
1412+
SpvRawAccessChainOperandsRobustnessPerElementNVShift = 1,
1413+
SpvRawAccessChainOperandsMax = 0x7fffffff,
1414+
} SpvRawAccessChainOperandsShift;
1415+
1416+
typedef enum SpvRawAccessChainOperandsMask_ {
1417+
SpvRawAccessChainOperandsMaskNone = 0,
1418+
SpvRawAccessChainOperandsRobustnessPerComponentNVMask = 0x00000001,
1419+
SpvRawAccessChainOperandsRobustnessPerElementNVMask = 0x00000002,
1420+
} SpvRawAccessChainOperandsMask;
1421+
14001422
typedef enum SpvOp_ {
14011423
SpvOpNop = 0,
14021424
SpvOpUndef = 1,
@@ -1874,6 +1896,7 @@ typedef enum SpvOp_ {
18741896
SpvOpConvertUToSampledImageNV = 5395,
18751897
SpvOpConvertSampledImageToUNV = 5396,
18761898
SpvOpSamplerImageAddressingModeNV = 5397,
1899+
SpvOpRawAccessChainNV = 5398,
18771900
SpvOpSubgroupShuffleINTEL = 5571,
18781901
SpvOpSubgroupShuffleDownINTEL = 5572,
18791902
SpvOpSubgroupShuffleUpINTEL = 5573,
@@ -2608,6 +2631,7 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy
26082631
case SpvOpConvertUToSampledImageNV: *hasResult = true; *hasResultType = true; break;
26092632
case SpvOpConvertSampledImageToUNV: *hasResult = true; *hasResultType = true; break;
26102633
case SpvOpSamplerImageAddressingModeNV: *hasResult = false; *hasResultType = false; break;
2634+
case SpvOpRawAccessChainNV: *hasResult = true; *hasResultType = true; break;
26112635
case SpvOpSubgroupShuffleINTEL: *hasResult = true; *hasResultType = true; break;
26122636
case SpvOpSubgroupShuffleDownINTEL: *hasResult = true; *hasResultType = true; break;
26132637
case SpvOpSubgroupShuffleUpINTEL: *hasResult = true; *hasResultType = true; break;

0 commit comments

Comments
 (0)