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marcanmarcan
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cpu_regs: Add more chicken bit names
These are from a public Apple source that shall remain unidentified (because it's utterly silly that they keep trying to hide these). Signed-off-by: Hector Martin <[email protected]>
1 parent ee0667e commit f61e5d4

4 files changed

Lines changed: 67 additions & 53 deletions

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‎src/chickens_avalanche.c‎

Lines changed: 18 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,10 @@
55

66
static void init_common_avalanche(void)
77
{
8-
reg_mask(SYS_IMP_APL_HID1, HID1_AVL_UNK42_MASK, HID1_AVL_UNK42(1));
9-
reg_mask(SYS_IMP_APL_HID1, HID1_AVL_UNK22_MASK, HID1_AVL_UNK22(3));
8+
reg_mask(SYS_IMP_APL_HID1, HID1_ZCL_RF_MISPREDICT_THRESHOLD_MASK,
9+
HID1_ZCL_RF_MISPREDICT_THRESHOLD(1));
10+
reg_mask(SYS_IMP_APL_HID1, HID1_ZCL_RF_RESTART_THRESHOLD_MASK,
11+
HID1_ZCL_RF_RESTART_THRESHOLD(3));
1012

1113
reg_set(SYS_IMP_APL_HID11, HID11_DISABLE_LD_NT_WIDGET);
1214

@@ -15,24 +17,26 @@ static void init_common_avalanche(void)
1517
// "configure dummy cycles to work around incorrect temp sensor readings on
1618
// NEX power gating" (maybe)
1719
reg_mask(SYS_IMP_APL_HID13,
18-
HID13_AVL_UNK0_MASK | HID13_AVL_UNK7_MASK | HID13_PRE_CYCLES_MASK |
19-
HID13_AVL_UNK26_MASK | HID13_AVL_UNK30_MASK | HID13_AVL_UNK34_MASK |
20-
HID13_AVL_UNK38_MASK | HID13_AVL_UNK42_MASK | HID13_AVL_UNK46_MASK |
21-
HID13_AVL_UNK50_MASK | HID13_RESET_CYCLE_COUNT_MASK,
22-
HID13_AVL_UNK0(8) | HID13_AVL_UNK7(8) | HID13_PRE_CYCLES(1) | HID13_AVL_UNK26(4) |
23-
HID13_AVL_UNK30(4) | HID13_AVL_UNK34(4) | HID13_AVL_UNK38(4) | HID13_AVL_UNK42(4) |
24-
HID13_AVL_UNK46(4) | HID13_AVL_UNK50(4) | HID13_RESET_CYCLE_COUNT(0));
25-
26-
// No idea what the correct name for these registers is
27-
reg_mask(s3_0_c15_c0_3, GENMASK(7, 0) | GENMASK(43, 36), (0x1aULL << 0) | (0x1fULL << 36));
28-
reg_mask(s3_0_c15_c0_4, GENMASK(15, 8), (0x1fULL << 8));
20+
HID13_POST_OFF_CYCLES_MASK | HID13_POST_ON_CYCLES_MASK | HID13_PRE_CYCLES_MASK |
21+
HID13_GROUP0_FF1_DELAY_MASK | HID13_GROUP0_FF2_DELAY_MASK |
22+
HID13_GROUP0_FF3_DELAY_MASK | HID13_GROUP0_FF4_DELAY_MASK |
23+
HID13_GROUP0_FF5_DELAY_MASK | HID13_GROUP0_FF6_DELAY_MASK |
24+
HID13_GROUP0_FF7_DELAY_MASK | HID13_RESET_CYCLES_MASK,
25+
HID13_POST_OFF_CYCLES(8) | HID13_POST_ON_CYCLES(8) | HID13_PRE_CYCLES(1) |
26+
HID13_GROUP0_FF1_DELAY(4) | HID13_GROUP0_FF2_DELAY(4) | HID13_GROUP0_FF3_DELAY(4) |
27+
HID13_GROUP0_FF4_DELAY(4) | HID13_GROUP0_FF5_DELAY(4) | HID13_GROUP0_FF6_DELAY(4) |
28+
HID13_GROUP0_FF7_DELAY(4) | HID13_RESET_CYCLES(0));
29+
30+
reg_mask(SYS_IMP_APL_HID26, HID26_GROUP1_OFFSET_MASK | HID26_GROUP2_OFFSET_MASK,
31+
HID26_GROUP1_OFFSET(26) | HID26_GROUP2_OFFSET(31));
32+
reg_mask(SYS_IMP_APL_HID27, HID27_GROUP3_OFFSET_MASK, HID27_GROUP3_OFFSET(31));
2933
}
3034

3135
static void init_m2_avalanche(void)
3236
{
3337
init_common_avalanche();
3438

35-
reg_mask(SYS_IMP_APL_HID3, HID3_AVL_UNK57_MASK, HID3_AVL_UNK57(0x3c));
39+
reg_mask(SYS_IMP_APL_HID3, HID3_DEV_PCIE_THROTTLE_LIMIT_MASK, HID3_DEV_PCIE_THROTTLE_LIMIT(60));
3640
reg_set(SYS_IMP_APL_HID3, HID3_DEV_PCIE_THROTTLE_ENABLE);
3741
reg_set(SYS_IMP_APL_HID18, HID18_AVL_UNK27 | HID18_AVL_UNK29);
3842
reg_set(SYS_IMP_APL_HID16, HID16_AVL_UNK12);

‎src/chickens_blizzard.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@ void init_m2_blizzard(void)
1212
{
1313
init_common_blizzard();
1414

15-
reg_mask(SYS_IMP_APL_EHID9, EHID9_BLZ_UNK6_MASK, EHID9_BLZ_UNK6(0x3c));
16-
reg_set(SYS_IMP_APL_EHID9, EHID9_DEV_THROTTLE_2_ENABLE);
15+
reg_mask(SYS_IMP_APL_EHID9, EHID9_DEV_2_THROTTLE_LIMIT_MASK, EHID9_DEV_2_THROTTLE_LIMIT(60));
16+
reg_set(SYS_IMP_APL_EHID9, EHID9_DEV_2_THROTTLE_ENABLE);
1717
reg_set(SYS_IMP_APL_EHID18, EHID18_BLZ_UNK34);
1818
}

‎src/chickens_icestorm.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ static void init_common_icestorm(void)
88
// "Sibling Merge in LLC can cause UC load to violate ARM Memory Ordering Rules."
99
reg_set(SYS_IMP_APL_HID5, HID5_DISABLE_FILL_2C_MERGE);
1010

11-
reg_clr(SYS_IMP_APL_EHID9, EHID9_DEV_THROTTLE_2_ENABLE);
11+
reg_clr(SYS_IMP_APL_EHID9, EHID9_DEV_2_THROTTLE_ENABLE);
1212

1313
// "Prevent store-to-load forwarding for UC memory to avoid barrier ordering
1414
// violation"

‎src/cpu_regs.h‎

Lines changed: 46 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -32,16 +32,16 @@
3232
#define HID1_ENABLE_MDSB_STALL_PIPELINE_ECO BIT(58)
3333
#define HID1_ENABLE_BR_KILL_LIMIT BIT(60)
3434

35-
#define HID1_AVL_UNK22_MASK GENMASK(23, 22)
36-
#define HID1_AVL_UNK22(x) (((unsigned long)x) << 22)
37-
#define HID1_AVL_UNK42_MASK GENMASK(43, 42)
38-
#define HID1_AVL_UNK42(x) (((unsigned long)x) << 42)
35+
#define HID1_ZCL_RF_RESTART_THRESHOLD_MASK GENMASK(23, 22)
36+
#define HID1_ZCL_RF_RESTART_THRESHOLD(x) (((unsigned long)x) << 22)
37+
#define HID1_ZCL_RF_MISPREDICT_THRESHOLD_MASK GENMASK(43, 42)
38+
#define HID1_ZCL_RF_MISPREDICT_THRESHOLD(x) (((unsigned long)x) << 42)
3939

40-
#define SYS_IMP_APL_HID3 sys_reg(3, 0, 15, 3, 0)
41-
#define HID3_DISABLE_ARBITER_FIX_BIF_CRD BIT(44)
42-
#define HID3_AVL_UNK57_MASK GENMASK(62, 57)
43-
#define HID3_AVL_UNK57(x) (((unsigned long)x) << 57)
44-
#define HID3_DEV_PCIE_THROTTLE_ENABLE BIT(63)
40+
#define SYS_IMP_APL_HID3 sys_reg(3, 0, 15, 3, 0)
41+
#define HID3_DISABLE_ARBITER_FIX_BIF_CRD BIT(44)
42+
#define HID3_DEV_PCIE_THROTTLE_LIMIT_MASK GENMASK(62, 57)
43+
#define HID3_DEV_PCIE_THROTTLE_LIMIT(x) (((unsigned long)x) << 57)
44+
#define HID3_DEV_PCIE_THROTTLE_ENABLE BIT(63)
4545

4646
#define SYS_IMP_APL_HID4 sys_reg(3, 0, 15, 4, 0)
4747
#define SYS_IMP_APL_EHID4 sys_reg(3, 0, 15, 4, 1)
@@ -72,10 +72,10 @@
7272
#define HID9_FIX_BUG_51667805 BIT(48)
7373
#define HID9_FIX_BUG_55719865 BIT(55)
7474

75-
#define SYS_IMP_APL_EHID9 sys_reg(3, 0, 15, 9, 1)
76-
#define EHID9_DEV_THROTTLE_2_ENABLE BIT(5)
77-
#define EHID9_BLZ_UNK6_MASK GENMASK(11, 6)
78-
#define EHID9_BLZ_UNK6(x) (((unsigned long)x) << 6)
75+
#define SYS_IMP_APL_EHID9 sys_reg(3, 0, 15, 9, 1)
76+
#define EHID9_DEV_2_THROTTLE_ENABLE BIT(5)
77+
#define EHID9_DEV_2_THROTTLE_LIMIT_MASK GENMASK(11, 6)
78+
#define EHID9_DEV_2_THROTTLE_LIMIT(x) (((unsigned long)x) << 6)
7979

8080
#define SYS_IMP_APL_HID10 sys_reg(3, 0, 15, 10, 0)
8181
#define SYS_IMP_APL_EHID10 sys_reg(3, 0, 15, 10, 1)
@@ -86,29 +86,29 @@
8686
#define HID11_ENABLE_FIX_UC_55719865 BIT(15)
8787
#define HID11_DISABLE_LD_NT_WIDGET BIT(59)
8888

89-
#define SYS_IMP_APL_HID13 sys_reg(3, 0, 15, 14, 0)
90-
#define HID13_AVL_UNK0(x) (((unsigned long)x))
91-
#define HID13_AVL_UNK0_MASK GENMASK(6, 0)
92-
#define HID13_AVL_UNK7(x) (((unsigned long)x) << 7)
93-
#define HID13_AVL_UNK7_MASK GENMASK(13, 7)
94-
#define HID13_PRE_CYCLES(x) (((unsigned long)x) << 14)
95-
#define HID13_PRE_CYCLES_MASK GENMASK(17, 14)
96-
#define HID13_AVL_UNK26(x) (((unsigned long)x) << 26)
97-
#define HID13_AVL_UNK26_MASK GENMASK(29, 26)
98-
#define HID13_AVL_UNK30(x) (((unsigned long)x) << 30)
99-
#define HID13_AVL_UNK30_MASK GENMASK(33, 30)
100-
#define HID13_AVL_UNK34(x) (((unsigned long)x) << 34)
101-
#define HID13_AVL_UNK34_MASK GENMASK(37, 34)
102-
#define HID13_AVL_UNK38(x) (((unsigned long)x) << 38)
103-
#define HID13_AVL_UNK38_MASK GENMASK(41, 38)
104-
#define HID13_AVL_UNK42(x) (((unsigned long)x) << 42)
105-
#define HID13_AVL_UNK42_MASK GENMASK(45, 42)
106-
#define HID13_AVL_UNK46(x) (((unsigned long)x) << 46)
107-
#define HID13_AVL_UNK46_MASK GENMASK(49, 46)
108-
#define HID13_AVL_UNK50(x) (((unsigned long)x) << 50)
109-
#define HID13_AVL_UNK50_MASK GENMASK(53, 50)
110-
#define HID13_RESET_CYCLE_COUNT(x) (((unsigned long)x) << 60)
111-
#define HID13_RESET_CYCLE_COUNT_MASK (0xFUL << 60)
89+
#define SYS_IMP_APL_HID13 sys_reg(3, 0, 15, 14, 0)
90+
#define HID13_POST_OFF_CYCLES(x) (((unsigned long)x))
91+
#define HID13_POST_OFF_CYCLES_MASK GENMASK(6, 0)
92+
#define HID13_POST_ON_CYCLES(x) (((unsigned long)x) << 7)
93+
#define HID13_POST_ON_CYCLES_MASK GENMASK(13, 7)
94+
#define HID13_PRE_CYCLES(x) (((unsigned long)x) << 14)
95+
#define HID13_PRE_CYCLES_MASK GENMASK(17, 14)
96+
#define HID13_GROUP0_FF1_DELAY(x) (((unsigned long)x) << 26)
97+
#define HID13_GROUP0_FF1_DELAY_MASK GENMASK(29, 26)
98+
#define HID13_GROUP0_FF2_DELAY(x) (((unsigned long)x) << 30)
99+
#define HID13_GROUP0_FF2_DELAY_MASK GENMASK(33, 30)
100+
#define HID13_GROUP0_FF3_DELAY(x) (((unsigned long)x) << 34)
101+
#define HID13_GROUP0_FF3_DELAY_MASK GENMASK(37, 34)
102+
#define HID13_GROUP0_FF4_DELAY(x) (((unsigned long)x) << 38)
103+
#define HID13_GROUP0_FF4_DELAY_MASK GENMASK(41, 38)
104+
#define HID13_GROUP0_FF5_DELAY(x) (((unsigned long)x) << 42)
105+
#define HID13_GROUP0_FF5_DELAY_MASK GENMASK(45, 42)
106+
#define HID13_GROUP0_FF6_DELAY(x) (((unsigned long)x) << 46)
107+
#define HID13_GROUP0_FF6_DELAY_MASK GENMASK(49, 46)
108+
#define HID13_GROUP0_FF7_DELAY(x) (((unsigned long)x) << 50)
109+
#define HID13_GROUP0_FF7_DELAY_MASK GENMASK(53, 50)
110+
#define HID13_RESET_CYCLES(x) (((unsigned long)x) << 60)
111+
#define HID13_RESET_CYCLES_MASK (0xFUL << 60)
112112

113113
#define SYS_IMP_APL_HID16 sys_reg(3, 0, 15, 15, 2)
114114
#define HID16_AVL_UNK12 BIT(12)
@@ -140,6 +140,16 @@
140140
#define HID21_DISABLE_CDP_REPLY_PURGED_TRANSACTION BIT(34)
141141
#define HID21_AVL_UNK52 BIT(52)
142142

143+
#define SYS_IMP_APL_HID26 sys_reg(3, 0, 15, 0, 3)
144+
#define HID26_GROUP1_OFFSET(x) (((unsigned long)x) << 0)
145+
#define HID26_GROUP1_OFFSET_MASK (0xffUL << 0)
146+
#define HID26_GROUP2_OFFSET(x) (((unsigned long)x) << 36)
147+
#define HID26_GROUP2_OFFSET_MASK (0xffUL << 36)
148+
149+
#define SYS_IMP_APL_HID27 sys_reg(3, 0, 15, 0, 4)
150+
#define HID27_GROUP3_OFFSET(x) (((unsigned long)x) << 8)
151+
#define HID27_GROUP3_OFFSET_MASK (0xffUL << 8)
152+
143153
#define SYS_IMP_APL_PMCR0 sys_reg(3, 1, 15, 0, 0)
144154
#define PMCR0_CNT_EN_MASK (MASK(8) | GENMASK(33, 32))
145155
#define PMCR0_IMODE_OFF (0 << 8)

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