|
| 1 | +from m1n1.trace import Tracer |
| 2 | +from m1n1.trace.dart import DARTTracer |
| 3 | +from m1n1.utils import * |
| 4 | +import struct |
| 5 | + |
| 6 | + |
| 7 | +class BTBAR0Regs(RegMap): |
| 8 | + IMG_DOORBELL = 0x140, Register32 |
| 9 | + RTI_CONTROL = 0x144, Register32 |
| 10 | + RTI_SLEEP_CONTROL = 0x150, Register32 |
| 11 | + DOORBELL_6 = 0x154, Register32 |
| 12 | + DOORBELL_05 = 0x174, Register32 |
| 13 | + |
| 14 | + BTI_MSI_LO = 0x580, Register32 |
| 15 | + BTI_MSI_HI = 0x584, Register32 |
| 16 | + REG_24 = 0x588, Register32 |
| 17 | + HOST_WINDOW_LO = 0x590, Register32 |
| 18 | + HOST_WINDOW_HI = 0x594, Register32 |
| 19 | + HOST_WINDOW_SZ = 0x598, Register32 |
| 20 | + RTI_IMG_LO = 0x5a0, Register32 |
| 21 | + RTI_IMG_HI = 0x5a4, Register32 |
| 22 | + RTI_IMG_SZ = 0x5a8, Register32 |
| 23 | + REG_21 = 0x610, Register32 |
| 24 | + |
| 25 | + AXI2AHB_ERR_LOG_STATUS = 0x1908, Register32 |
| 26 | + |
| 27 | + CHIPCOMMON_CHIP_STATUS = 0x302c, Register32 |
| 28 | + |
| 29 | + APBBRIDGECB0_ERR_LOG_STATUS = 0x5908, Register32 |
| 30 | + APBBRIDGECB0_ERR_ADDR_LO = 0x590c, Register32 |
| 31 | + APBBRIDGECB0_ERR_ADDR_HI = 0x5910, Register32 |
| 32 | + APBBRIDGECB0_ERR_MASTER_ID = 0x5914, Register32 |
| 33 | + |
| 34 | + DOORBELL_UNK = irange(0x6620, 7, 4), Register32 |
| 35 | + |
| 36 | + |
| 37 | +class BTBAR1Regs(RegMap): |
| 38 | + REG_0 = 0x20044c, Register32 |
| 39 | + RTI_GET_CAPABILITY = 0x200450, Register32 |
| 40 | + BOOTSTAGE = 0x200454, Register32 |
| 41 | + RTI_GET_STATUS = 0x20045c, Register32 |
| 42 | + |
| 43 | + REG_7 = 0x200464, Register32 |
| 44 | + |
| 45 | + IMG_ADDR_LO = 0x200478, Register32 |
| 46 | + IMG_ADDR_HI = 0x20047c, Register32 |
| 47 | + IMG_ADDR_SZ = 0x200480, Register32 |
| 48 | + BTI_EXITCODE_RTI_IMG_RESPONSE = 0x200488, Register32 |
| 49 | + RTI_CONTEXT_LO = 0x20048c, Register32 |
| 50 | + RTI_CONTEXT_HI = 0x200490, Register32 |
| 51 | + RTI_WINDOW_LO = 0x200494, Register32 |
| 52 | + RTI_WINDOW_HI = 0x200498, Register32 |
| 53 | + RTI_WINDOW_SZ = 0x20049c, Register32 |
| 54 | + |
| 55 | + RTI_MSI_LO = 0x2004f8, Register32 |
| 56 | + RTI_MSI_HI = 0x2004fc, Register32 |
| 57 | + RTI_MSI_DATA = 0x200500, Register32 |
| 58 | + |
| 59 | + REG_14 = 0x20054c, Register32 |
| 60 | + |
| 61 | + |
| 62 | +class MemRangeTracer(Tracer): |
| 63 | + REGMAPS = [] |
| 64 | + REGRANGES = [] |
| 65 | + NAMES = [] |
| 66 | + PREFIXES = [] |
| 67 | + |
| 68 | + def __init__(self, hv, verbose=False): |
| 69 | + super().__init__(hv, verbose=verbose, ident=type(self).__name__) |
| 70 | + |
| 71 | + @classmethod |
| 72 | + def _reloadcls(cls): |
| 73 | + cls.REGMAPS = [i._reloadcls() if i else None for i in cls.REGMAPS] |
| 74 | + return super()._reloadcls() |
| 75 | + |
| 76 | + def start(self): |
| 77 | + for i in range(len(self.REGRANGES)): |
| 78 | + if i >= len(self.REGMAPS) or (regmap := self.REGMAPS[i]) is None: |
| 79 | + continue |
| 80 | + prefix = name = None |
| 81 | + if i < len(self.NAMES): |
| 82 | + name = self.NAMES[i] |
| 83 | + if i < len(self.PREFIXES): |
| 84 | + prefix = self.PREFIXES[i] |
| 85 | + |
| 86 | + start, size = self.REGRANGES[i] |
| 87 | + self.trace_regmap(start, size, regmap, name=name, prefix=prefix) |
| 88 | + |
| 89 | + |
| 90 | +class BTTracer(MemRangeTracer): |
| 91 | + DEFAULT_MODE = TraceMode.ASYNC |
| 92 | + REGMAPS = [BTBAR0Regs, BTBAR1Regs] |
| 93 | + # FIXME this is kinda a hack |
| 94 | + REGRANGES = [(0x5c2410000, 0x8000), (0x5c2000000, 0x400000)] |
| 95 | + NAMES = ['BAR0', 'BAR1'] |
| 96 | + |
| 97 | + def __init__(self, hv, dart_tracer): |
| 98 | + super().__init__(hv, verbose=3) |
| 99 | + self.dart_tracer = dart_tracer |
| 100 | + |
| 101 | + |
| 102 | +BTTracer = BTTracer._reloadcls() |
| 103 | + |
| 104 | +dart_tracer = DARTTracer(hv, "/arm-io/dart-apcie0", verbose=1) |
| 105 | +# do not start, clock gates aren't enabled yet |
| 106 | +print(dart_tracer) |
| 107 | + |
| 108 | +bt_tracer = BTTracer(hv, dart_tracer) |
| 109 | +bt_tracer.start() |
| 110 | +print(bt_tracer) |
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