fix opcodes not emulated

Signed-off-by: R <[email protected]>

Author: ArcaneNibble

src/hv_vm.c

@@ -644,6 +644,8 @@ static bool emulate_store(struct exc_info *ctx, u32 insn, u64 *val, u64 *width)
 
     regs[31] = 0;
 
+    union simd_reg simd[32];
+
     u64 mask = 0xffffffffffffffffUL;
 
     if (*width < 3)
@@ -657,6 +659,12 @@ static bool emulate_store(struct exc_info *ctx, u32 insn, u64 *val, u64 *width)
     } else if ((insn & 0x3fc00000) == 0x39000000) {
         // STRx (immediate) Unsigned offset
         *val = regs[Rt] & mask;
+    } else if ((insn & 0x3fc00000) == 0x3d800000) {
+        // STR Q (immediate) Unsigned offset, SIMD&FP, 128-bit
+        get_simd_state(simd);
+        val[0] = simd[Rt].d[0];
+        val[1] = simd[Rt].d[1];
+        *width = 4;
     } else if ((insn & 0x3fe04c00) == 0x38204800) {
         // STRx (register)
         *val = regs[Rt] & mask;
@@ -667,6 +675,16 @@ static bool emulate_store(struct exc_info *ctx, u32 insn, u64 *val, u64 *width)
         val[0] = regs[Rt];
         val[1] = regs[Rt2];
         *width = 4;
+    } else if ((insn & 0xffc00000) == 0xad000000) {
+        // STP (Signed offset, SIMD&FP), 256-bit
+        CHECK_RN;
+        get_simd_state(simd);
+        u64 Rt2 = (insn >> 10) & 0x1f;
+        val[0] = simd[Rt].d[0];
+        val[1] = simd[Rt].d[1];
+        val[2] = simd[Rt2].d[0];
+        val[3] = simd[Rt2].d[1];
+        *width = 4;
     } else if ((insn & 0x3fe00c00) == 0x38000000) {
         // STURx (unscaled)
         *val = regs[Rt] & mask;
@@ -837,7 +855,7 @@ bool hv_handle_dabort(struct exc_info *ctx)
     }
 
     u32 insn = read32(elr_pa);
-    u64 val[2] = {0, 0};
+    u64 val[4] = {0, 0, 0, 0};
     u64 width;
 
     hv_wdt_breadcrumb('2');