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pcie: Add initial t8122 support
Signed-off-by: Alyssa Milburn <[email protected]>
1 parent 46fc983 commit ba6835d

1 file changed

Lines changed: 65 additions & 15 deletions

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‎src/pcie.c‎

Lines changed: 65 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -137,6 +137,7 @@ const struct fuse_bits pcie_fuse_bits_t8112[] = {
137137
enum apcie_type {
138138
APCIE_T81XX = 0,
139139
APCIE_T602X = 1,
140+
APCIE_T8122 = 2,
140141
};
141142

142143
struct reg_info {
@@ -177,6 +178,18 @@ static const struct reg_info regs_t602x = {
177178
.fuse_idx = 7,
178179
};
179180

181+
static const struct reg_info regs_t8122 = {
182+
.type = APCIE_T8122,
183+
.shared_reg_count = 7,
184+
.config_idx = 0,
185+
.rc_idx = 1,
186+
.phy_common_idx = 2,
187+
.phy_idx = 2,
188+
.phy_ip_idx = 3,
189+
.axi_idx = 4,
190+
.fuse_idx = 5,
191+
};
192+
180193
static bool pcie_initialized = false;
181194

182195
enum PCIE_CONTROLLERS {
@@ -236,6 +249,10 @@ static int pcie_init_controller(int controller, const char *path)
236249
fuse_bits = pcie_fuse_bits_t8112;
237250
state->pcie_regs = &regs_t8xxx_t600x;
238251
printf("pcie: Initializing t8112 PCIe controller\n");
252+
} else if (adt_is_compatible(adt, adt_offset, "apcie,t8122")) {
253+
fuse_bits = NULL;
254+
state->pcie_regs = &regs_t8122;
255+
printf("pcie: Initializing t8122 PCIe controller\n");
239256
} else if (adt_is_compatible(adt, adt_offset, "apcie,t6020")) {
240257
fuse_bits = NULL;
241258
state->pcie_regs = &regs_t602x;
@@ -290,8 +307,8 @@ static int pcie_init_controller(int controller, const char *path)
290307
if (state->pcie_regs->phy_common_idx != -1) {
291308
if (adt_get_reg(adt, adt_path, "reg", state->pcie_regs->phy_common_idx,
292309
&state->phy_common_base, NULL)) {
293-
printf("pcie: Error getting reg with index %d for %s\n", state->pcie_regs->phy_idx,
294-
path);
310+
printf("pcie: Error getting reg with index %d for %s\n",
311+
state->pcie_regs->phy_common_idx, path);
295312
return -1;
296313
}
297314
} else {
@@ -310,6 +327,13 @@ static int pcie_init_controller(int controller, const char *path)
310327
return -1;
311328
}
312329

330+
if (state->pcie_regs->type == APCIE_T8122) {
331+
// The T8122 init seems very similar to the T602X, with different offsets,
332+
// and with reg[2], [3] and [4] coalesced to reg[2] in the ADT.
333+
state->phy_base[0] = state->phy_base[0] + 0x8000;
334+
state->phy_common_base += 0x4000;
335+
}
336+
313337
for (int phy = 1; phy < state->num_phys; phy++) {
314338
state->phy_base[phy] = state->phy_base[0] + PHY_STRIDE * phy;
315339
state->phy_ip_base[phy] = state->phy_ip_base[0] + PHYIP_STRIDE * phy;
@@ -399,7 +423,7 @@ static int pcie_init_controller(int controller, const char *path)
399423
if (state->pcie_regs->type == APCIE_T81XX) {
400424
set32(state->rc_base + APCIE_PHYIF_CTRL, APCIE_PHYIF_CTRL_RUN);
401425
udelay(1);
402-
} else if (state->pcie_regs->type == APCIE_T602X) {
426+
} else if (state->pcie_regs->type == APCIE_T602X || state->pcie_regs->type == APCIE_T8122) {
403427
set32(state->phy_base[phy] + 4, 0x01);
404428
}
405429

@@ -433,12 +457,12 @@ static int pcie_init_controller(int controller, const char *path)
433457
return -1;
434458
}
435459

436-
if (state->pcie_regs->type == APCIE_T602X) {
460+
if (state->pcie_regs->type == APCIE_T602X || state->pcie_regs->type == APCIE_T8122) {
437461
set32(state->phy_base[phy] + 4, 0x10);
438462
}
439463
}
440464

441-
if (state->pcie_regs->type == APCIE_T602X) {
465+
if (state->pcie_regs->type == APCIE_T602X || state->pcie_regs->type == APCIE_T8122) {
442466
mask32(state->phy_common_base + APCIE_PHYCMN_CLK, APCIE_PHYCMN_CLK_MODE,
443467
FIELD_PREP(APCIE_PHYCMN_CLK_MODE, 1));
444468

@@ -449,17 +473,23 @@ static int pcie_init_controller(int controller, const char *path)
449473
return -1;
450474
}
451475
for (int phy = 0; phy < state->num_phys; phy++) {
452-
set32(state->phy_base[phy] + APCIE_PHY_CTRL, 0x300);
476+
if (state->pcie_regs->type == APCIE_T602X) {
477+
set32(state->phy_base[phy] + APCIE_PHY_CTRL, 0x300);
478+
} else if (state->pcie_regs->type == APCIE_T8122) {
479+
set32(state->phy_base[phy] + APCIE_PHY_CTRL, 0x200);
480+
}
453481
}
454482
write32(state->rc_base + 0x54, 0x140);
455483
write32(state->rc_base + 0x50, 0x1);
456484
if (poll32(state->rc_base + 0x58, 1, 1, 250000)) {
457485
printf("pcie: Failed to initialize RC thing\n");
458486
return -1;
459487
}
460-
if (controller == APCIE)
461-
clear32(state->rc_base + 0x3c, 0x1);
462-
pmgr_adt_power_disable_index(path, 1);
488+
if (state->pcie_regs->type == APCIE_T602X) {
489+
if (controller == APCIE)
490+
clear32(state->rc_base + 0x3c, 0x1);
491+
pmgr_adt_power_disable_index(path, 1);
492+
}
463493
}
464494

465495
for (u32 port = 0; port < state->port_count; port++) {
@@ -529,22 +559,38 @@ static int pcie_init_controller(int controller, const char *path)
529559
// ??????
530560
if (controller == APCIE)
531561
write32(state->port_base[port] + 0x10, 0x2);
562+
}
563+
564+
if (state->pcie_regs->type == APCIE_T602X || state->pcie_regs->type == APCIE_T8122) {
532565
write32(state->port_base[port] + 0x88, 0x110);
533566
write32(state->port_base[port] + 0x100, 0xffffffff);
534567
write32(state->port_base[port] + 0x148, 0xffffffff);
535568
write32(state->port_base[port] + 0x210, 0xffffffff);
536569
write32(state->port_base[port] + 0x80, 0x0);
537570
write32(state->port_base[port] + 0x84, 0x0);
538-
write32(state->port_base[port] + 0x104, 0x7fffffff);
571+
if (state->pcie_regs->type == APCIE_T602X) {
572+
write32(state->port_base[port] + 0x104, 0x7fffffff);
573+
} else if (state->pcie_regs->type == APCIE_T8122) {
574+
write32(state->port_base[port] + 0x104, 0xfffffff0);
575+
}
539576
write32(state->port_base[port] + 0x124, 0x100);
540577
write32(state->port_base[port] + 0x16c, 0x0);
541578
write32(state->port_base[port] + 0x13c, 0x10);
542579
write32(state->port_base[port] + 0x800, 0x100100);
543580
write32(state->port_base[port] + 0x808, 0x1000ff);
544581
write32(state->port_base[port] + 0x82c, 0x0);
545-
for (int i = 0; i < 512; i++)
582+
if (state->pcie_regs->type == APCIE_T8122) {
583+
for (int i = 0; i < 16; i++) {
584+
write32(state->port_base[port] + 0x3000 + 4 * i, 0);
585+
}
586+
}
587+
// It seems fine to write the full range (512) here.
588+
for (int i = 0; i < 512; i++) {
546589
write32(state->port_base[port] + APCIE_T602X_PORT_MSIMAP + 4 * i, 0);
547-
write32(state->port_base[port] + 0x397c, 0x0);
590+
}
591+
if (state->pcie_regs->type == APCIE_T602X) {
592+
write32(state->port_base[port] + 0x397c, 0x0);
593+
}
548594
if (controller == APCIE)
549595
write32(state->port_base[port] + 0x130, 0x3000000);
550596
else
@@ -553,7 +599,7 @@ static int pcie_init_controller(int controller, const char *path)
553599
write32(state->port_base[port] + 0x144, 0x253770);
554600
write32(state->port_base[port] + 0x21c, 0x0);
555601
write32(state->port_base[port] + 0x834, 0x0);
556-
if (controller != APCIE)
602+
if (controller != APCIE || state->pcie_regs->type == APCIE_T8122)
557603
write32(state->port_base[port] + 0x83c, 0x0);
558604
}
559605

@@ -564,7 +610,7 @@ static int pcie_init_controller(int controller, const char *path)
564610

565611
set32(state->port_base[port] + APCIE_PORT_APPCLK, APCIE_PORT_APPCLK_EN);
566612

567-
if (state->pcie_regs->type == APCIE_T602X) {
613+
if (state->pcie_regs->type == APCIE_T602X || state->pcie_regs->type == APCIE_T8122) {
568614
clear32(state->port_phy_base[port] + APCIE_PHY_CTRL,
569615
APCIE_PHY_CTRL_CLK0REQ | APCIE_PHY_CTRL_CLK1REQ);
570616

@@ -582,7 +628,11 @@ static int pcie_init_controller(int controller, const char *path)
582628
return -1;
583629
}
584630

585-
clear32(state->port_phy_base[port] + APCIE_PHY_CTRL, 0x4000);
631+
if (state->pcie_regs->type == APCIE_T602X) {
632+
clear32(state->port_phy_base[port] + APCIE_PHY_CTRL, 0x4000);
633+
} else if (state->pcie_regs->type == APCIE_T8122) {
634+
clear32(state->port_phy_base[port] + APCIE_PHY_CTRL, 0x10);
635+
}
586636
set32(state->port_phy_base[port] + APCIE_PHY_CTRL, 0x200);
587637
set32(state->port_phy_base[port] + APCIE_PHY_CTRL, 0x400);
588638

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