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11 | 11 |
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12 | 12 | #define CLUSTER_PSTATE_BUSY BIT(31) |
13 | 13 | #define CLUSTER_PSTATE_SET BIT(25) |
14 | | -#define CLUSTER_PSTATE_UNK BIT(20) |
| 14 | +#define CLUSTER_PSTATE_UNK_M2 BIT(22) |
| 15 | +#define CLUSTER_PSTATE_UNK_M1 BIT(20) |
15 | 16 | #define CLUSTER_PSTATE_DESIRED2 GENMASK(16, 12) |
16 | 17 | #define CLUSTER_PSTATE_DESIRED1 GENMASK(4, 0) |
17 | 18 |
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@@ -62,13 +63,26 @@ void cpufreq_fixup_cluster(const struct cluster_t *cluster) |
62 | 63 | { |
63 | 64 | u64 val = read64(cluster->base + CLUSTER_PSTATE); |
64 | 65 |
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65 | | - // Older versions of m1n1 stage 1 erroneously cleared CLUSTER_PSTATE_UNK, so put it back for |
| 66 | + // Older versions of m1n1 stage 1 erroneously cleared CLUSTER_PSTATE_UNK_Mx, so put it back for |
66 | 67 | // firmwares it supported (don't touch anything newer, which includes newer devices). |
67 | 68 | // Also clear the CLUSTER_PSTATE_DESIRED2 field since it doesn't seem to do anything, and isn't |
68 | 69 | // used on newer chips. |
69 | 70 | if (os_firmware.version != V_UNKNOWN && os_firmware.version <= V13_3) { |
70 | | - if (!(val & CLUSTER_PSTATE_UNK) || (val & CLUSTER_PSTATE_DESIRED2)) { |
71 | | - val |= CLUSTER_PSTATE_UNK; |
| 71 | + u64 bits = 0; |
| 72 | + switch (chip_id) { |
| 73 | + case T8103: |
| 74 | + case T6000 ... T6002: |
| 75 | + bits = CLUSTER_PSTATE_UNK_M1; |
| 76 | + break; |
| 77 | + case T8112: |
| 78 | + case T6020 ... T6021: |
| 79 | + bits = CLUSTER_PSTATE_UNK_M2; |
| 80 | + break; |
| 81 | + default: |
| 82 | + return; |
| 83 | + } |
| 84 | + if (!(val & bits) || (val & CLUSTER_PSTATE_DESIRED2)) { |
| 85 | + val |= bits; |
72 | 86 | val &= ~CLUSTER_PSTATE_DESIRED2; |
73 | 87 | printf("cpufreq: Correcting setting for cluster %s\n", cluster->name); |
74 | 88 | write64(cluster->base + CLUSTER_PSTATE, val); |
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