m1n1.fw.agx.channels: Do not require contiguous pages for channel state

Signed-off-by: Asahi Lina <[email protected]>

Author: hoshinolina

proxyclient/m1n1/fw/agx/channels.py

@@ -423,9 +423,8 @@ def __init__(self, u, uat, info, ring_defs, base=None, state_fields=ChannelState
         self.ring_defs = ring_defs
         self.info = info
 
-        self.st_maps = uat.iotranslate(0, info.state_addr, state_fields._SIZE * len(ring_defs))
-        assert len(self.st_maps) == 1
-        self.state_phys = self.st_maps[0][0]
+        self.accessor = uat.ioaccessor(0)
+        self.state_addr = info.state_addr
         self.state = []
         self.rb_base = []
         self.rb_maps = []
@@ -437,7 +436,7 @@ def __init__(self, u, uat, info, ring_defs, base=None, state_fields=ChannelState
         for i, (msg, size, count) in enumerate(ring_defs):
             assert msg.sizeof() == size
 
-            self.state.append(state_fields(self.u, self.state_phys + 0x30 * i))
+            self.state.append(state_fields(self.accessor, self.state_addr + 0x30 * i))
             m = uat.iotranslate(0, p, size * count)
             self.rb_base.append(p)
             self.rb_maps.append(m)

proxyclient/m1n1/hw/uat.py

@@ -333,7 +333,7 @@ def iostream(self, ctx, base, recurse=True):
         return UatStream(self, ctx, base, recurse)
 
     # A read/write register interface like proxy/utils objects that can be used by RegMap
-    def ioaccessor(self, ctx, base):
+    def ioaccessor(self, ctx):
         return UatAccessor(self, ctx)
 
     def iomap(self, ctx, addr, size, **flags):

proxyclient/m1n1/trace/agx.py

@@ -106,16 +106,13 @@ def __init__(self, tracer, info, index):
 
         self.channel = Channel(self.u, self.uat, self.info, channelRings[index], base=base,
                                state_fields=self.STATE_FIELDS)
-        for addr, size in self.channel.st_maps:
-            self.log(f"st_map {addr:#x} ({size:#x})")
         for i in range(self.ring_count):
             for addr, size in self.channel.rb_maps[i]:
                 self.log(f"rb_map[{i}] {addr:#x} ({size:#x})")
 
         self.set_active(self.state.active)
 
-    def state_read(self, evt, regmap=None, prefix=None):
-        off = evt.addr - self.channel.state_phys
+    def state_read(self, evt, regmap=None, prefix=None, off=None):
         ring = off // 0x30
         off = off % 0x30
 
@@ -133,8 +130,7 @@ def state_read(self, evt, regmap=None, prefix=None):
             if self.verbose:
                 self.log(f"RD [{evt.addr:#x}] UNK[{ring}] {off:#x} = {evt.data:#x}")
 
-    def state_write(self, evt, regmap=None, prefix=None):
-        off = evt.addr - self.channel.state_phys
+    def state_write(self, evt, regmap=None, prefix=None, off=None):
         ring = off // 0x30
         off = off % 0x30
 
@@ -187,16 +183,20 @@ def set_active(self, active=True):
                     self.state.tail[ring] = self.channel.state[ring].WRITE_PTR.val
 
             for base in range(0, 0x30 * self.ring_count, 0x30):
-                self.hv.add_tracer(irange(self.channel.state_phys + base + self.RPTR, 4),
+                p = self.uat.iotranslate(0, self.channel.state_addr + base + self.RPTR, 4)[0][0]
+                self.hv.add_tracer(irange(p, 4),
                                    f"ChannelTracer/{self.name}",
                                    mode=TraceMode.SYNC,
                                    read=self.state_read,
-                                   write=self.state_write)
-                self.hv.add_tracer(irange(self.channel.state_phys + base + self.WPTR, 4),
+                                   write=self.state_write,
+                                   off=base + self.RPTR)
+                p = self.uat.iotranslate(0, self.channel.state_addr + base + self.WPTR, 4)[0][0]
+                self.hv.add_tracer(irange(p, 4),
                                    f"ChannelTracer/{self.name}",
                                    mode=TraceMode.SYNC,
                                    read=self.state_read,
-                                   write=self.state_write)
+                                   write=self.state_write,
+                                   off=base + self.WPTR)
         else:
             self.hv.clear_tracers(f"ChannelTracer/{self.name}")
         self.state.active = active